JPS592294A - Test method of memory device - Google Patents

Abstract

PURPOSE:To detect quickly a fault for both address and data system. CONSTITUTION:For instance, it is supposed that the lowest bit of a counter CT1 is stacked to ''1''. Thus an address 1, i.e., address 0001 is read out of a memory MEM1 when an address 0 of a MEM2 is read out. Then the check result of a parity check circuit CH shows an error to detect a fault. Such a stack is equal not only with the lowest bit of the counter CT1 but with any bit position. When a data on the 2nd address (address 1) of the MEM2 is read in case the lowest bit of the CT1 is stacked to ''0'', the data on the 1st address (address 0) is read out of the MEM1. Then a fault is detected by the circuit CH.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a test method for a memory device, and particularly to a test method for detecting address-related and rank-related failures.

[Technology background]

A memory device is roughly divided into a data system for storing data therein, and an address system for determining in which address the data is stored. The reliability of this memory device is extremely important, and it is desired to promptly detect that something is wrong with the fault.

[Conventional technology and problems]

A conventional test of such a memory device is shown in FIG.

That is, data from the control device (including parity pit r)
is sent from the write data line DA.

Also, a memo to accumulate that data! The address on JMEM is sent from the control device via address line AD.

At this time, the address selector SE selects the address line AD and stores the data at the address specified by the control device. Next, the data stored in memo 17M and EM is stored by selecting counter CT with selector SF.
According to the value indicated by the counter CT, the data read out in this manner is checked by the parity e check circuit CH each time.

When a failure occurs in the data system, it can be detected by this parity check circuit CH, but the address system,
For example, a fault on the address line containing control device #ii,
Even if a failure occurs in the counter CT or, although not shown, in the address decoder, it cannot be detected. For example, if a failure occurs in the counter CT, 2
Although there are addresses that are read once and addresses that are never read, the parity check circuit CH'''C does not detect any error.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve such drawbacks and to make it possible to easily detect failures in the data system or removal of damage in the address system.

[Structure of the invention]

In order to achieve the above object, the present invention divides and stores the memory of one word worth of booter machines with an error check bit added, and stores the data of the address specified for writing first and the data of other addresses. The data is stored and lost, and when data is read, all data error checks are performed, and when the data at the address specified for writing is first read, it is compared with the data at the time of writing. .

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows an example of the relationship between memory data and addresses in the embodiment.

In the figure, the same reference numerals as those in the first part indicate the same functions, and the memory M
EMI, MEfv12 kl each has 6 bits and 11 bits, memory M and EM1 have bits b1 to b6 + memory IVIEM2 has bits b1 to b11 and parity PTI.
One word consists of focus, b, ~bll, and PT. These multiplexed memories MEMI and MEM2 are
Of course, the same address is specified and the data is loaded and tracked, and the counter CT for reading is used.
I and Cr2 are installed individually or normally operate in synchronization.

In such a memory device, if a failure occurs in the data system, it can be detected by the parity check circuit CH, as in the past. Therefore, a test performed when a failure occurs in the address system will be described in detail below.

For example, address 0 of memory MEMI contains data containing an even number of ``'1'' values out of 6 bits;
Address 2 OK is 0, in which data containing an odd number of 1's out of 6 bits is written from the control device;
Data containing an odd number of ``1'' values is written to all addresses other than address O of the memory MEM2 from the control 1A location. These data are stored in memory M
EMI, MP; At addresses other than 0 of M2, different data may be written as long as the above conditions are satisfied, but for simplification, the same data may be written.

This example is shown in Figure 3 (Note I) MEMI
Address 0, that is, 0000, contains data 101000'', and address 0 of memory MEM2 contains data 0011.
Data of 01' is written. At other addresses, the memory MEMI contains data "100000".
However, the memory MEM2 has data "001010"
is written. Here, it is assumed that if a fault occurs in the counter, the least significant bit of the counter CTI is stuck at '1' if all the counters are cleared.

In this case, when address 0 of the memory MEM2 shown in FIG. 3 is read out, address 1, that is, address 0001, is read out in the memory MEMI, and the check result by the parity check circuit CH shows no error, so that a fault can be detected. The stack of zeros is the same regardless of whether it occurs at any bit position, not just at the least significant bit of the counter CTI. Next, when the lowest pit of the counter CT1 is stuck at 0'' and the data at the second address (i.e. address 1) of the memory MEM2 shown in FIG. The data at address 0) is read out, and the parity instruction check circuit CH
Faults can be detected by

Regarding the 0'' stack, the combination of data other than address 0 of the memory ME and address 0 of the memory MEM2 is read out, regardless of which focus position is stacked, not just the least significant bit of the counter CTI. If a fault occurs, the parity check circuit CH can detect the fault.Such a fault is the same even if the color data CTI and CT2 are reversed.

In this way, even if a failure occurs in either counter CTI or CT2, it can be easily detected.

Yes, and as described above, it is sufficient if a failure in any one of the counters can be detected.

Further, even if such a failure occurs in the address decoder, it can be detected by the same method as described above. Furthermore, when detecting a failure in the address itself from the control device, any data 'kW' is placed in any address of the memory MEMI or MEM2, and then all remaining addresses are filled with data different from that data. Convolve the data. In this case, if the data is different from the data written to the first address, different data may be written to all remaining addresses, but for simplicity, it is better to write different data to all remaining addresses. The same data may include all bamboo. After this, the data is extracted from the address where the booter was first loaded and compared with the data that was initially loaded.

For example, in the memo 'JMEMI, MEM2, from address 0 to j-, the data shown in FIG. Memories I quality 11. MhlVI2
By the time I got there, it was already midday. Due to this operation, if there is a stack at the address J from the device, the data written first will be lost among the data written to all remaining addresses.・When υjμ is corrected, a mismatched output is obtained from the matching circuit M A 'l', and a fault is detected.

[Effects around 9G] As described above, according to the present invention, even if a fault occurs in either the address system or the data thread, 70 faults can be quickly detected, and the detection means are also complicated. (It is extremely effective and does not require any circuitry.)

[Brief explanation of the drawing]

FIG. 1 shows a conventional example, and FIG. 2 shows an embodiment of the present invention. FIG. 3 is a diagram showing details of data in the memory in FIG. 2. In the figure, MEM is a memory, SE is an address selector, and CT
is a counter, CHU is a parity check circuit, MAT is a verification circuit, and LAT is a latch circuit. Ryo 1 figure

Claims (1)

[Claims] Data for one word with error check pits is divided and stored in multiple memories, and the data at the address specified for writing is stored differently from the data at other addresses, and when reading data, , data error m
- A test method for a memory device characterized in that when all checks are performed and data at an address designated for writing first is read, it is compared with data at the time of convolution.