JPS59227095A - Screening method of semiconductor storage element - Google Patents

Abstract

PURPOSE:To discriminate a non-defective element from a defective element by using two different kinds of erasing conditions, and checking an erasing state of a bit after each erasion. CONSTITUTION:In a step S1, a data is written in all bits. Subsequently, in a step S2, all the bits are erased by erasing voltage VPPE which is weaker than rating, and an erasing pulse width tpw2. Next, in an erasing bit comparing process S3, whether a bit which is above 1-bit was erased or not is checked. At this stage, a chip (characteristic C4 and C5) containing a bit which can be erased by a short time tpw2 can be detected. Subsequently, in a step S4, the bit is erased by a rating erasing condition, and thereafter, a data is written in all bits. In a step S5, all the bits are erased by the erasing voltage VPPE which is weaker than rating, and an erasing pulse width tpw2+2.DELTAtpw, and next, in an erasing bit comparing process S6, whether all the bits was erased or not is checked. In this way, the chip (characteristic C4) in which the distribution of an erasion rate is greatly varied can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for screening charge storage type semiconductor memory elements.

[Background of the invention]

Charge storage type semiconductor memory element (electrically written.

The structure of the storage section of an erasable read-only memory (hereinafter abbreviated as EEP-ROM) is that a charge storage section is provided above the channel of a general V field effect transistor (hereinafter abbreviated as FIT), and charges are accumulated in this. This is done by changing the threshold voltage.

A typical FET that achieves this includes a 70mm wire that is electrically isolated from other circuits between the ordinary FET's substrate and the dart electrode.
- A similar place is formed with a silicon oxide layer and a silicon nitride layer, and the interface or the trap level inside the silicon nitride is used as a charge accumulation (capture) site. There is something to do.

Although the structures of the two are quite different, the basic memory and erasure mechanisms are the same, so the following explanation will mainly focus on the latter.

FIG. 1 is a cross-sectional view of a memory element of an EEP ROM,
Silicon oxide layer 1 and silicon nitride layer 2. Formed from a polycrystalline polysilicon layer 3, a polycrystalline polysilicon layer 3. Silicon nitride layer 2 is covered by silicon oxide layer 1 . The N layer of the substrate is connected to the source S and the drain D, and the P layer is placed opposite to the silicon nitride layer 2 with the silicon oxide layer 1 interposed therebetween. This corresponds to the fact that no information is written in a state where charges are not captured at the interface between the silicon oxide layer 1 and the silicon nitride layer 2 or at the trap level inside the silicon nitride layer. At this time, the dart voltage (Va
B) - drain current (In5) characteristic diagram, vos
The IDS characteristic is in the state of curve 4, and the threshold voltage Vthl is negative.

Information is written by capturing charges (electrons) at the interface between the silicon oxide layer 1 and the silicon nitride layer 2 or at a trap level inside the silicon nitride by some means. For example, a high voltage is applied to the gate G, the substrate, the source S, and the drain D are grounded, and electrons tunnel through the thin silicon oxide layer 1 to trap charges in the trap level. Due to the influence of the trapped charges, the vas ID8 characteristic after writing changes to the state shown by curve 5 in FIG. 2, and the threshold voltage Vtbz increases.

Reading of stored information is performed by grounding the dart G and determining the presence or absence of the tray/current ID8 using the read dart voltage VR in FIG. 2 using a sense amplifier. For example, in a memory element where no information is written, the read dirt voltage vR is greater than the threshold voltage Vtht, so the tray/current IDI+ flows, and in a memory element where information is written, the read dirt voltage VR is equal to the threshold voltage Vth.
2, the tray 7 current ID8 does not flow.

In addition, to erase stored information, all that is needed is to eliminate the charge trapped in the trap level.Contrary to the writing process, by applying a high voltage to the substrate and grounding r-to-G, thin oxide silicon Electrons tunnel through layer 1, allowing erasure.

By the way, if the captured charge leaks, vos in Figure 2
The IDII characteristic is in the state of curve 69, and the threshold voltage vth3 is smaller than the read dirt voltage vR. Then, tray/current ID8 begins to flow,
If this reaches a level that can be detected by the sense amplifier, it means that the written information has been lost.

This point is the end of the life of the memory element. Normally this lifespan is 10
Designed for over 20 years.

However, if there are defects in the thin silicon oxide layer l, or if it contains impurities, further oxidation
If the silicon layer 1 is extremely thin, the captured charges will leak faster than normal leakage and the memory life will be shortened. Also,
Even if the manufacturing process is the same, the amount of trap levels for trapping charges is different, and if this is smaller than the normal one,
The amount of captured charge also decreases, and the memory life becomes shorter accordingly.

A screening method has been developed by the applicant and others to select semiconductor memory elements that have such factors that shorten the memory life. By changing the erasing conditions from a region that is sufficiently weaker than the rated value to a region where all btts of the EEP-ROM are erased, and determining the distribution shape of the erasure rate obtained from the erasure bits of the gEP-ROM, a good product can be detected. , to distinguish between defective products.

FIG. 3 shows an example of this, and shows the erasure rate (number of erased bits/number of bits attempted to be erased: hereinafter abbreviated as E) and erasure rate, which is one of the erase parameters. This figure shows the relationship between the pulse width t and W (erasing characteristics). In Figure 3, C1,
, C2 and C3 indicate the distribution shape of the erasure rate obtained from the three chips, cl indicates that the distribution shape is normal (less variation), and C2 and C3 indicate El (%) from the distribution shape. This shows that there are bits that are removed by the amount of pits (bits that disappear in a shorter time than other bits), and such bits (C2, C3) can be removed as defective products.

By the way, the following problems remain with conventional screening methods.

(1) When determining the relationship between erase conditions and erase rate, a write operation is always required before performing one chip erase.
Normally, this writing takes several tens of seconds. Therefore,
It takes several hours to investigate the erasure characteristics of one chip. It takes a considerable amount of time to plot the obtained results, find and evaluate the distribution shape.

(2) Even if there is a bit that deviates from the distribution shape, if the time it takes for that bit to start disappearing is long (t in C3 in Figure 3)
pwl), there is no problem with the lifespan, and if such things are removed, it will be excessive screening.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems.
An object of the present invention is to provide a screening method capable of non-destructively identifying semiconductor memory elements having factors that shorten memory life.

[Summary of the invention]

In order to achieve the above object, the present invention determines the distribution shape of the erase rate at an early stage, performs an accelerated life test, and determines the distribution shape of semiconductor memory elements that have actually leaked charge and become defective. The erase bit is checked under two types of erase conditions. This makes it a good product.

This is to distinguish between defective products.

In other words, the feature of the present invention is to use a charge storage type semiconductor memory element in which data has been written in advance, perform erasing under sufficiently weaker erase conditions than the rated value, and check whether one or more bits of the semiconductor memory element have been erased. A detecting means and a detecting means for erasing under erasing conditions different from the above-mentioned erasing conditions and checking whether all bits of the semiconductor memory element have been erased are used to distinguish between good products and defective products based on the detection comparison result between the two. This is the point.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 4 and 5. FIG. 4 shows a typical distribution shape of the erasure rate of semiconductor memory elements subjected to an accelerated life test, and FIG. 5 is a flowchart for explaining the screening method of the present invention.

FIG. 4 shows the distribution shape of the erase rate of four semiconductor memory elements (hereinafter abbreviated as chips), and characteristic C4 is the erase characteristic of a chip that has become defective due to charge leakage. Note that the chip with temporality C4 has defective bits that can be erased by 81% between t1w□ and t1w3, so it exhibits a characteristic similar to that of a chip. Comparing the chip with characteristic C4 with other chips, the major differences are (1) characteristic C4,
The C5 chip has the shortest time tpw (
tpwz). (2) There is little variation in the distribution of erasure rates for characteristics c5 to c7, and the difference Δtp7 between the time tpvr when the first bit disappears and the time tpw' until all bits are erased is several ms. , characteristic c
It can be confirmed that the No. 4 chip requires about twice as much time (2Δtpw).

The present invention has developed a screening method as explained in the flowchart of FIG. 5 based on the characteristic results of FIG. 4. That is, in step s1, data is written to all hits. Then, in step S2, all bits are erased using an erase voltage (Vppz) weaker than the rated value and an erase/write width tpW2. Furthermore, in the erase pit comparison Pro 7S S3, 1
Check whether more than one bit has been erased.

At this stage it is possible to detect chips containing bits that can be erased in a short time t pW 2 (characteristics C4 and c5). Next, after erasing with Stella 7'S4 under the rated erasing conditions,
Write data to all bits. And step S5
Erase voltage (Vppg) weaker than the rating, erase pulse width t
All bits are erased with pwz+2·Δtpw, and then it is checked in erased bit comparison process S6 whether all bits have been erased. As a result, it is possible to detect chips f (characteristic c4) in which the distribution of erasure rates varies widely.

It should be noted that the erasure/arm width in Stella fs5 varies depending on the sample lot and product type, and is therefore set appropriately.

As is clear from the above explanation, by using two different types of erase conditions as initial characteristics and checking the erased state of the bit after each erase9, it is possible to distinguish between good and defective chips, and to effectively This is a screening method.

〔Effect of the invention〕

As is clear from the above embodiments, the semiconductor memory element screening method of the present invention uses two different types of erase conditions and checks the erased state of the bit after each erase, thereby determining whether the semiconductor memory element is good or defective. Since it is used to determine good products, compared to conventional screening methods,
This method has advantages such as being able to significantly reduce the time required for screening and preventing excessive screening.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a semiconductor memory element to which the present invention is applied, FIG. 2 is a voltage-current characteristic diagram thereof, and FIG. 3 is a diagram showing the number of erased bits/the number of bits attempted to be erased and the erasure parameters. FIG. 4 is an erasure characteristic diagram showing the relationship between the erasure Hals width, which is one of the characteristics of the erasure characteristics, and FIG.
The figure is a flowchart for explaining one embodiment of the screening method according to the present invention. S2...Chip erase test 1, 83...Erase bit comparison process 1, S5...Chip erase test 2, S6
... Erased bit comparison process 2゜ Agent Patent attorney Tadashi Akimoto Real 1st prisoner Figure 2 GS Figure 3 -560- 5A NG G.

Claims (1)

[Claims] In a method for screening a charge storage type semiconductor memory element in which data has been written in advance, when data is erased from the semiconductor memory element under erase conditions that are sufficiently weaker than the rated value,
a first check detection step for checking whether one or more bits of the semiconductor memory element can be erased; and a first check detection step for checking whether one or more bits of the semiconductor memory element can be erased; 1. A method for screening a semiconductor memory element, comprising: a second check detection step of checking whether the semiconductor memory element is good or defective based on the results of both checks.