JPS59223999A - 情報処理装置 - Google Patents

情報処理装置

Info

Publication number
JPS59223999A
JPS59223999A JP58088157A JP8815783A JPS59223999A JP S59223999 A JPS59223999 A JP S59223999A JP 58088157 A JP58088157 A JP 58088157A JP 8815783 A JP8815783 A JP 8815783A JP S59223999 A JPS59223999 A JP S59223999A
Authority
JP
Japan
Prior art keywords
memory
access
data
time
error correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58088157A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0465417B2 (enrdf_load_stackoverflow
Inventor
Toshihiro Sakai
酒井 利弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58088157A priority Critical patent/JPS59223999A/ja
Publication of JPS59223999A publication Critical patent/JPS59223999A/ja
Publication of JPH0465417B2 publication Critical patent/JPH0465417B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP58088157A 1983-05-19 1983-05-19 情報処理装置 Granted JPS59223999A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58088157A JPS59223999A (ja) 1983-05-19 1983-05-19 情報処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58088157A JPS59223999A (ja) 1983-05-19 1983-05-19 情報処理装置

Publications (2)

Publication Number Publication Date
JPS59223999A true JPS59223999A (ja) 1984-12-15
JPH0465417B2 JPH0465417B2 (enrdf_load_stackoverflow) 1992-10-20

Family

ID=13935084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58088157A Granted JPS59223999A (ja) 1983-05-19 1983-05-19 情報処理装置

Country Status (1)

Country Link
JP (1) JPS59223999A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03182947A (ja) * 1989-08-01 1991-08-08 Digital Equip Corp <Dec> メモリデバイス

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528158A (en) * 1978-08-18 1980-02-28 Casio Comput Co Ltd Calender display unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528158A (en) * 1978-08-18 1980-02-28 Casio Comput Co Ltd Calender display unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03182947A (ja) * 1989-08-01 1991-08-08 Digital Equip Corp <Dec> メモリデバイス

Also Published As

Publication number Publication date
JPH0465417B2 (enrdf_load_stackoverflow) 1992-10-20

Similar Documents

Publication Publication Date Title
US5850530A (en) Method and apparatus for improving bus efficiency by enabling arbitration based upon availability of completion data
US6405271B1 (en) Data flow control mechanism for a bus supporting two-and three-agent transactions
US6173349B1 (en) Shared bus system with transaction and destination ID
US5588122A (en) Universal buffered interface for coupling multiple processors memory units, and I/O interfaces to a common high-speed interconnect
US5428753A (en) Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment
US5265231A (en) Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system
US7716430B2 (en) Separate handling of read and write of read-modify-write
KR930000992B1 (ko) 멀티 프로세서 컴퓨터 시스템상의 인터록 판독 트랜잭션을 개시하기 위한 방법 및 장치
US5301332A (en) Method and apparatus for a dynamic, timed-loop arbitration
US6055598A (en) Arrangement and method for allowing sequence-independent command responses across a computer bus bridge
US6807609B1 (en) Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
US5812803A (en) Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller
US5761532A (en) Direct memory access controller with interface configured to generate wait states
US20160117123A1 (en) Device, method, and computer program for scheduling access requests to shared memory
US4885679A (en) Secure commodity bus
US5923857A (en) Method and apparatus for ordering writeback data transfers on a bus
US5247640A (en) Dual access control system including plural magnetic disk control units and contention control circuitry
US5799161A (en) Method and apparatus for concurrent data routing
JPS59223999A (ja) 情報処理装置
US6412060B2 (en) Method and apparatus for supporting multiple overlapping address spaces on a shared bus
US6799293B2 (en) Sparse byte enable indicator for high speed memory access arbitration method and apparatus
US7779188B2 (en) System and method to reduce memory latency in microprocessor systems connected with a bus
US20100131677A1 (en) Data transfer device and data transfer method
US6839820B1 (en) Method and system for controlling data access between at least two memory arrangements
US8402233B2 (en) Method and apparatus for high throughput mass storage device interface in a microprocessor for handheld systems