JPS59222961A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To make thin an insulating film under a select gate electrode, to thicken an insulating film between a floating gate electrode and the select gate elctrode easily and to enable low program voltage without shortening the life of the storage of a memory by using a silicon nitride film as a gate insulating film for the PACMOS memory. CONSTITUTION:A gate insulating film for a channel L2 under a floating gate electrode 14 is formed by a silicon dioxide film 16 and a silicon nitride film 17, and a gate insulating film for a channel L1 is shaped by a composite film consisting of an insulating film composed of the film 16 and the film 17 formed at the same time as the gate insulating film for the channel L2 and an oxide film 18 of a nitride film shaped at the same time as the floating gate electrode 14 is oxidized. The oxide film 18 of the film 17 formed on the oxidation of the electrode 14 is thinned up to 100Angstrom or less while an oxide film 19 for the floating gate electrode 14 can be thickened simply up to 1000Angstrom or more. Consequently, a gate insulating film for an electrode 15 can be thinned without thinning the oxide film 19 for the floating gate electrode 14 by using silicon nitride films as the gate insulating films. Accordingly, the volatilization of electrons to the electrode 15 from the electrode 14 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate type semiconductor non-volatile memory with low programming voltage and high reliability.

First, we will discuss the low program pressure channel injection floating gate semiconductor non-volatile memory that we previously invented.

Figure 1 shows a conventional semiconductor non-volatile memory (PACM).
FIG. 3 shows a cross-sectional view of an embodiment of the invention (hereinafter referred to as O8). Structure and operating principle of conventional P A O1110El'zN
The case of channel type memory will be explained.

A source region 2 and a drain region 5 in the tq+ region are formed on the surface of the P-type semiconductor substrate 1, and 2 regions are formed between the source and drain regions.
two channel regions, namely channel Ll and channel L
form 2. First channel L+Lt, source region 2
A floating gate electrode 5 is formed on the gate oxide film 7 and in contact with the second channel Lzl t drain region 5 and on the gate oxide film 6. An electrode 4 is formed.The floating gate electrode 4 has strong capacitive coupling through the drain region 5 and the gate insulator 6. Therefore, the potential of the floating gate electrode 4 is applied to the drain region 3. It is determined by the drain voltage VD applied and the amount of charge present in the floating gate electrode 4.

As is clear from FIG. 1, the first channel L.

The surface potential of the second channel L2 is controlled by the selection gate voltage OG stamped on the selection gate electrode 5.The potential of the second channel L2 is controlled by the charge in the floating gate electrode 4 and the drain voltage IFVD. controlled.

This concludes the explanation of the method for reading out the PACM OS message having the structure as shown in FIG. The first channel L.

It is read out by completely inverting the signal, applying a drain pressure VD, and detecting the channel contour between the source and drain regions. That is, when a large number of electrons are contained in the floating gate electrode 4, the conductance of the second channel L2id becomes low, and the conductance of the channel between the source and drain regions also becomes low.

Conversely, if there are no trench 9 electrons in the floating gate electrode 4, the second channel L under the floating gate electrode 4
Since the conductance of the transistor No. 2 is high, the conductance of the channel between the source and drain regions is also high.

Next, a method for fully injecting electrons into the floating gate electrode 4 (hereinafter referred to as programming) will be described.

When a full voltage is applied as the selection gate voltage to the extent that the first channel L1 is inverted, the first surface potential becomes approximately equal to the potential of the source region 2. Moreover, when the programming voltage of the drain region B is applied, the second channel L
The surface potential of 2 is close to the programming voltage. Therefore, a potential gap approximately equal to the programming voltage is generated in the semiconductor surface portion where the first and second channel intersect, and as a result, the channel current is accelerated by the potential gap, and a portion of it enters the floating gate electrode 4.

As explained above, PAC performs programming using the potential gap that occurs between two channel regions.
! In the case of MOS memory, the surface concentration of the first channel Ll is high to form a steep potential gap;
Also, in order to lower the threshold voltage of the first channel L1,
The gate oxide film 7 is formed of a thin film of 200× or less.

However, since the gate oxide film 7 is an oxide film that is formed simultaneously when the floating gate electrode 4 is oxidized, if an attempt is made to make it thin, the oxide film 8 formed on the floating gate electrode 4 will also become thin. As a result, as shown by arrow B in Figure 1, the electrons once programmed are transferred to the oxide film 8.
It has the disadvantage that it can escape through the process, shortening its lifespan.

The present invention has been made to overcome the above-mentioned drawback of reduced reliability due to thinning of the selection gate insulating film. This provides high P A CM OS memory.

FIG. 2 shows a cross-sectional view of the PAOMOS memory according to the first embodiment of the present invention. PAC of the present invention! The case of the fN channel type MOS memory structure will be explained.

N+ conductivity type source region 12 and drain region 13 are formed on the surface of P type semiconductor substrate 110.

On a part of the channel region and the drain region 13 between the source and drain regions, a silicon dioxide film 16 of 100X or less and a silicon nitride film 17 (il-) of 100X or less are formed. As shown in FIG. 2, a floating gate electrode 14 made of polycrystalline silicon is formed.Next, the floating gate electrode 14 is oxidized, and on the silicon dioxide film 18 formed on the nitride film 17 at that time, The selection gate electrode 15 is provided as shown in FIG. 2. As explained above, in the structure of the P AOM OE! The gate insulating film of the first channel L1 under the selection gate electrode 15 is the gate insulating film of the second channel L2. It is formed of a composite film of an insulating film consisting of a silicon dioxide film 16 and a silicon dioxide film 17 formed at the same time, and an oxide film 18 of a silicon dioxide film formed simultaneously when the floating gate electrode 14 is oxidized. The oxide film 18 of the silicon oxide film 17 formed during oxidation of the floating gate electrode 14 is very thin, less than 100X, while the oxide film 19 of the floating gate electrode 14 can be easily made thicker than 1000X. This is because the oxidation rates of the silicon film 17 and the floating gate electrode 14 are more than 10 times different.Therefore, as shown in FIG. Gate electrode 1
The gate insulating film of the selection gate electrode 15 (composite film consisting of silicon dioxide film 16, silicon dioxide film 17, and diacid film 18) can be made thinner without thinning the oxide film 19 of No. 4. Therefore, according to the present invention, the floating gate electrode 14
Since the structure allows the oxide film to be easily thickened, volatilization of electrons from the floating gate electrode 14 to the selection gate electrode 15 can be prevented. That is, the life of the nonvolatile memory can be extended.

Further, since the gate insulating film of the selection gate electrode 15 can be easily made thin, a higher lfi concentration can be used for the first channel L+, and the programming voltage can be easily lowered. For example, the underlying silicon dioxide film 167, (30A, silicon dioxide film 17
In the case of the first practical example of the present invention shown in FIG. 2, if the gate insulating film of the first channel Ll is thinned, the selection gate When a voltage of about 5 V is applied to the substrate 11, a tunnel current flows between the substrate 11 and the selection gate electrode 15, and a portion of the tunnel current becomes a trap of silicon nitride (Model 17).

There is a risk that the threshold voltage of the first channel Ll will be reduced.

The second embodiment of the present invention shown in FIG. 3 has a structure that prevents the threshold value of the first channel L from being degraded. That is, after etching the thin oxide film on the phosphoric acid film 17 formed when the floating gate electrode 14 is oxidized,
In the case of the second embodiment of the present invention shown in FIG. 3 in which the selection gate electrode 15 is formed, even if the gate insulating film of the first channel LL is made into a 11-thick film and a tunnel current flows, the tunnel current will not flow. is almost not trapped by the dust film 17 and is a selection game) 1! Since li@15 is reached, no deterioration of the threshold voltage of the first channel L occurs.

As explained above, according to the present invention, PAcM OS
Since silicon nitride is used as the memory gate insulating film, it is easy to thin the insulating film under the selection gate electrode and thicken the insulating film between the floating gate electrode and the selection gate electrode. Low program voltages are possible without reducing memory life.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional PACMO8 floating gate type nonvolatile memory, and FIG. 2 is a cross-sectional view of a PA of a first actual sister example of the present invention.
C! FIG. 3 is a cross-sectional view of a MOS memory, and FIG. 3 is a MOS memory according to a second embodiment of the present invention. FIG. 3 is a cross-sectional view of MOE+memory. 1.11... Semiconductor substrate 2.12... Source region 5.13... Drain region 4.14... Floating gate IE electrode 5.15. ...Selection gate electrodes 6.7, 16.18 ...2 [1 arsenic dust 17 ......Silicon nitride film or more]
Applicant: Kusani Seikosha Co., Ltd. Patent attorney: Tsutomu Mogami

Claims (1)

[Claims] Sources of a second conductivity type different from the first conductivity 'α type are provided at a distance from each other on the surface portion of the semiconductor substrate of the first conductivity type.
a first channel current having a drain region, a first gate current between the source and drain regions, and a first channel current located outside the first channel region IJ between the source and drain regions and in contact with the drain region; A second channel region having a two-gate gap, a selection gate electrode provided on the first gate insulating film, and a floating gate electrode provided on the second gate insulating film, In the floating gate semiconductor memory, a part of the channel current is injected from the opposite surface of the semiconductor substrate 4 where the first channel region and the second channel region are in contact with each other to the FF floating gate electrode. The gate insulating film of 2 is 10
[A structure in which the first gate insulating film includes an insulating film layer formed simultaneously with the second gate insulating film, which has a two-layer structure of a silicon dioxide film of JA or less and a silicon nitride film of 100 A or less. A semiconductor nonvolatile memory characterized by: