JP3512975B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a single electronic device, its application circuit device, and its manufacturing method.

[0002]

2. Description of the Related Art The structure of a conventional single-electron transistor operating at room temperature will be described with reference to FIG. An SOI (Si (Si) formed on a silicon substrate 101 via an oxide film 102.
The silicon quantum wires 103 are formed in the liconOn Insulator) layer by fine etching and subsequent thermal oxidation, and both ends of the silicon quantum wires 103 serve as a source and a drain. Quantum wire 10
On the gate electrode 105 via the gate oxide film 104.
Are formed.

In the conventional single-electron transistor shown in FIG. 23, the silicon islands formed in the fine wires 103 by etching and thermal oxidation have very small grain sizes smaller than 10 nm. Can have a total capacity of about 1 aF. Therefore, the Coulomb blockade phenomenon becomes possible at room temperature, and the room temperature device operation as a single electron transistor can be realized (for example, H. Ishikuro et al., Proc. Of SSDM p82 (1995), Y.
Takahashi et al., Dig. Of IEDM p938 (1994)).

In the conventional single-electron transistor shown in FIG. 23, since the silicon islands in the silicon quantum wires are naturally formed during the etching and the subsequent oxidation process, the island structure in the wires is caused by thermal fluctuation. The basic elements of the device such as and the capacity of each island were out of control. Therefore, there is a problem that there is no uniformity and reproducibility and it is impossible to design a device structure.

Attempts have also been made to apply a single electronic device to a nonvolatile semiconductor memory device. The structure of a conventional single-electron MOSFET type non-volatile semiconductor memory device will be described with reference to FIG. 24 (S. Tiwari and F. Rana et al., IEDM Dig.,
p521 (1955)).

Source / drain regions 112 are formed in a p-type silicon substrate 111, and a grain size of 5 is formed on the substrate surface through a tunnel oxide film 113 having a thickness of about 1.5 nm.
nm fine silicon particles 114 are uniformly formed over the entire channel. Further, a gate electrode 116 is formed on the gate electrode 116 via a control oxide film 115 having a thickness of about 7 nm.

Information is written by applying a gate voltage of about +4 V so that carrier electrons in the inversion layer that can be used as a channel are tunneled through the tunnel oxide film 113 and injected into and trapped in the silicon fine particles 114.

Information is read by observing the decrease in drain current due to the shielding of the electric field from the gate electrode to the inversion layer by the trapped information charges. For example, assuming that the surface density of silicon fine particles is 1 × 10 ¹² cm ⁻² , and one electron is trapped in each fine particle, the threshold value of the MOSFET is 0.36V.
The current changes and appears as a five-digit difference from the subthreshold region, which is sufficiently perceptible.

Information is erased by applying a negative gate voltage, which is the reverse of writing, to trap electrons in the tunnel oxide film 1.
It is performed by tunneling 12 through the silicon fine particles 114 to the channel. FIG. 25 shows an equivalent circuit diagram of a conventional single-electron transistor type nonvolatile semiconductor memory device.

The write / erase operation of the conventional single-electron MOSFET type non-volatile memory device shown in FIGS. 24 and 25 is performed by the tunnel junction and the standard capacitance as shown in FIG.

FIG. 27 shows the write / erase operation. Since the information charges are quantized in the unit of the elementary charge q due to the Coulomb blockade effect in the silicon fine particles which are the information charge accumulating portion, they have a stepwise characteristic as shown in FIG.

By applying the write voltage, the information charges written from the channel, which is the information charge supply source, to the silicon fine particles, which are the information charge storage part, through the tunnel junction are tunneled even if they are returned to the state where the write voltage is not applied. Due to the time delay, the channel is not returned to immediately and hysteresis occurs.

Therefore, even if the information charge is written in the silicon fine particles, the information charge tends to return to a more energy stable state, that is, the state in which the information charge is not written, when the information charge is returned to the state in which the write voltage is not applied. Has a problem that it easily escapes to the channel and disappears, and thus the memory retention time is short.

Further, in order to lengthen the memory retention time, it is necessary to increase the tunnel oxide film thickness to some extent to lengthen the tunnel time, which causes a problem that the write / erase time becomes longer and the memory operation becomes slower. there were.

In the conventional single-electron non-volatile semiconductor memory device, in order to read the state in which the electric charge is stored in the floating gate which is the information charge storage unit, a voltage is applied between the source and the drain to flow a current. In that case, a high electric field is applied between the floating gate and the channel in the electric field region higher than the drain in the channel from the pinch-off point. It leaks into the drain side channel.

Particularly, in an element using microcrystals as floating gates, under the condition that there is almost no movement of electric charges between microcrystals, in the case where an ordinary floating gate element does not leak charge from the entire floating gate. However, since a tunnel oxide film that is thin enough to directly tunnel the charges is used, leakage of the charges from the microcrystal near the drain becomes a problem.

After all, since the total amount of electric charge stored in the floating gate changes, the threshold value of the drain current during reading shifts more and more, so-called reed disturbance.
The problem of becomes remarkable.

When the device is intended to function as a multi-valued memory, a multi-valued memory is obtained by utilizing the fact that the injection of charges into nanoscale crystallites is suppressed by the Coulomb blockade effect. A memory is feasible. That is, the voltage required for accumulating the first charge to the second charge is strictly determined discretely by Q / C, where Q is the charge and C is the capacity of the microcrystal. Is possible.

In other words, the threshold voltage is determined by the capacitance C of one microcrystal, but in order to obtain a clear threshold voltage at room temperature, in the case of a silicon nanoscale microcrystal, the size should be about 3 nm or less. Need to be small. Since it is very difficult to form such fine and uniform nanoscale crystallites by the natural formation method, it is necessary to use some other method in order to utilize this device as a multilevel memory.

As described above, in the conventional floating gate type memory device using nanoscale crystallites, read disturba
There was a problem of nce and a problem that it was difficult to make multi-valued memory.

[0021]

SUMMARY OF THE INVENTION It is a first object of the present invention to provide a structure of a room temperature single electron device capable of device design and circuit design, and a manufacturing method thereof.

A second object of the present invention is to provide a structure of a single-electron MOSFET type nonvolatile semiconductor memory device which has a long memory retention time and can operate at high speed.

The third object of the present invention is read disturbance.
Single electron M that avoids the problem of multi-valued memory
It is intended to provide an OSFET type non-volatile semiconductor memory element.

[0024]

In order to achieve the first object, a semiconductor device of the present invention is formed between at least one pair of electrodes formed on a semiconductor substrate and the pair of electrodes. It is characterized by comprising a groove and conductive fine particles which are inscribed on both side surfaces of the groove and form two tunnel junctions between the groove and both side surfaces of the groove and which can hold one electron.

In the method for manufacturing a semiconductor device described above, a step of forming a first electrode on a semiconductor substrate and a step of forming a second electrode on the first electrode so as to face the first electrode with an insulating film interposed therebetween. A step of forming a groove between the first and second electrodes by etching the insulating film from the side surface exposed at the end of the second electrode; A step of causing the conductive fine particles to be contained in the groove by being dispersed over the entire surface of the semiconductor substrate, and forming two tunnel junctions at the interfaces between the first and second electrodes and the conductive fine particles. And is provided.

In the double tunnel junction having this structure, since the fine particles in the fine groove are limited to have a particle diameter of not more than the groove width, it is possible to reduce the size of the fine particles to the nm order (1 to 10 nm). Further, since the current flows through the path having the smallest resistance, the current flows at the fine particles whose particle diameter and the fine groove width are exactly the same. Therefore, the conductive island can be miniaturized to several nm capable of operating at room temperature, and the grain size can be controlled by controlling the groove width of the fine groove.

In this case, since each tunnel junction is formed by contact between the fine particles of which the grain size is known and the wall of the electrode, basic parameters such as island capacitance and tunnel resistance are also determined by the fine groove width. Therefore, by controlling the groove width of the fine groove, it is possible to realize a micro double tunnel junction with uniformity and reproducibility, and it is possible to achieve a room temperature single electron device capable of device design and further circuit design.

In order to achieve the second object, in the semiconductor device of the present invention, the source and drain diffusion layers are formed so as to face the surface of the semiconductor substrate, and the source and drain diffusion layers sandwich the source and drain diffusion layers. A floating electrode, which is a charge storage unit formed on a semiconductor substrate via a gate insulating film, a channel region formed on the surface of the semiconductor substrate below the floating electrode, and a channel region included in the gate insulating film. The conductive fine particles satisfying the Coulomb blockade condition that the charging energy is larger than the thermal fluctuation are formed, and the conductive fine particles and the gate insulating film surrounding the conductive fine particles are formed in the charge transfer direction. It is characterized in that the electric charge is taken in and out of the floating electrode through the two tunnel junctions.

In the method of manufacturing a semiconductor device described above, a single-electron MOSFET type semiconductor device having a floating electrode which is a charge storage portion on a semiconductor substrate via a gate insulating film is used. The step of forming fine grooves by etching the end portion of the gate oxide film between the electrodes from the outside, and the step of forming fine particles of silicon on the entire surface of the substrate to remove the fine silicon particles from the fine grooves. And forming two tunnel junctions in the interface between the silicon fine particles and both side surfaces of the fine groove in the direction in which electric charges are taken in and out of the floating electrode.

In the above manufacturing method, it is preferable that the gate insulating film is a silicon oxide film and the etching is performed using an etching solution containing ammonium fluoride.

In another method of manufacturing a semiconductor device of the present invention, a polysilicon grain film is formed on a first oxide film on the surface of a silicon substrate, and an interface between the first oxide film and the polysilicon grain film is formed. Forming a first tunnel junction on the surface of the polysilicon grain film, forming a second oxide film on the surface of the polysilicon grain film, and forming a second tunnel junction on the interface between the polysilicon grain film and the second oxide film. The method is characterized by including a step of forming and a step of forming a floating electrode on the second oxide film.

Yet another method of manufacturing a semiconductor device according to the present invention is that, on a first oxide film formed on the surface of a silicon substrate,
Forming a plurality of silicon microcrystals each having an apex and forming a first tunnel junction at an interface between the first oxide film and the plurality of silicon microcrystals; and a surface of the plurality of silicon microcrystals. And forming a second oxide film having a plurality of vertices corresponding to the vertices of the silicon microcrystals, and forming a second tunnel junction at the interface between the plurality of silicon microcrystals and the second oxide film. Forming step and the second step
And forming floating electrodes mounted on a plurality of vertices of the oxide film.

In the memory device having this structure, the coulomb blockade causes the information charges to have hysteresis in the form of energy stability from beginning to end, so that the written information charges do not escape from the floating electrode. Time will increase. Furthermore, since the tunnel oxide film thickness of the double tunnel junction sandwiching the microcrystals can be made thin regardless of the memory retention time, the tunnel time can be shortened without sacrificing the memory retention time, so high-speed operation with fast write / erase time is possible. It will be possible.

In order to achieve the third object, the semiconductor device of the present invention comprises first and second impurity diffusion layers formed so as to face the surface of a semiconductor substrate, and the first and second impurities. A first gate insulating film formed on the semiconductor substrate sandwiched between diffusion layers; a floating gate electrode formed of a plurality of microcrystals formed on the first gate insulating film;
A control gate electrode formed on the floating gate electrode via a second gate insulating film, wherein the first gate insulating film has at least two regions having different film thicknesses; The thickness of the region of the first gate insulating film near the first impurity diffusion layer is smaller than the thickness of the region of the first gate insulating film near the second impurity diffusion layer. Characterize.

Further, the region of the first gate insulating film near the first impurity diffusion layer functions as a tunnel barrier layer, and the region of the first gate insulating film near the second impurity diffusion layer is It is characterized in that it functions as an insulating film.

In addition, the film thickness of the first gate insulating film is from the region of the first gate insulating film close to the first impurity diffusion layer to the first impurity diffusion layer close to the first impurity diffusion layer.
Of the first gate insulating film, the thickness of which increases stepwise toward the region of the gate insulating film, and at least two regions of the first gate insulating film closer to the first diffusion layer function as tunnel barrier layers.

In the present invention, the problem of read disurbance is
A nanoscale (1 to 10 nm) microcrystalline region, which is a floating gate, and a channel region are provided in the source / drain direction.
The problem is solved by dividing and making the thickness of the barrier layer between the channel and the floating gate near the drain thicker than the thickness of the barrier layer near the source. By doing so, charges are tunnel-injected into the microcrystalline floating gate near the source when the gate bias is applied, but no electric charge is accumulated from the beginning in the microcrystalline floating gate near the drain, and a high electric field near the drain is read out during reading. The problem of charge escaping from the region, that is, the problem of read dis-turbance, is also avoided.

Further, the problem of the multilevel memory is that the microcrystalline region, which is the floating gate, and the channel are divided into a plurality of regions in the source / drain direction, and the thickness of the barrier layer is gradually increased from the source region to the drain region. It is solved by making it thicker. By adopting such a configuration and applying the voltage applied to the gate stepwise, charges are accumulated in each region, so that a multi-valued memory is easily realized. In addition, the thickness of the barrier layer between the drain and the channel / floating gate is thicker than that of the drain, so charge leakage does not occur during reading, and read dis
The problem of turbance will also be avoided.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A to 1C are sectional views showing stepwise a method of manufacturing a single electronic device (double tunnel junction) according to a first embodiment of the present invention.

After the oxide film 12 having a thickness of 5 nm and the n + polysilicon layer having a thickness of 200 nm are formed on the p-type silicon substrate 11,
The pattern of the electrode 13 of the polysilicon layer is formed, and the electrode 1 is formed.
Using phosphorus as a mask, phosphorus (P) is dosed at 1 × 10 ¹⁵ cm
^-2 , injection energy 15 KeV, 1000 ℃,
The n + layer 14 is formed by annealing for 20 seconds (FIG. 1).
(A)).

Then, the oxide film 12 is etched from the outside by performing an oxide film etching for 4 seconds with NH ₄ F, and a fine groove 15 having a width of 5 nm and a depth of 7 nm is formed between the electrodes 13 and 14. (FIG. 1 (b)).

Next, silicon fine particles having an average particle diameter of about 5 nm are sprayed on the entire surface of the substrate while being stirred with alcohol or the like, and the surface of the substrate is rinsed with alcohol or the like.
Fine silicon particles 1 that become islands in the fine grooves 15
Double tunnel junction where 6 exists can be formed (Fig. 1
(C)). This double tunnel junction can be represented by an equivalent circuit as shown in FIG.

In the present invention, as shown in FIG.
The silicon fine particles 16 in 5 have a particle diameter of 5 n
Since the size is limited to those smaller than m, the island can be miniaturized on the nanoscale (1 to 10 nm). further,
The current flowing between the electrodes 13 and 14 flows through the path having the lowest resistance, so that the current flows through the place of the fine particles whose particle size is exactly the same as the groove width of 5 nm. Therefore, the grain size of the island that determines the current can be uniquely determined by the groove width.

Therefore, even at a fine nanoscale capable of operating at room temperature, by controlling the thickness of the oxide film 12, the basic elements of the double tunnel junction such as the grain size and capacitance of the island are controlled and designed. can do. In this case, the thickness of the oxide film 12 can be accurately controlled by appropriately setting the conditions for gate oxidation.

(Second Embodiment) FIGS. 3 and 4 show stepwise a method of manufacturing a single electron device (double tunnel junction type single electron transistor) according to a second embodiment of the present invention. FIG.

A height difference of 500 on the surface of the p-type silicon substrate 21.
After forming a step of nm, an oxide film 22 having a thickness of 5 nm and an n + polysilicon layer 20 having a thickness of 300 nm are formed (FIG. 3).
(A)).

By performing reactive ion etching (RIE) using the resist pattern 27 as a mask, the polysilicon 20 in the upper step is removed and the substrate surface is exposed, and the n + polysilicon electrode 23 serving as a source is left by leaving the side wall. Is formed, and the lead line 29 of the source electrode connected to this is formed. Then, phosphorus (P) was added at a dose of 1 × 10 ¹⁵ cm ^-2 and an incident energy of ¹⁵ KeV.
And then annealed at 1000 [deg.] C. for 20 seconds to form the n <+> layer 24 to be the drain (FIG. 3B).

Thereafter, the oxide film 22 is removed from the outer side (upper side) by etching the oxide film with NH ₄ F for 4 seconds, and the width of the oxide film 22 between the source electrode 23 and the drain electrode 24 is reduced to 5 mm.
The fine groove 25 having a depth of 7 nm and a depth of 7 nm is formed. After that, silicon fine particles having an average particle diameter of about 5 nm are sprayed on the entire surface of the substrate while being stirred with alcohol or the like, and the surface of the substrate is rinsed with alcohol or the like to form fine silicon particles 26 which become islands in the fine grooves 25. To form a double tunnel junction (FIG. 4A).

Next, 100 nm thick Si is formed by CVD.
After forming an O ₂ layer 30 and an n + polysilicon layer of 200 nm thereon, the polysilicon layer is patterned to form a gate electrode 28. This completes the double-junction single-electron transistor (FIG. 4B). An equivalent circuit diagram of the double tunnel junction type single electron transistor is shown in FIG.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
6A to 6C are cross-sectional views showing stepwise a method of manufacturing a single electronic device (single electronic memory) according to the embodiment of FIG.

A 100 nm thick SOI (Silicon On Insul) film is formed on the buried oxide film 38 in the p-type silicon substrate 31.
A substrate on which the ator) layer 31 'is formed is prepared. The SOI layer 31 'is partially vertically etched by RIE to form a step having a height difference of 100 nm. Next, the thickness of 5
After a gate oxide film 32 of 50 nm and a polysilicon layer of 50 nm are formed in sequence, the polysilicon layer is vertically etched by RIE using the resist pattern as a mask to form an SOI.
While exposing the upper surface of the layer, a polysilicon electrode 33 is formed by leaving the side wall, and a polysilicon electrode 37 is further formed. Then, phosphorus (P) is added at a dose of 1 × 10 ¹⁵ cm
^-2 , injection energy 15 KeV, 1000 ℃,
The n + layer 34 is formed by annealing for 20 seconds (FIG. 6).
(A)).

Then, the oxide film 32 is removed from the outer side (upper side) by etching the oxide film with NH ₄ F for 4 seconds, and the width between the electrode 33 and the n + layer 34 is 5 nm and the depth is 7.
The fine groove 35 of nm is formed. After that, the average particle size is 5 nm
A double tunnel in which fine silicon particles 36, which become islands, are present in the fine grooves 35 by spraying a small amount of silicon fine particles on the entire surface of the substrate while stirring with alcohol or the like, and then washing the surface of the substrate with alcohol or the like. A bond is formed (FIG. 6B).

In this case, a capacitance is formed between the electrodes 33 and 37, and a single electron memory is formed between the electrode 37 and the electrode (n + layer) 34. An equivalent circuit diagram of the single-electron memory formed in this way is shown in FIG.

(Fourth Embodiment) FIGS. 8 and 9 are sectional views showing stepwise a method of manufacturing a single electronic device (turnstile device) according to a fourth embodiment of the present invention.

After a trench pattern having a height difference of 100 nm and a width of 300 nm is formed on the surface of the p-type silicon substrate 41 by an EB exposure device or the like, a gate oxide film 42 having a thickness of 5 nm and an n + layer 43 having a thickness of 200 nm are sequentially formed (see FIG. 8
(A)).

RIE under conditions where the sidewall of the polysilicon layer is left
After the n + polysilicon electrode 43 'is formed by the following method, phosphorus (P) is added at a dose of 1 × 10 ¹⁵ cm ^-2 and an incident energy of 1
Implantation is performed at 5 KeV, and annealing is performed at 1000 ° C. for 20 seconds to form an n + layer 44 (FIG. 8B).

Thereafter, the oxide film 42 is removed from the outer side (upper side) by etching the oxide film with NH ₄ F for 4 seconds, and the width between the electrode 43 ′ and the n + layer 44 is 5 nm and the depth is 7 nm. The fine groove 45 is formed. Then average particle size 5n
A silicon fine particle group of about m is sprayed over the entire surface of the substrate while being stirred with alcohol or the like, and then the surface of the substrate is rinsed with alcohol or the like, so that the fine silicon particles 46 serving as islands are present in the fine groove 45. A tunnel junction is formed (FIG. 8 (c)).

Next, 100 nm thick Si is formed by CVD.
After an O2 layer 47 and a 200 nm n + polysilicon layer are sequentially formed on the substrate, a pattern of a gate electrode 48 having a length of 50 nm is formed by an electron exposure apparatus or the like (FIG. 9). As a result, a capacitance is formed between the gate electrode 48 and the electrode 43, and a double tunnel junction is formed between the electrode 43 and the electrode (n + layer) 44 and between the electrode 43 and the electrode 44 '. The element is completed. An equivalent circuit diagram of this turnstile element is shown in FIG.

As described in the first to fourth embodiments of the present invention, by using the double tunnel junction of the present invention, various kinds of room temperature operation single electronic devices and single electronic circuit devices can be obtained. Can be designed.

In the first to fourth embodiments, the formation of the fine grooves by the NH ₄ F etching of the SiO ₂ thin film between the n + silicon electrodes has been described. The configuration of the present invention is also possible by using a selective etching method corresponding to. Also, the above first to first
Although silicon fine particles are used in the fourth embodiment, other conductive fine particles may be used. Further, while the fine particles are dispersed on the substrate surface by stirring the fine particles with alcohol or the like, the fine particles may be directly formed on the surface by a CVD method.

(Fifth Embodiment) FIGS. 11 and 12 are sectional views showing stepwise a method of manufacturing a single electronic element semiconductor memory device according to a fifth embodiment of the present invention. An oxide film 52 having a thickness of 5 nm and a thickness of 10 n are formed on a p-type silicon substrate 51.
An n + type polysilicon layer 53 to be a floating electrode of m is sequentially formed, and a SiN film 5 having a thickness of 10 nm is formed on the n + type polysilicon layer 53 by CVD.
4 and a 200 nm thick n + polysilicon layer to be the gate electrode 55 are sequentially formed.

After that, a pattern of the gate electrode 55 is formed, and the electrode 55 is used as a mask to dose As in 1 × 10 ^15.
cm ^-2 , injection with an incident energy of 15 KeV, 1000
An n + layer 56 is formed by annealing at 20 ° C. for 20 seconds (FIG. 11A).

Next, the oxide film 52 is removed from the outside by etching the oxide film with NH ₄ F for 4 seconds.
A fine groove 57 having a width of 5 nm and a depth of 7 nm is formed between the n + layer 53 and the n + layer 56 (FIG. 11B).

Next, silicon fine particles having an average particle diameter of about 5 nm are sprayed over the entire surface of the substrate while being ultrasonically stirred with methanol, and the surface of the substrate is rinsed with methanol, pure water or the like. A new single-electron MOSFET type non-volatile semiconductor memory device having a double tunnel junction in which fine silicon particles 58 are sandwiched is formed (FIG. 12).

(Sixth Embodiment) FIGS. 13 and 14 are sectional views showing stepwise a method of manufacturing a single electron type semiconductor memory device according to a sixth embodiment of the present invention. After forming an oxide film 62 having a thickness of 1 nm on a p-type silicon substrate 61, an ultrathin film of amorphous silicon is deposited on the oxide film 62, and the temperature is set to 750 ° C.
Anneal. Thus, a silicon film 63 having a thickness of 5 nm and made of nm order polysilicon grains is formed (FIG. 13).

Further, after forming an oxide film 64 having a thickness of 1 nm, an n + polysilicon layer 65 having a thickness of 10 nm to be a floating electrode is formed, and subsequently an oxide film 66 having a thickness of 10 nm and a thickness to be a gate electrode are formed. 200 nm n + polysilicon layer 67
Are formed by CVD (FIG. 14A).

Then, the laminated layer on the substrate is vertically etched by using the resist pattern 69 as a mask to expose the substrate surface to form a gate electrode portion. afterwards,
As is injected into the exposed substrate surface at a dose of 1 × 10 ¹⁵ cm ⁻² and an incident energy of ¹⁵ KeV, and 1000 ° C.
By annealing for 20 seconds, an n + layer 68 serving as a source / drain is formed. As a result, a new single-electron MOSFET type non-volatile semiconductor memory device having a double tunnel junction in which the microcrystal 63 is sandwiched in the gate oxide film can be formed (FIG. 14B).

(Seventh Embodiment) FIGS. 15A to 15C are sectional views showing stepwise a method of manufacturing a single electron semiconductor memory device according to a seventh embodiment of the present invention. p-type silicon substrate 71
After forming an oxide film 72 with a thickness of 1 nm on the silicon microcrystals 7 with a grain size of 5 nm by ultra-thin film CVD and subsequent annealing.
3 is uniformly formed on the surface, and further an oxide film 74 having a thickness of 1 nm is formed (FIG. 15A).

After that, n having a thickness of 10 nm to be a floating electrode is formed.
+ The polysilicon layer 75 is formed. At that time, the surface density is adjusted in the step of forming the microcrystals 73 so that the polysilicon 75 cannot enter the space between the fine particles 73 due to the high aspect ratio ( FIG. 15B).

Subsequently, an oxide film 76 having a thickness of 10 nm and an n + polysilicon layer having a thickness of 200 nm to be the gate electrode 77 are formed by CVD, and anisotropic etching is performed using a resist pattern (not shown) as a mask to expose the substrate surface. The gate electrode portion is formed by exposing. After that, the dose of As is 1 × 10 ¹⁵ cm ^-2 and the incident energy is ¹⁵ KeV.
Is implanted into the surface of the substrate and annealed at 1000 ° C. for 20 seconds to form an n + layer 78 to be the source / drain regions. As a result, a new single-electron MOSFE having a double tunnel junction in which the microcrystal 73 is sandwiched in the gate oxide film.
A T-type nonvolatile semiconductor memory device is formed (FIG. 15).
(C)).

Although silicon fine particles or polysilicon grains are used in the fifth to seventh embodiments, other conductive nanoscale fine particles may be used. Sixth,
In the seventh embodiment, the tunnel junction is formed by thermal oxidation of SiO 2.
It is set to _2, but may be a SiO ₂ or other insulating film by CVD.

As shown in FIG. 12 of the fifth embodiment of the present invention, writing of information charges between the floating electrode 53 which is a charge storage part and the source / drain diffusion layer or the channel which is a charge supply part. Erasing is performed through a double tunnel junction sandwiching nanoscale silicon particles 58 that satisfy the Coulomb blockade condition at room temperature.

Similarly, in the sixth and seventh embodiments, writing / erasing to / from the floating electrodes 65 and 75 via the double tunnel junction sandwiching the nanoscale particles 63 and 73 satisfying the Coulomb blockade condition at room temperature, respectively. Is done.

FIG. 16 shows an equivalent circuit diagram of the single-electron MOSFET type nonvolatile semiconductor memory device according to the fifth to eighth embodiments of the present invention. In the write / erase operation of the semiconductor memory device of the present invention, as shown in the model by the equivalent circuit of FIG. 17, a minute conductive island that satisfies the Coulomb blockade condition at room temperature and a double tunnel junction (capacitance C ₁ X2) and the standard capacitance (capacitance C).

The write / erase operation will be described with reference to FIG. To write the information charge Q ₀ , V _G
Write voltage V _W = q / (2C ₁ ) + Q ₀ / C (q:
It is enough to instantly raise it to (elementary charge) and return it to 0 immediately. At this time, the Coulomb blockade effect, V _G = 0 from _{V G = q / (2C 1} ) does not occur write up. Similarly, Q ₀ does not change even if V _G is raised to V _{W and then} lowered to ₀ . This is because the VI characteristic in the circuit of FIG.
It can be understood from the fact that it exhibits a characteristic like 0.

Next, when it is desired to erase the information charge Q ₀ , V _G is instantaneously lowered to the erase voltage V _e = −q / (2C ₁ ) and then returned to 0 immediately, the information charge returns to the initial state. Can be erased. The hysteresis shown in FIG. 18 depends on the Coulomb blockade effect shown in FIG. 20, but since it always follows an energy stable state, the written information charge is not lost. Therefore, the memory retention time becomes very long.

Further, even if the tunnel oxide film thickness is extremely thin to 1 nm or less, the tunnel time, that is, the write / erase time can be greatly shortened without a trade-off between the memory holding time and the memory operation can be performed at high speed. . Also at this time,
The drain voltage at the time of reading is Vd <q / (2C ₁ ) −Q ₀
If / C is set, the information charge Q ₀ is also present at the drain end.
Is in the region where it does not change due to Coulomb blockade, so malfunctions due to so-called Read Disturbance can be prevented in advance.

[0078] Incidentally, the capacitance of the double tunnel junction in the above embodiment are equal in both two C _1, but different C ₁ and the threshold value q / (2 of blockade region even when the C ₂
C ₁₎ is only becomes _{q / (C 1 + C 2} ), does not change the write-erase operation shown in FIG. 18.

In the fifth to seventh embodiments, the floating electrodes 53, 65, 75 for accumulating the information charges are large electrode plates, but the charge accumulating portions are also silicon fine particles satisfying the Coulomb blockade condition. If a minute crystal such as polysilicon grain is used, the information charges are quantized in the unit of elementary charge, so that a high-speed multi-valued memory having a long storage retention time is possible.

(Eighth Embodiment) FIG. 21 is a sectional view of a floating gate type semiconductor memory device according to an eighth embodiment of the present invention. In this embodiment, in a normal n-type MOSFET-based floating gate type semiconductor memory device, nanoscale silicon microcrystals formed by a CVD method are used as floating gates, and a channel / floating gate having two thicknesses is used. It has a barrier.

First, a thick gate oxide film 82 is formed to a thickness of 5 nm or more on the entire gate region on the p-type semiconductor substrate 81. After that, the gate oxide film 82 near the source region 88 ′ is selectively removed using a mask, and the entire surface is again subjected to thermal oxidation, so that only the region near the source region 88 ′ has a thickness of 4 nm.
The following thin gate oxide film 82 'is formed. that time,
The thick oxide film 82 has a lower oxidation rate than the thin oxide film 82 ', but the film thickness increases.

After forming the tunnel oxide films 82 and 82 ',
For example, the floating gate region 83 of nanoscale silicon microcrystals is formed by performing CVD of silicon while keeping the substrate at room temperature without heating the substrate and continuously heating the substrate at a high temperature for a short time. After that, CV on the entire surface
A D oxide film 86 is deposited and a control gate 87 is formed thereon. Reference numeral 84 is an electrode separation region.

The other transistor manufacturing process can be easily carried out by using a normal n-channel MOSFET type floating gate element manufacturing process. In the floating gate type semiconductor memory device thus manufactured, electrons can be injected into the silicon microcrystal 83 near the source region 88 ′ at a low voltage by direct tunneling through the thin barrier region, and the electrons near the drain region 88 can be injected. Since a thick barrier region is present in the silicon microcrystal, electron injection does not occur under the same bias condition as the source region.

Therefore, even if a bias is applied to the source / drain at the time of reading, the floating gate region 83 near the drain is formed.
Since no electrons originally existed in the floating gate, the charge quantity of the entire floating gate did not change, and therefore, read disturbance
Problem does not occur.

(Ninth Embodiment) FIG. 22 is a sectional view of a floating gate type memory device according to the ninth embodiment of the present invention. In the present embodiment, the tunnel oxide film 82 is divided into three regions having different film thicknesses, and the source region 88 '.
From the region having the thinnest tunnel oxide film 82 ″ to the drain region 88, there are two other regions in which the thickness of the tunnel oxide film gradually increases.

If the two regions 82 "and 82 'of the tunnel oxide film closer to the source region 88' are used as tunnel barrier layers, it is possible to function as a ternary memory due to the difference in threshold voltage. If a region close to 88 is included, a 4-value memory becomes possible.

Although a plurality of barrier regions having different thicknesses are present in this embodiment, this can be easily formed by sequentially repeating the method shown in the eighth embodiment a plurality of times.
Further, other processes can be easily carried out by using a usual method for manufacturing an n-channel MOSFET type memory device. Therefore, the same parts as those in the eighth embodiment are designated by the same reference numerals, and the duplicate description will be omitted.

The floating gate type memory device manufactured in this manner can form a four-valued multi-valued memory of 0 to 3 with a clear threshold voltage, although the crystallite size is relatively large at 5 nm or more. In addition, since the barrier layer between the channel and floating gate near the drain is thick, charge leaks during reading.
The problem of ead disturbance does not occur.

Although the n-channel type MOSFET is used in the eighth and ninth embodiments, the present invention is a p-type MOSFET.
The same can be applied to T. The same can be applied to a MOS type or heterojunction type transistor using a mixed crystal such as SiGe or SiGeC. Furthermore, GaAlAs series, GaAlN series, or GaI
The same can be applied to a heterojunction transistor formed of a compound semiconductor such as nAsP system.

As described above, according to the present invention, read diaturbance
It is possible to provide a highly reliable floating gate type memory device that is not affected by the above. Further, the present invention can provide a multi-valued floating gate type memory device having a well-defined threshold voltage.

[0091]

According to the present invention (claims 1 to 3), since the fine particles in the fine grooves are limited in particle diameter to the groove width or less,
It is possible to miniaturize fine particles on the order of nm. Therefore, the conductive island can be miniaturized to several nm capable of operating at room temperature, and the grain size can be controlled by controlling the groove width of the fine groove. In this case, basic parameters such as island capacitance and tunnel resistance are also determined by the fine groove width. Therefore, by controlling the groove width of the fine groove, it is possible to realize a micro double tunnel junction with uniformity and reproducibility, and it is possible to achieve a room temperature single electron device capable of device design and further circuit design.

Further, according to the present invention (claims 4 to 7), the written information charge escapes from the floating electrode due to the occurrence of hysteresis in the information charge in the energy stable form from beginning to end due to Coulomb blockade. As a result, the memory retention time becomes long. Furthermore, since the tunnel oxide film thickness of the double tunnel junction sandwiching the microcrystals can be made thin regardless of the memory retention time, the tunnel time can be shortened without sacrificing the memory retention time, so high-speed operation with fast write / erase time is possible. It will be possible.

Further, in the present invention (claims 8 to 10), the nanoscale microcrystalline region which is the floating gate and the channel region are divided into two in the source / drain direction, and the channel / floating gate barrier layer near the drain is formed. Is made thicker than the thickness of the barrier layer near the source, the charges are tunnel-injected into the microcrystal floating gate near the source when the gate bias is applied, but the microcrystal floating gate near the drain is initially charged. Charge is not accumulated from the read disturbance
The problem of can be avoided.

Further, the microcrystalline region which is the floating gate and the channel are divided into a plurality of regions in the source / drain direction,
By increasing the thickness of the barrier layer in steps from the source region to the drain region and applying the applied voltage to the gate in stages, charges are accumulated in each region, making it easy to realize multilevel memory. To be done. In addition, since the thickness of the barrier layer between the drain and the channel / floating gate is thicker than that of the drain, charge leakage does not occur during reading, and the problem of read disturbance can be avoided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing steps of manufacturing a single electronic device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the single electronic device according to the first embodiment.

FIG. 3 is a cross-sectional view showing stepwise a manufacturing process of a single electronic device according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing stepwise steps following the step of FIG. 3 of manufacturing a single electronic device according to the second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the single electronic device according to the second embodiment.

FIG. 6 is a cross-sectional view showing stepwise a manufacturing process of a single electronic device according to a third embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of the single electronic device according to the third embodiment.

FIG. 8 is a cross-sectional view showing stepwise a manufacturing process of a single electronic device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing a step that follows the step of FIG. 8 for manufacturing the single electronic device according to the fourth embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of the single electronic device according to the fourth embodiment.

FIG. 11 is a single electron M according to the fifth embodiment of the present invention.
Sectional drawing which shows the manufacturing process of an OSFET type nonvolatile semiconductor memory device.

FIG. 12 is a single electron MO according to a fifth embodiment of the present invention.
FIG. 11 of the manufacturing process of the SFET type nonvolatile semiconductor memory device
Sectional view showing the steps following

FIG. 13 is a single electron M according to the sixth embodiment of the present invention.
Sectional drawing explaining the manufacturing method of an OSFET type non-volatile semiconductor memory device.

FIG. 14 is a single electron MO according to a sixth embodiment of the present invention.
FIG. 13 of the manufacturing process of the SFET type nonvolatile semiconductor memory device
Sectional view showing the steps following

FIG. 15 is a single electron M according to the seventh embodiment of the present invention.
Sectional drawing which shows the manufacturing method of an OSFET type non-volatile semiconductor memory device in steps.

FIG. 16 is an equivalent circuit diagram of the single-electron MOSFET type nonvolatile semiconductor memory device of the present invention.

FIG. 17 is an equivalent circuit diagram for explaining programming and erasing of the single-electron MOSFET type nonvolatile semiconductor memory device of the present invention.

FIG. 18 is a V _G -Q characteristic diagram for explaining writing and erasing of the single-electron MOSFET type nonvolatile semiconductor memory device of the present invention.

FIG. 19 is an equivalent circuit diagram for explaining the Coulomb blockade effect of the double tunnel junction.

FIG. 20 is a VI characteristic diagram illustrating the Coulomb blockade effect of the double tunnel junction.

FIG. 21 is a sectional view of a floating gate type semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 22 is a sectional view of a floating gate type semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 23 is a sectional view of a conventional single-electron MOSFET.

FIG. 24 is a cross-sectional view of a conventional single-electron MOSFET type nonvolatile semiconductor memory device.

FIG. 25 is an equivalent circuit diagram of a conventional single-electron MOSFET type nonvolatile semiconductor memory device.

FIG. 26 is an equivalent circuit diagram for explaining writing and erasing of a conventional single-electron MOSFET type nonvolatile semiconductor memory device.

FIG. 27 is a V _G -Q characteristic diagram for explaining writing and erasing of the conventional single-electron MOSFET type nonvolatile semiconductor memory device.

[Explanation of symbols]

11 ... Silicon substrate 12 ... Oxide film 13 ... Polysilicon electrode 14 ... n + diffusion layer 15 ... Groove 16… Small silicon particles

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/792 (72) Inventor Naoji Sugiyama 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center Co., Ltd. (56 ) Reference JP-A-8-167662 (JP, A) JP-A-49-52581 (JP, A) JP-A-48-27687 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB) Name) H01L 29/788

Claims (10)

(57) [Claims] 1. At least one formed on a semiconductor substrate
A pair of electrodes; a groove formed between the pair of electrodes;
A semiconductor device comprising: conductive fine particles capable of forming one tunnel junction and holding one electron. 2. A step of forming a first electrode on a semiconductor substrate; a step of forming a second electrode on the first electrode so as to face the first electrode via an insulating film; A step of forming a groove between the first and second electrodes by etching the film from a side surface exposed at an end of the second electrode; and spraying conductive fine particles on the entire surface of the semiconductor substrate. By doing so, the conductive fine particles are contained in the groove,
A step of forming two tunnel junctions at an interface between the first and second electrodes and the conductive fine particles, and a method of manufacturing a semiconductor device. 3. A source and drain diffusion layer formed to face a surface of a semiconductor substrate, and a charge storage formed on the semiconductor substrate sandwiched by the source and drain diffusion layers via a gate insulating film. Part, a floating electrode, a channel region formed on the surface of the semiconductor substrate below the floating electrode, and a Coulomb blockade condition included in the gate insulating film, in which charging energy of one electron is larger than thermal fluctuation. A conductive fine particle that fills at room temperature, and is formed between the conductive fine particle and the gate insulating film surrounding the conductive fine particle in the charge transfer direction.
A semiconductor device, wherein the electric charge is taken in and out of the floating electrode via the two tunnel junctions. 4. A single-electron MOSFET having a floating electrode, which is a charge storage portion, on a semiconductor substrate via a gate insulating film.
Forming a fine groove by etching an end portion of the gate oxide film between the source or drain diffusion layer and the floating electrode from the outside in a method for manufacturing a semiconductor device, and forming silicon fine particles on the substrate. The silicon fine particles inside the fine groove by being dispersed over the entire surface of the micro-groove, and two tunnel junctions are formed at the interface between the silicon fine particle and both side surfaces of the fine groove in the direction of charging / discharging the electric charge to / from the floating electrode. And a step of forming a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the gate insulating film is a silicon oxide film, and the etching is performed using an etching solution containing ammonium fluoride. 6. A first oxide film on a surface of a silicon substrate,
Charge energy of one electron is larger than thermal fluctuation
Forming a polysilicon grain film so as to satisfy the Coulomb blockade condition at room temperature and forming a first tunnel junction at an interface between the first oxide film and the polysilicon grain film; and the polysilicon grain film. Forming a second oxide film on the surface of the second oxide film and forming a second tunnel junction at the interface between the polysilicon grain film and the second oxide film; and forming a floating electrode on the second oxide film. A method of manufacturing a semiconductor device, comprising: 7. The charging energy of one electron is larger than the thermal fluctuation on the first oxide film formed on the surface of the silicon substrate.
Meet the Coulomb blockade requirement of temperature at room temperature
As described above, forming a plurality of silicon microcrystals each having an apex, and forming a first tunnel junction at the interface between the first oxide film and the plurality of silicon microcrystals; A second oxide film is formed on the surface so as to have a plurality of vertices corresponding to the vertices of the silicon microcrystals, and a second tunnel junction is formed at the interface between the plurality of silicon microcrystals and the second oxide film. And a step of forming floating electrodes mounted on a plurality of vertices of the second oxide film, the method of manufacturing a semiconductor device. 8. The semiconductor according to claim 3, wherein the charges are taken in and out of the floating electrode only through the two tunnel junctions sandwiching the conductive fine particles satisfying the Coulomb blockade condition. apparatus. 9. The method of manufacturing a semiconductor device according to claim 6, wherein all of the polysilicon grain films satisfy the Coulomb blockade condition. 10. The method of manufacturing a semiconductor device according to claim 7, wherein all of the silicon microcrystals satisfy the Coulomb blockade condition.