JPS59221811A - Decoder of pcm recording and reproducing device - Google Patents

Abstract

PURPOSE:To manufacture a titled decoder by a simple circuit, to cause no block shift nor error detection leakage, and to execute exactly the operation by executing various signal processigs by the decoder, before information recorded in a recording medium is sent to a D/A converter. CONSTITUTION:A decoder has an RAM 4 for storing data of at least one field in order of an arriving block, and an RAM 7 for storing an error flag for showing a result of an error inspection (CRC check) of each block by ''1'' (error) and ''0'' (correct). Also, the decoder has an address generating part 11 for supplying simultaneously a common address to the respective address buses of the two RAMs, and a clock generating part 2 for generating and sending a time signal for executing a prescribed operation at a suitable time, to the data RAM 4, the flag RAM 7 and the address generating part 11. In this way, the decoder can be converted to an IC easily, can be made small-sized, no block shift nor error detection leakage is caused, and the operation is executed exactly.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a PCM (Pulse Code Modulation) recording and reproducing device, and particularly to a dental analog
/A>Relates to a decoder that performs various signal processing prior to sending to a converter.

[Background technology]

In a PCM recording/reproducing apparatus, data recorded on a recording medium is recorded as a chain of units called blocks, and a field is formed by a set of a predetermined number of blocks. A block consists of a synchronization word for distinguishing between blocks, a block address word for indicating the block number, a parity word for code error detection, and a CRCii! for error correction. i and an information word containing original information. Before extracting the data recorded in the above format from the recording medium and reproducing it as an analog signal, detect the field, block and edict synchronization signals, convert from serial to parallel, and address W? ,
Various processes such as WC1CRC check, error correction, and error interpolation are performed. , the part that performs these processes is called a decoder of the PCM recording and reproducing apparatus.

Conventionally, each of the above-mentioned processes is sequentially performed on an input signal to a decoder by a series of circuits. Therefore, the circuit as a whole is complex, not easy to manufacture, and difficult to integrate into an IC, making it difficult to miniaturize.

[Disclosure of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder for a PCM recording and reproducing apparatus that overcomes the drawbacks of the prior art described above.

The decoder of the PCM recording and reproducing apparatus according to the present invention includes a RAM (data RAM) that stores at least one field of data in the order of arriving blocks, and a 1 ("error") result of error checking (CRC check) for each block. and O(r
A RAM (flag RAM) that stores an error flag represented by "-"; an address generator that simultaneously supplies a common address to each of the address buses of the two RAMs; and the data RAM and flags described above. It includes a clock generation section that generates and delivers a time signal for causing the RAM and address generation section to perform predetermined operations at appropriate times.

The address generation section includes a circuit for calculating a reference address of a memory area storing field 1i, a first ROM, and a second ROM.
ROM, a third ROM, several adders, and three control circuits that control output to the address bus.

The above first ROM inputs the block address and
It stores the procedure for calculating the relative position of blocks within a field. The output of the first ROM is summed with the output of the reference address calculation circuit described above to provide the address of the first word of each block in the data RAM.

The second ROM stores the procedure for calculating the relative position of each city for each block relative to the first word.

The addition result of the output of the first ROM and the reference address mentioned above and the output of the second ROM are further added in an adder, and the output of the adder is sent to the address bus mentioned above via the first control circuit. It is connected. The first control circuit passes the output of the adder to the address bus in response to a write command signal from the clock generator.

The address generation section performs 1 itu of the above field.
It includes an adder that calculates the address of the first word of the R end block based on the address of the first word of the R end block. The output of this adder is "the second R
It is input to the adder together with the output of OM. And the output of this adder is each t! It is supplied to the second control circuit as a signal specifying the address of the final block for i. Second
The control circuit passes the person horn signal to the address bus in response to either a command signal for temporarily storing each city at the address of the -H final block or a command signal to read from the final block. .

The third (7) ROM stores the relative relationship between the field reference address and the address of each city in the final block. The output of the third ROM and the output of the field reference address are added by an adder, and the added output is connected to be supplied to the address bus via the third control circuit. When the third II control circuit receives the final error flag write signal from the clock generator, it passes its input to the address bus.

The clock generator generates and delivers a time signal so that each part of the decoder operates at the same timing.

t, that is, before storing the block in the data RAM,
The error flags corresponding to the 6 words of all blocks are set to "1".

All blocks are temporarily stored at the address where the final block is to be stored. Thereafter, it is immediately read out to a suitable auxiliary memory and subjected to a CRC check. CR
If the error flag is I'OJ as a result of the C check, the block is stored at the address in the data RAM where it should originally be stored. If the error flag 5 is "1", the above storing operation does not occur. By repeating the above series of operating procedures for each block, one field of data is stored in the data RAM, and the error status is stored in the flag RAM.

Only when storing the last block candy error flag rOJ, the address is specified by the output of the third ROM.

[Invention 9 Preferred Embodiments] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram illustrating a decoder according to the present invention.

The serial PCM signal 1 extracted from the recording medium is input to a clock and synchronization pulse extraction circuit 2.

The clock and synchronization pulse extraction circuit 2 detects the basic clock, and based on it detects the field synchronization signal,
Each block synchronization signal and 8-byte synchronization signal are detected, and based on these synchronization signals, the block synchronization word, address word, data word (including information), check word (P, Q), etc.
) and error correction code (CRC) are retrieved. Of these edicts, excluding the block synchronization word (6 words are converted into parallel signals in word (byte) units by the serial/parallel converter 3 and then sent to the data bus 5 of the data RAM 4 (addresses will be described later) do).

On the other hand, each city other than the synchronization word is input to the CRC check circuit 6, where it undergoes a CRC check. CRC (Cyc
The error detection method based on Lic Redundancy Code is currently used in PCM recording and reproducing equipment.
It is widely used as the most reliable error detection method. Flag R is set for 3H which is determined to be an error as a result of the check at J'3 in the CRC check circuit 5.
A signal Ml indicating an error is sent to the data bus 8 of AM7.

The flag RAM 7 has a number of pits corresponding to the number of words stored in the data RAM 4, and an error flag for a masterpiece sent from the CRC check circuit 6 ("1" if 1 bit is "error", "correct"). (represents rOJ) is stored.

The respective address buses 9 and 10 of the data RAM 4 and the flag RAM are commonly connected to the output of the address generator 11. Due to this connection, one oil and the error flag corresponding to the edict are stored in the same address in the data RAM 4 and the flag RAM in a one-to-one correspondence.

Address generator 11 supplies a common address signal to data RAM and flag RAM as described above.

Clock and synchronization pulse extraction circuit 2 supplies the aforementioned synchronization pulses to address generator 11 via line 12. The block address extractor 12 also decodes the number of each block in the field (block address) and sends a corresponding signal to the address generator 11 via a line 13.
give to The address generator 11 is further supplied with a time signal from a clock 14.

After the error flags corresponding to one field of masterpieces are stored in the data RAM and the error flags corresponding to eight edicts are stored in the flag RAM as described above, the error correction circuit 15 performs error correction.

The error correction circuit 14 performs error correction based on the parity g p , Q stored in the data RAM and the error flag stored in the flag RAM.

Finally, after error correction and correction by interpolation etc. are performed by the output J circuit 16, the contents of the data RAM 4 are transferred to the D/A
Sent to the converter.

Next, the address generator 11 which simultaneously and commonly addresses the data RAM 4 and the flag RAM 7 will be explained.

FIG. 2 shows a circuit diagram of the address generator 11.

The adder 17 sends out a signal (referred to as RF318) representing a field reference address of input data based on a signal (RF2>) representing a reference address of the data RAM.

1st (7) ROM (ROMG) 19 is fiil (7)
A signal BΔ indicating a block number (block address) within the field is received from the block address extractor 12 as shown in FIG. The ROMG 19 is programmed to provide an output corresponding to the J input shown in FIG. 3(a). In FIG. 3(a), the interval between each output is 10.

The output of ROMG19 and the output RF3 of adder 17 are added in adder 19. As a result, at the output of the adder 20, a signal corresponding to the address of the first candy of each block is obtained.

The counter 21 inputs the candy (byte) synchronization signal F1 and the block synchronization signal E5 indicating the start of EB immediately after the block synchronization signal, and sends the count signal for each M1 to the second RO.
M (ROME22').

ROME 22 is programmed to provide outputs corresponding to the inputs shown in Figure 3(1)).

The output 23 of ROME is supplied to an adder 24 along with the output of adder 20. As a result, the output 25 of the adder 2/l provides the address at which the 8 edicts of the block should be stored.

Output 25 of adder 24 is supplied to control circuit 26 . The control circuit 26 receives its input signal 2 by the input/output signal F4.
5 to the address bus 27.

Adder 28 adds reference signal RF3 and a signal representing the number of blocks (<51EH) to determine the address of the first word of the final block. The output of adder 28 is ROME2
2 is supplied to an adder 29 together with the output 23 of 2. As a result, the address of the edict of the final block is obtained at the output of the adder 29 for each input of the master. The output of the adder 29 is sent to the control circuit 3
0, the data output signal F2 and the data storage signal F3
is sent to the address bus 27 when either one of them is given.

The counter 31 counts the signal A15 representing the number of information devices in one block and the signal F5 indicating the last write, and supplies the counted signals to the third ROM (ROM32). ROMF 32t is block programmed to provide outputs for inputs as shown in FIG. 3(C). Output of ROMF32 and reference address signal eRF3
is supplied to the adder 33. As a result, adder 33 sends an output to control circuit 34 giving the address at which the final block is to be stored. The control circuit 34 uses signals A15 and E5 to send data to the address bus 27 only in the case of storage when the error flag of the last block is "0".

Fig. 4 shows the signals that control the timing of each movement of the top.

The operation of the decoder according to this embodiment will be comprehensively explained with focus on the data RAM and flag RAM as follows.

(1) When a word is output from the data RAM to the D/A converter, the error flag corresponding to the edict is output as rlJ. Therefore, the error flag is "1" for all blocks in the field at the time of input to the de-RAM. By making the initial settings in this manner, it is possible to prevent a one-block length error that may occur when blocks are stored one block apart due to synchronization when each block is stored in the data RAM 4.

(2) Each city of the n-th block input to the decoder is sequentially stored at the address where the last block is to be stored. A CRC check is performed at the same time as the storage of the block is completed. The results are stored in each corresponding bin 1-- of the flag RAM.

(3) When the first block is input, the nth block is read out and temporarily stored in the D flip 70 block.

The first block is then stored at the final block address. When the M5mm flag associated with the n-th block is rOJ, that block is written to the address of the original block. If the error flag is "1", no action is taken. At the same time, a CRC check is performed on the first block and the result is stored in the D flip-flop.

(4) For the second to last blocks, each block and error flag are sequentially stored using the same procedure as above. That is, each time the nth block is input, the (n-1)th block is read out and temporarily stored in the D flip 70 block.

b. The 11th block is temporarily stored at the storage address of the final block.

If the error flag of the (n-1)th block is "0", then D
The block stored in the flip-flop and the error flag rOJ are stored at the original addresses of the data RAM and flag RAM, respectively.

If the error flag is "1", no action is taken.

] Second, a CRC check is performed on the nth block,
The result is stored in the D flip-flop.

(5) The final block is stored at the original address from the beginning. Therefore, when the error flag is rOJ, only the error flag is written.

The block with the above configuration is block β11113
Even if a deviation occurs, the error flag becomes "1" and no error detection will occur. Also, the data RAM address is OR, C
Since it is created from checked block addresses, it has the advantage that block shifts will not occur.

The decoder of the PCM recording and reproducing apparatus according to the present invention has a simple circuit, so it is easy to manufacture, and it can be easily integrated into an IC, so it can be miniaturized. Furthermore, there is no block shift or error detection failure, and the operation is reliable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a decoder according to the present invention. FIG. 2 is a block diagram of the address generator. FIG. 3 is an input/output comparison table showing the algorithms stored in ROMG, ROME, and 1 dog OMF. FIG. 4 is a waveform diagram showing timing signals in the embodiment of FIG. 1. 4...Data RAM. 7...Flag RAM. 11...Address generation section, 19...First ROM. 22...Second ROM. 32...Third ROM. 26...First control circuit, 30...Second control circuit, 34...Third control circuit. Applicant: Nippon Electric Co., Ltd. Agent: Patent Attorney: Takeo Masuda

Claims (1)

[Claims] 1. After performing processing such as synchronization extraction, serial/parallel conversion, address extraction, error checking, and error correction on the recorded signal read from the recording medium, the digital-to-analog (D/A) converter A PQM recording and reproducing device that sends data to The decoder includes a random access memory (hereinafter referred to as data RAM) that stores input data of at least one field in the order of arriving blocks, and a random access memory (hereinafter referred to as data RAM) that stores the input data of at least one field in the order of arriving blocks, and one that stores the error check results of each block.
a random access memory (hereinafter referred to as flag RAM) that stores a flag to be cleared with (error) and O (correct); and an address generator that simultaneously supplies a common address to each address bus of the two RAMs; The data R
A.M. The address generating section generates and delivers a time signal for timely and predetermined operation of the flag RAM and the address generating section, and the address generating section generates a reference address for storing the field. A first dedicated memory for storing a circuit for calculating a field reference address (hereinafter referred to as a field reference address) and a procedure for calculating a reference address for each block (hereinafter referred to as a block reference address) using the field reference address as a reference. ROM), a second ROM that stores a procedure for calculating the address at which the 8 words in the block should be stored based on the block reference address of each block, and a second ROM that stores the 8 words of the final block directly from the field reference address. It includes a third ROM that stores a procedure for calculating an address to be stored, several adders, and three controllers that control output to the address bus, and the field reference address calculation circuit and the first The outputs of the ROM and the second ROM are added up to t, and the 8 in the field is
A signal representing a storage address of the edict is supplied to a first control circuit, and the first control circuit responds to the write signal by sending an input signal to a common address bus of the data RAM and flag RAM (field reference). The output of said adder calculating the 7 address is also added in another adder with an input signal representing the block number, said other adder adding a signal giving the address of the first edict of the last block to a second ROM. along with the output to a further adder, the further adder providing a second controller with a signal representing the storage address on each side of the final block, the second controller controlling the clock. An input signal is passed through the address bus in response to either a temporary storage command signal to the final block given from the generator or a read signal from the final block, and the output of the third ROM is the field reference address. is input to an adder different from the above-mentioned adder together with the output of the adder that calculates the . In response to the signal, the clock generator passes the input to the address bus, and before the input data is stored in the data RAM, the error flags corresponding to all commands in the field are set to ``1'' and all blocks are Error checking (CRC check)
After the last block of the field is stored in the memory area where it should be stored, it is immediately read out to a temporary memory appropriate for each colorimetry and subjected to a CRC check.
When the error flag as a result of the RC check is "0", the edict is stored at the address of the data RAM where it should originally be stored, and when the error flag is "1", the storage operation is not performed.
By repeating the above series of operations, one field of data is stored in the data RAM, and the error status is stored in the flag RAM, and the error flag rO of the last block edict is stored.
A decoder characterized in that a time signal is delivered to each component of the decoder so that it is supplied from the address by the output from the third ROM only when storing at time J.