JPS59221755A - Detecting system for runaway of processor - Google Patents

Abstract

PURPOSE:To simplify the constitution of a runaway detecting circuit by detecting the runaway of a processor of one side of a multi-processor system by a processor of the other side. CONSTITUTION:A local control (LP) program starts a global (GP) monitor program within a fixed time T1. Thus this monitor program compares the contents of a GP monitor flag area 9 with those of an LP monitor flag area 10. Then the contents of the area 10 are inverted if the coincidence is obtained, and at the same time a GP monitor timer area 11 is reset. If no coincidence is obtained, it is checked whether the value of the area 11 exceeds the GP timer value T2. If the value of the area 11 exceeds the value T2, it is decided that a GP processor 7 has a runaway. At the same time, a GP control program also starts an LP monitor program every fixed time T3. Thus a runaway of a local processor 8 can be detected in the same way.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a processor runaway detection method, and more particularly to a processor runaway detection method suitable for automatic diagnosis of a multiprocessor system connected via a shared memory. It is.

[Background of the invention]

The conventional processor runaway detection method in a processor system uses a special hardware circuit, as shown in Japanese Patent Laid-Open No. 57-86956, for example. A nodeware circuit for runaway detection is required.

That is, a global processor and multiple local
In a multiprocessor system consisting of processors,
As shown in Figure 1D, main memory 1 and global
A processor 7 is incorporated into one LSI, and each local processor 8 also has a corresponding local memory 2.
It is also incorporated into each LSI. In this case, the global processor 7 can write/write to the main memory 1 and the local memories 2 of all other LSIs, and each local processor 8 has the local memory 2 assigned to it. - Can only read/write memory 2. The global processor 7 and each local processor 8 independently execute programs and perform separate jobs, but if the local processor 8 malfunctions or the program runs out of control for some reason, After detecting them, the global processor 7 needs to stop the operation of the processor 8 in order to disconnect only that processor from the system. However, since the global processor 7 and the local processor 8 each execute programs independently, and there is no direct communication between the processors, it is impossible for one program to detect a runaway in the other program. be. Therefore, in the past, a hardware circuit 9 was attached externally to each LSI as shown in FIG. 1, and the program operation of each processor was constantly monitored, and when a program runaway was detected, this was reported to the global processor 1. ing. In response to instructions from the global processor 1, the reported hardware circuit 9 is activated, and the local processor 8 of the LSI connected to the hardware circuit 9 is stopped.

However, in this method, a special hardware circuit 9 is required to detect the escape of the processor 8 and to stop the operation. Therefore, the third. Fourth, when the number of processors increases, a hardware circuit for detecting and stopping runaway is required for the processors, which has the disadvantage of increasing product cost.

[Purpose of the invention]

An object of the present invention is to eliminate such conventional drawbacks and to provide a processor runaway detection method that can detect program runaway in a multiprocessor using a simple and inexpensive method without using any special hardware circuit. It is about providing.

[Summary of the invention]

In order to achieve the above object, the processor runaway detection method of the present invention includes a first processor that can read/write the entire memory of the system, and a first processor that can read/write only a part of the memory.
In a multiprocessor system consisting of one or more second processors that can write data, a processor monitoring flag area is provided in a memory area that can be read/written by the second processor, and the contents of the processor monitoring flag area are The feature is that the first and second processors are updated alternately, and runaway of the other processor is detected by monitoring the update status with a timer.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, memory 1 and local memory 2 are collectively referred to as global memory.

Global memories 1 and 2 have global memory addresses that do not overlap with each other.

The local memory control circuit 5 periodically connects and disconnects the global memory bus 3 and the U-cal memory bus using timing pulses from the clock pulse generator 6, so that the global processor 7 can access the four-cal memory 2 via the four-cal memory control circuit 5.

The global control program and the local supervisory program in the memory 1 operate on the global processor 7, and the local control program and the local supervisory program in the quadruple memory 2 operate on the local processor 8.

The global monitoring timer area 11 is an area that is updated at constant RflJJ(To) intervals by the local control program.

GP monitoring flag area 9 and LP monitoring flag area 1
0 is an area that is referenced and updated by the local monitoring program and the global monitoring program, and by alternately inverting this flag area between the local monitoring program and the global monitoring program, the status of the global processor 7 and the local processor 8 can be changed. monitor.

In FIG. 2, when the local control program starts the global monitoring program within a certain period of time (T1), the global monitoring program compares the contents of GP monitoring flag area 9 and LP monitoring flag area 10 and finds that they match. If so, LP monitoring flag area 10
At the same time, the contents of the global monitoring timer area 11 are reset, and if they do not match, the value of the global monitoring timer area 11 becomes the global monitoring timer value (T
Check whether 2) is exceeded. At this time, if the value of the global monitoring timer area 11 exceeds T2, it is assumed that a runaway in the global processor section has been detected. In addition, since the global control program also starts the local h=l rM program after a certain period of time (T3), the local monitoring program l-
i Compare the contents of GP monitoring flag area 9 and LP monitoring flag area 10, and if they do not match, transfer the contents of GP monitoring flag area 9 to LP monitoring flag area 1.0 (1
) (c) No processing is performed to match the valley. If they match, it is assumed that a runaway in the local processor section has been detected.

Here, Ti, T2. The timer value of T3 has the following relationship.

(TIX2)<(T3X2)<(T2)...
(1) Due to the above operation, the global monitoring program does not operate when the local processor 8 goes out of control, so the GP monitoring flag area 9 and the LP monitoring flag area 1 are
The contents of 0 remain consistent, and runaway of the local processor 8 can be detected the next time the local monitoring program is run.

Similarly, when the global processor 7 runs out of control, the local monitoring program does not operate, so the contents of the GP monitoring flag area 9 and the LP monitoring flag area 10 remain inconsistent, and the value of the global monitoring timer area 11 exceeds T2. Runaway of the global processor 7 can be detected by the global monitoring program that is started after the overflow occurs.

Incidentally, the buffer of main memory 1 in FIG.

The chief area stores a table of data used by the global processor 7, while the buffer and table area of the local memory 2 stores data tables used by the global processor 7.
A table of data used by processor 8 is stored.

FIG. 3 is a time chart when detecting a runaway in the local processor 8 in FIG. 2, and FIG. 4 is a time chart when detecting a runaway in the global processor 7.

As shown in FIG. 3, the local monitoring program is started every time T3, and the GP monitoring flag area 9 and LP
Compare the contents of monitoring flag area 10 and select one
”, and the other is different from “Ou”, it is determined to be normal and the GP monitoring flag is inverted. In FIG. 3, the program (LP) of the local processor 8 runs out of control at a certain point in time T1 when the global monitoring program starts, so the runaway is detected when the contents of flag areas 9 and 10 match. There is.

Next, as shown in FIG. 4, the global monitoring program is started every time T1, compares the contents of the GP monitoring flag area 9 and the Lp7 lag area 10, and determines whether one is l l IT , when the other is different from ``0'', one will be inverted within a short time (within the timer value T2) and both will match, so wait until then, and when they match, determine it as normal and set the LP monitoring flag. Invert. In FIG. 4, at a certain point in time T3 when the local monitoring program starts, the program (GP) of the global processor '7
flag area 9. due to out of control. Even if the value of lO becomes inconsistent and the global monitoring timer value (T2) exceeds, by continuing to disagree, GP
Runaway is detected.

As described above, in the embodiment shown in FIG. 2, the GP monitoring flag area 9 and the LP monitoring flag area 10 are provided in the local memory, and the contents of these areas are alternately read by the global monitoring program and the four-cal monitoring block. By looking down, you can detect if your processor is running out of control.

Although FIG. 2 shows the case where there is only one local processor 8, even in the case where there are two or more local processors 8, a local memory control circuit M5 is provided for each a-local processor, and each local In memory 2, there is a G similar to that shown in Figure 2.
P monitoring 7 lag area 9 and LP monitoring flag area 10
By providing a g-run of each local processor 8, it is possible to detect the g-run of each local processor 8.

Furthermore, as for the method of disconnecting the runaway local processor 8 or global processor 7 from the system, there is a "program stop method" previously proposed by the present inventors.
(Refer to the specification of Japanese Patent Application No. 187415/1983).

〔Effect of the invention〕

As explained above, according to the proposed IJ, runaway of one processor in a multiprocessor system can be detected in other processors, so there is no need to install a special hardware circuit. <, it is possible to simplify the hard query and reduce the cost of the entire circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional processor fog detection method, FIG. 2 is a block diagram of a multiprocessor system showing an embodiment of the present invention, and FIG. FIG. 4 is a time chart when detecting local processor runaway and global processor runaway, respectively. 1.2 Nigellobal memory (main memory and local memory), 5: Local memory control times m, 6
: Clock Pulse J, Rake, 7: Glow Pal Processor+, 8: C-Cal Processor.

Claims (1)

[Claims] (1) In a multiprocessor system consisting of a first processor that can read/write the entire memory of the system and one or more second processors that can read/write only a part of the memory, the second processor A processor monitoring flag area is provided in the memory area that can be read/written by the processor monitoring flag.
A processor runaway detection method, characterized in that the content of the area is updated alternately by the first and second processors, and runaway of the other processor is detected by monitoring the updated state with a timer.