JPS59221033A - Variable frequency divider - Google Patents

Abstract

PURPOSE:To obtain a variable frequency divider which can have a high-speed operation and a wide variable range of the number of divisions by using a D-FF within a prescaler and providing a variable delay element within a feedback loop ranging from the output of the D-FF to the set terminal of the D-FF. CONSTITUTION:The delay time amount of a delay element 11 can be controlled by the value (e) held at a latch 10. A basic clock fin is supplied to a D-FF14. When a clock is supplied to a clock terminal CLK of a D-FF13, the output Q is set at L level. While the output Q' is set at H level and sets the FF13 when the time set by the element 11 elapses. As a result, the output Q is set at H level and supplied to the terminal D of the FF14. A division clock fout with which the timing is set again by the clock fin is delivered from the output Q'. The output Q of the FF14 is supplied to the terminal CLK of the FF13, and therefore the clock fout divided synchronously with the fin is obtained. Thus the number of frequency divisions can be continuously varied by setting properly the delay time of the element 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a variable division divider that has a wide range of frequency division ratios and is suitable for high-speed operation.

[Background of the invention]

When a preset counter is used as a means for variable frequency division, the frequency of the basic clock is limited by the operating speed of the counter, so it is difficult to increase the resolution of the divided clock.

For this reason, conventionally, a grease scrubber was installed before the preset counter to increase the frequency of the basic clock and increase the resolution of the divided clock, but the minimum division number was limited by the variable division ratio of the grease scrubber. Therefore, there was a drawback that the variable frequency division range was narrow.

FIG. 1 is a circuit diagram of an example of a conventional 2-modulus prescaler, and FIG. 2 is a block diagram of an example of a variable frequency divider using the 2-modulus prescaler.

A conventional example will be specifically explained with reference to FIGS. 1 and 2.

This precipice number 7 is Orgate 1. and gate 2
．． It is composed of a NOR gate 3 and a D flip-flop 4.5.6, and divides the basic clock fIn to generate f o
It outputs nt.

The frequency division number is controlled by the selection signal SEL, for example,
When the selection signal SEL is at the "H" (high) level, the frequency division number is 5, and when the selection signal SEL is at the "I," (low) level, the frequency division number is 6.

Since it is not possible to continuously vary the frequency division number with a prescaler, counters 8 and 9 are connected as shown in FIG. Frequency division number N when data value "A"' is preset in counter 8 and data value II B T' is preset in counter 9
is expressed by the following equation (1).

N=f+,,/fo=6A+5 (B A)-A,+
5B ・・・・・・・・・(1)
The frequency division number N can be changed in steps of 1 by changing the value of data A, and in steps of 5 by changing the value of data B. Here, the minimum frequency division number that allows the frequency division number N to be continuously varied is 20, taking into consideration the condition that B≧A.

Generally, the dividing number of prescaler is t UII , tt
If L rp, there is a relationship of U='L-1-1, so the minimum frequency division number N m I that allows the frequency division number to be continuously varied
n is given by the following equation (2).

N, nln=L (L-1) --
-(2) That is, if the frequency division numbers U and L of the prescaler are set large for the purpose of lowering the operating speed of the counter, the minimum frequency division number N□. becomes large, and the variable range of the frequency division number N becomes narrow.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable frequency divider which eliminates the above-mentioned drawbacks of the prior art, is capable of high-speed operation, and has a wide variable range of frequency division number.

[Summary of the invention]

The configuration of the variable frequency divider according to the present invention includes a delay means that can set a delay time according to a frequency division ratio, and a feedback loop formed by this from a positive output terminal (or inverted output terminal) to a set terminal or a reset terminal. The first D flip-flop is created and the input terminal is kept at a low level (or high level), the other output terminal is connected to the input terminal, and the basic clock to be divided is input to the clock terminal. second to be done
A D flip-flop, and a delay element that delays the output of one of the D flip-flops by a certain value and uses the delayed output as a clock input of the first D flip-flop, and uses the other output of the second D flip-flop as a frequency-divided clock. This is the output.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 3 is a block diagram of an embodiment of the variable frequency divider according to the present invention, and FIG. 4 is an operation timing chart thereof.

Here, 10 is a launch related to the delay means, 11 is a variable delay element, 12 is a fixed delay element, 13゜14iJJ1
．． This is a second D flip-flop (hereinafter each simply referred to as a D flip-flop).

Note that the waveforms a to e in FIG. 4 are for the locations with the same symbols in FIG. It is assumed that the above value e is selected and rated as a desired value.

Basic clock f, n (waveform a) is D flip-flop 1
4 is supplied. When the positive edge (beginning of interval To) of the clock (waveform b) is input to the clock terminal CLK of the D flip-flop 13, its output Q (waveform C) becomes the IILL+ level.

On the other hand, the output Q becomes the "H" level, and the delay element 11
After the time set by has elapsed, the D flip-flop 13 is set. Therefore, the output Q becomes 'H' level in section T2.

The output Q is inputted to the input terminal of the D flip-flop 14, and the divided clock f,ut (waveform d) whose timing is resynchronized by the basic clock fIfi is outputted from the D flip-flop 14.
is output from. Here, the output Q of the D flip-flop 14 passes through the delay element 12, and the output Q of the D flip-flop 14 passes through the delay element 12.
Since it is input to the clock terminal CLK of No. 1, the frequency-divided clock f is frequency-divided in synchronization with the basic clock 'In. , [is obtained.

The frequency division number N is expressed by the following equation (3), where the period of the basic clock is T and the propagation delay time of each element is determined as follows.

(N-1)T<Tcqt+TA+Tsq+++TsgTz
+Tcqz+ T B < N-T
(3) However, TcQl is the propagation delay time from the tarlock terminal CLK of the D flip-flop 13 to the output Q, TA is the propagation delay time of the delay element 11, and TSQL is , T8ET2 is the propagation delay time from the set terminal SD of the D flip-flop 14 to the output Q, T8ET2 is the clock set-up time from the input of the D flip-flop 70 tube 140, and TcQ2 is the propagation delay time from the set terminal SD of the D flip-flop 14 to the output Q.
The propagation delay time from the tally clock terminal CLK to the output Q,
TB is the propagation delay time of the delay element 12.

Therefore, by appropriately setting the delay time of the delay element 11, the frequency division number N can be made continuously variable.

In FIG. 3, data e corresponding to the frequency division value 1/N is
The divided clock f out is held by the latch 10.
The propagation delay time of the delay element 11 is kept constant for one cycle period. That is, in the interval T3 of FIG. 4, the data e of the frequency division value 1/N is held in the latch 10 by the negative edge of the figure d, and the width of the negative pulse in the interval T5 to T7 of the figure d is controlled. Therefore, it is possible to continuously control the frequency division number N for each cycle of the frequency-divided clock f out.

As a variation of the above embodiment, as shown in FIG.
The same effect can be obtained by using the reset terminal CD of the flip-flop 13 instead of the set terminal SD and by reversing the connection of the outputs Q and Q.

In short, there is a difference between positive logic and negative logic, and they are basically the same.

As is clear from the above implementation 1, for example, since a D flip-flop is used instead of a counter in the prescaler, high-speed operation is possible, and the frequency division number can be determined from the output Q of the D flip-flop to the set terminal. By changing the propagation delay time of the delay element in the feedback loop of the SD, it can be easily and arbitrarily changed.

〔Effect of the invention〕

As described in detail above, according to the present invention, a variable frequency divider with a high speed and a wide variable range of the frequency division number can be obtained, so it can meet the demands of various electronic circuits, etc., and its effects are Remarkable.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram of an example of a conventional 2-modulus prescaler, and Fig. 2 is a block diagram of an example of a variable frequency divider using the 2-modulus prescaler. , FIG. 3 is a block diagram of an embodiment of the variable frequency divider according to the present invention, and FIG. 4 is an operation timing chart thereof. 10...Latch, 11. ．． 12...Delay element, 13°14...D flip-flop. 1ij, Agent: Patent attorney Kosaku Fukuda: (1 other person) Stem 1 LZ prisoner 3 b' /2

Claims (1)

[Claims] 1. A delay means that can set the delay time according to the frequency division ratio, and this creates a feedback loop from the positive output terminal (straddle inverted output terminal) to the set terminal (dimension set terminal), and A first D flip-flop whose input terminal is kept at a low level (or high level), and whose other output terminal is kept at a low level (or high level); A second D-flip 70 tube is connected to the clock terminal and the basic clock to be divided is input to the clock terminal, and the output of one of the two is delayed by a certain value to serve as the clock input of the first D-flip-flop. The output of one side of the second D flip-flop is a frequency-divided clock output, or a variable frequency divider.