JPS59220969A - Manufacture of planar type transistor - Google Patents
Manufacture of planar type transistorInfo
- Publication number
- JPS59220969A JPS59220969A JP9831283A JP9831283A JPS59220969A JP S59220969 A JPS59220969 A JP S59220969A JP 9831283 A JP9831283 A JP 9831283A JP 9831283 A JP9831283 A JP 9831283A JP S59220969 A JPS59220969 A JP S59220969A
- Authority
- JP
- Japan
- Prior art keywords
- region
- recess
- impurity
- base region
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000003321 amplification Effects 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000002253 acid Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- JVJQPDTXIALXOG-UHFFFAOYSA-N nitryl fluoride Chemical compound [O-][N+](F)=O JVJQPDTXIALXOG-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明はプレーナ形のトランジスタの製法に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a method for manufacturing a planar transistor.
プレーナ形トランジスタで高耐圧を得るには第１図に示
すようにコレクタン領域（１）内にベース領域（２）を
深く拡散し、底ｇｉＳ胸部の深部方向への曲率半径をで
きるたけ太き（していた。To obtain a high breakdown voltage with a planar transistor, as shown in Figure 1, the base region (2) is deeply diffused within the collector region (1), and the radius of curvature toward the deep part of the bottom giS chest is made as thick as possible ( Was.
それ故、電流増幅率を確保するためにエミッタ領域（３
）も深く拡散し、エミッタ領域とベース領域の底部間の
間隔であるベース幅を小さくしていたしかし、プレーナ
形トランジスタの電流増幅率はベース幅だけではなくエ
ミッタ領域（３）の不純物濃度とも間係し、この濃度が
大きい程、電流増幅率も大きくとれることかわかってい
る。Therefore, in order to ensure the current amplification factor, the emitter region (3
) also diffused deeply, reducing the base width, which is the distance between the bottom of the emitter region and the base region. However, the current amplification factor of a planar transistor depends not only on the base width but also on the impurity concentration in the emitter region (3). It is known that the higher the concentration, the higher the current amplification factor.
しかるに、エミッタ拡散を深くすればエミッタ領域（３
）と、ベース領域（２）の接合部伺近でのエミッタ不純
物濃度は薄くなり、電流増幅率の増大をははむ結果にな
っていた。However, if the emitter diffusion is made deeper, the emitter region (3
), the emitter impurity concentration near the junction of the base region (2) becomes thinner, resulting in an increase in the current amplification factor.
この発明は上記の点に鑑みてなされたものであり、その
目的とするところは高耐圧で、かつ電流増幅率の大きな
プレーナ形トランジスタの製法を提供することである。The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a planar transistor having a high breakdown voltage and a large current amplification factor.
この発明の要旨とするところはコレクター領域上にベー
ス領域を形成し、該ベース領域の中央部にエツチングに
より凹部を形成し、該凹部を介して不純物を拡散するこ
とによりベース領域内にエミッタ領域を形成することを
特徴とするプレーナ形のトランジスタの製法である。The gist of this invention is to form a base region on a collector region, form a recess in the center of the base region by etching, and diffuse impurities through the recess to form an emitter region in the base region. This is a method for manufacturing a planar transistor characterized by forming.
以下この発明を第２図及び第６図に示す一実施例に基づ
いて説明する。The present invention will be explained below based on an embodiment shown in FIGS. 2 and 6.
まず従来通りコレクター領域（１）となるウェハーの表
面に不純物を拡散してベース領域（２）を形成する。つ
づいてベース領域（２）の表面中央部を数ミクロンから
数十ミクロンの深さまでフッ硝酸系のエツチング液にて
エツチング除去してベース領域（２）の中央部に凹部（
４）を形成する。ｍ２図はこの状態を示す。First, impurities are diffused into the surface of the wafer which will become the collector region (1) to form the base region (2) as in the conventional manner. Next, the central part of the surface of the base region (2) is removed by etching to a depth of several microns to several tens of microns using a fluoro-nitric acid-based etching solution to create a recess (
4) Form. The m2 diagram shows this state.
このあと凹部（４）の表面よりベース領域（２）に不鈍
物拡散をおこなってベース領域（２）の表面にエミッタ
領域（３）を形成する。この工程も従来のプレーナ形の
トランジスタの製造工程と同一である。Thereafter, inert material is diffused into the base region (2) from the surface of the recess (4) to form an emitter region (3) on the surface of the base region (2). This process is also the same as the manufacturing process of conventional planar transistors.
層上の如くしてエミッタ領域（３）はベース領域（２）
の凹部（４）の内表面に形成される。As above the emitter region (3) is the base region (2)
is formed on the inner surface of the recess (4).
而して凹部（４）を設けて不純物を拡散するので、ベー
ス幅が小さくなるまで拡散しても不純物―艮は低下する
ことがなく、不純物の拡散は凹部（４）の内面にそって
おこなっているので拡散工程も容易におこなえるのであ
る。Since the concave portion (4) is provided to diffuse impurities, the impurity concentration does not decrease even if the base width is reduced, and the impurity is diffused along the inner surface of the concave portion (4). Therefore, the diffusion process can be carried out easily.
以上の如くこの発明によれば高耐圧であり、かつ電流増
幅率の大きなプレーナ形のトランジスタが得られるので
ある。As described above, according to the present invention, a planar type transistor having a high breakdown voltage and a large current amplification factor can be obtained.
第１図乃至第６図に示すのはこの発明の一実施例を示す
断面図である。
特許出願人
松下電工株式会社
代理人弁理士 竹 元 敏 丸
（ばか２名）1 to 6 are cross-sectional views showing one embodiment of the present invention. Patent applicant Matsushita Electric Works Co., Ltd. Patent attorney Toshimaru Takemoto (two idiots)
Claims (1)
ベース領域の中央部にエツチングにより四部を形成し、
該凹部を介して不純物を拡散することによりベース領域
内にエミッタ領域を形成することを特徴とするプレーナ
形のトランジスタの製法。(1) forming a base region on the collector region, forming four parts by etching in the center of the base region;
A method for manufacturing a planar transistor, characterized in that an emitter region is formed in a base region by diffusing impurities through the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9831283A JPS59220969A (en) | 1983-05-31 | 1983-05-31 | Manufacture of planar type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9831283A JPS59220969A (en) | 1983-05-31 | 1983-05-31 | Manufacture of planar type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59220969A true JPS59220969A (en) | 1984-12-12 |
Family
ID=14216401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9831283A Pending JPS59220969A (en) | 1983-05-31 | 1983-05-31 | Manufacture of planar type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59220969A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453572A (en) * | 1987-08-25 | 1989-03-01 | Mitsubishi Electric Corp | Semiconductor integrated circuit device with bipolar element |
| US6703283B1 (en) | 1999-02-04 | 2004-03-09 | International Business Machines Corporation | Discontinuous dielectric interface for bipolar transistors |
-
1983
- 1983-05-31 JP JP9831283A patent/JPS59220969A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6453572A (en) * | 1987-08-25 | 1989-03-01 | Mitsubishi Electric Corp | Semiconductor integrated circuit device with bipolar element |
| US6703283B1 (en) | 1999-02-04 | 2004-03-09 | International Business Machines Corporation | Discontinuous dielectric interface for bipolar transistors |
| US6939771B2 (en) | 1999-02-04 | 2005-09-06 | International Business Machines Corporation | Discontinuous dielectric interface for bipolar transistors |
| US7008852B2 (en) | 1999-02-04 | 2006-03-07 | International Business Machines Corporation | Discontinuous dielectric interface for bipolar transistors |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4049476A (en) | Method of manufacturing a semiconductor integrated circuit device which includes at least one V-groove jfet and one bipolar transistor | |
| JPH0481345B2 (en) | ||
| US4566174A (en) | Semiconductor device and method for manufacturing the same | |
| JPS59220969A (en) | Manufacture of planar type transistor | |
| US4977107A (en) | Method for manufacturing semiconductor rectifier | |
| JPS61180449A (en) | Dielectric-isolated semiconductor integrated circuit substrate and manufacture thereof | |
| JPS59200464A (en) | Manufacture of bipolar semiconductor device | |
| JPS63185063A (en) | Manufacture of semiconductor device | |
| JPS60144968A (en) | Semiconductor device | |
| JPS62282470A (en) | Mesa-type semiconductor device | |
| JPH027527A (en) | Transistor | |
| JPS6245065A (en) | Manufacture of semiconductor device | |
| JPH01290261A (en) | Semiconductor device | |
| JPS6142955A (en) | Manufacture of semiconductor device | |
| JPH0555557A (en) | Manufacture of semiconductor device | |
| JPH01134970A (en) | Manufacture of semiconductor device | |
| JPS62183174A (en) | Manufacture of semiconductor device | |
| JPH01196172A (en) | Semiconductor device | |
| JPS5914669A (en) | Manufacture of semiconductor device | |
| JPS59145570A (en) | Lateral bipolar transistor and manufacture thereof | |
| JPH05129314A (en) | Semiconductor device and its manufacture | |
| JPS58108772A (en) | Manufacture of transistor | |
| JPS6031273A (en) | Manufacture of high withstand voltage transistor | |
| JPS59167069A (en) | Manufacture of junction type field effect transistor | |
| JPS61160973A (en) | Semiconductor device |