JPS59219048A - Information transfer system - Google Patents

Abstract

PURPOSE:To attain the reduction in signal lines by using a data signal line and a clock signal line in common in a simple type information transfer circuit. CONSTITUTION:When a clock signal is applied to a drive control circuit CONT of a master device MAIN, the device controls a signal so as to be outputted with a signal level (b) opposite to a signal level (a) superposed on a signal line to drive circuits 1, 2. This level change is detected by a level detecting circuit LEV at a slave device SUB so as to bring the level (a) of the drive circuit 2 into the same level (b). Then the master device MAIN brings the drive circuit 1 into off-state after a certain time is elapsed, and the output is obtained by the drive circuit 2 only. The drive circuit 1 of the slave device SUB inverts a signal line after a prescribed time from this change point when a data is at ''1''. The master device MAIN detects it, a data reproducing circuit DPR reproduces the data and the drive circuit 2 is brought into the state of signal line.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) 1 Technical Field of the Invention The present invention relates to an information transfer circuit, and particularly to a simplified information transfer circuit.

(b), Prior art and problems Figure 1 (al is a diagram showing data transmission by the prior art;
(bl is a diagram for explaining the above operation.

In the figure, A and B are data transmission devices, respectively.

In Figure 1(a), when transmitting data from device B to another device in serial format, the data is transmitted in synchronization with the clock of device A, which is the main device, and for this purpose, the data signal is line and clock signal line are required.

As mentioned above, such a conventional data transmission system requires a data signal line and a clock signal line, so when the number n of slave stations increases, 2n sets of communication lines are required, which is uneconomical and complicated.

(C)1 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
The object of the present invention is to provide an information transfer circuit that can reduce the number of signal lines by sharing the data signal line and the clock signal line.

(d29 Configuration of the Invention According to the present invention, the above object is to supply a clock from the main device side to the slave device side, and to send data from the slave device side to the main device side in synchronization with the clock. In the data transfer method, the main device transmits the clock signal by taking a level (3) different from the level I of the signal line before starting communication, and then the slave device detects the level change of the signal line. detect and receive the clock signal, and the transmitted data is “
If it is 1'', it sends out a level I that is different from the level of the signal line, and if it is 0, it sends out a level ■ that is the same as the level of the signal line, and then the main device outputs the level I of the signal line at that time. This is achieved by providing an information transfer method characterized in that the clock signal is transmitted again by taking a level different from the above, and communication is performed by repeating this operation.

(e) 2 Embodiment of the invention FIG. 2 is a block diagram showing an embodiment of the invention.
AIN is the main device, SUB is the slave device, LINE is the signal line,
CLOCK is a clock regeneration circuit, DPR is a data regeneration circuit, C0NT is a drive control circuit, LEV is a level detection circuit, DRI VE 1 is a drive circuit 1, DRI V
E2 is operated by drive circuit 2.

Drive circuit IDRIVEI and drive circuit 2DRI
Both VE2 are circuits that output binary values, and the drive circuit I
The difference between DRIVE 1 and drive circuit 2DRIVE2 is that drive circuit IDRIVEI has a higher priority than drive circuit 2DRIVE2. The cross-level detection circuit LBV is a circuit that identifies these two values.

The present invention will be described in detail below with reference to FIG.

When a clock is applied to the drive control circuit C0NT of the main device MAIN, the drive control circuit C0NT controls the drive circuit IDRIVEI and the drive circuit 2DRIVE2 to change the signal level (currently a Control is performed so that the output is at a signal level (b level) that is opposite to the signal level (b level).

The slave device SUB side detects this level change using the level detection circuit LEV within its own device.Drive circuit 2DRIV
E2 is set to the same level (b level) as the signal level currently on the signal line LINE.

Next, after a period of time has elapsed, the main device MA I N turns off the drive circuit IDRIVEI, and turns off the drive circuit 2.
Output using only DRjVE2.

After a certain period of time from this change point, the slave device SUB side inverts the state of the signal line in the drive circuit 11DRIVE1 when the data becomes 1'', and leaves it as it is when it becomes o''.

The main device MAIN detects this with the level detection circuit LEV, reproduces the data with the data reproduction circuit DPR, and sets the drive circuit 2DRIVE2 to the signal line state. The data reproducing circuit DPR stores the level sent out by its own device and returns "0" if the received levels are the same, and "1" if they are different.
This is a circuit that determines that

The slave device SUB side maintains its state in the drive circuit 2DRIVE2 from the drive circuit IDRIVEI and prepares for the next data transmission.

Furthermore, in the system of the present invention, as is clear from the above explanation, the frequency of the received clock is half the frequency of the transmitted clock, so the frequency is doubled and supplied to the own station.

FIG. 3 is a time chart of data transmission and reception according to the present invention, taking as an example the case where the data transmitted from the slave device SUB to the main device MAIN is '011001'.

■ is the clock of the main device MAIN, ■ is the data to be transmitted “011001”, ■ is the level of the signal line, ■ is the slave device S
UB's reception clock, ■ is the recovered clock of the slave device SUB, and ■ is the reception data of the main device MAIN.

(f) Effects of the Invention As described above in detail, the present invention has the great effect of making it possible to share the data signal line and the clock signal line, thereby reducing the number of signal lines.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing data transmission according to the conventional technology.
(bl is a diagram for explaining the above-mentioned operation. In the figure, A and B are data transmission devices, respectively. Figure 2 is a block diagram showing an embodiment of the present invention.
AIN is the main device, SUB is the slave device, LINE is the signal line,
CLOCK is a clock regeneration circuit, DPR is a data regeneration circuit, C0NT is a drive control circuit, LEV is a level detection circuit, DRI VE 1 is a drive circuit 1, DRI V
E2 is a drive circuit 2. FIG. 3 is a time chart of data transmission and reception according to the present invention. Perforation 1 mouth = 261- 籏 3 old■ ■ 1OllflOIOI If■ --7-hee L1 o 710 θ

Claims (1)

[Claims] In a binary data transfer method in which a clock is supplied from the main device side to the slave device side and data is sent from the slave device side to the main device side in synchronization with the clock, the main device starts communication. The clock signal is transmitted by taking a level ■ different from the level I of the previous signal line, and then the slave device detects a change in the level of the signal line and receives the clock signal, and the transmitted data is “1”. If it is "0", it will send out a level ■ that is different from the level of the signal line; if it is "0", it will send out a level ■ that is the same as the level of the signal line, and then the main device will An information transfer method characterized in that the clock signal is transmitted again by taking a different level, and communication is performed by repeating this operation.