JPS59217291A - Mos dynamic memory - Google Patents

Abstract

PURPOSE:To increase the signal charge amount of a memory greatly without altering the structure of a cell nor using a high voltage higher than VDD as a word line signal by discharging a cell plate voltage with the word line signal, and recharging the cell plate within the time when a word line is driven selectively. CONSTITUTION:A cell plate voltage control circuit 13 includes an enhancement type p channel TR14a and an n channel TR14b of the same type. When the word line 5 selected by an X decoder 17 is driven by a word line driver 18, the rising of the terminal end 5b of the word line is delayed behind the rising of the driving terminal 5a of the word line 5, and the word line signal rises to discharge a cell plate 8 which is charged previously to the source voltage VDD. Then, the discharge of the cell plate corresponding to the waveform which delays the rising of the word line signal most is quickened. Further, the word line signal corresponding to a cell plate whose discharge is delayed rises fast and the transfer of a signal charge from the memory cell to a bit line 4 is performed at a high speed to compensate the delay of the word line signal.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a one-transistor type MOS dynamic RAM.
In this MO, it is possible to obtain a large signal at high speed by controlling the cell rate voltage with a word line signal.
This relates to S dynamic memory.

[Prior art]

Generally, in a one-transistor type MOS dynamic RAM, the presence or absence of charge accumulated in a MOS capacitor corresponds to binary information 1# and %01F. Then, the transfer gate is turned on to transfer the charge accumulated in the MOS capacitor to the bit line.

At this time, the sense amplifier circuit detects minute voltage changes that occur on the bit line depending on the presence or absence of charge.

FIG. 1 is a block diagram showing a memory array of a conventional MOS dynamic memory. (1) Memory cells are arranged in a matrix on the left and right sides of the screen, respectively, and a detailed cross section is shown in FIG. (2) is a sense amplifier circuit provided for each row of memory cells (1) arranged in a matrix, and (3) is a sense amplifier circuit provided for each row of memory cells (1) with the sense amplifier circuit (2) sandwiched between them. Dummy cells (4) are provided for each row of memory cells (1) and dummy cells (3), and bits are placed on the left and right sides of the sense amplifier circuit (2), respectively. L(5) is a word line arranged for each column of memory cells (1) on the left and right side;
) are dummy word lines arranged in the left and right dummy cells (3), respectively, (7) are connected to the left and right dummy cells (3), respectively, and φ and φP to which signals are sent.
(8) is a cell plate that applies voltage Vno to the memory capacity of the left and right σ memory cells (1) and dummy cell (3), and (9) is a power supply line.

Note that the memory cell (1) shown in FIG. 2 is connected to the bit line (4).
is made of metal, and the wand wire is made of an electrode material such as polysilicon, where al is the gate oxide film, ←υ is the N shadow region that forms the memory terminal, and the side a separates the memory cells from each other. It is a thick field oxide film.

Next, the operation of the MOS dynamic memory shown in FIG. 1 will be briefly explained. First, for example, when one of the word lines (5) on the left side is selected, the dummy word line (6) on the right side connected to a dummy cell with a capacity of approximately 1/2 of the memory capacity is selected. be done. Therefore, the signal charge is transferred to the corresponding left bit line (4) and the corresponding right bit line (4), and the minute potential difference that occurs at this time is detected and amplified by the sense amplifier circuit (2). be.

However, in the conventional HIOS dynamic memory, when the word line voltage reaches the vDD level, the amount of signal charge transmitted to the bit line (4) increases the memory capacity by Cs,
) If the threshold voltage of the transfer gate is VT, then
It was C5 (Vna VT). Furthermore, if the RC component of the word line is large, the word line signal is delayed and the read speed at the terminal end is delayed, making it unsuitable for high-speed operation.

[Summary of the invention]

Therefore, it is an object of the present invention to provide a MOS dynamic memory that can dramatically increase the amount of signal charge that can be handled, compensate for delays in word line signals, and transfer large signal charges to bit lines at high speed. be.

To achieve these objectives, the present invention adds a cell plate voltage control circuit that discharges the cell plate voltage with a word line signal and recharges the cell plate during the time that the word line is selectively driven. This will be explained in detail below using examples.

[Embodiments of the invention]

FIG. 3 is a block diagram showing an embodiment of a MOS dynamic memory according to the present invention. Q3 is a cell plate voltage control circuit whose detailed circuit is shown in FIGS. 4 and 5.

Note that the cell plate voltage control circuit shown in FIG. 4 (L: 1, (14a) enhancement type P
Channel transistor (14b) is an enhancement type N-channel transistor. Furthermore, in the cell plate voltage control circuit Q31 shown in FIG.
15a) is an enhancement type P channel transistor, (15b) and (15C) are enhancement type N
The channel transistor Qf9 is connected to the φG signal (Fig. 7(c)
)) is sent to the φG line (see FIGS. 4 and 5). Further, FIG. 6 shows an example in which the cell plate voltage control circuit shown in FIG. 4 is connected to the circuit for one word line shown in FIG. 3. In the figure, α7) is an X decoder, and θQ is a word line driver. 7(a) to 7(,) are diagrams showing each waveform in FIG. 3, and FIG. 7(,) shows the drive end (5a) of the word line (5).
Figure 7 (b) shows the waveform in Figure 6 (see Figure 6).
shows the waveform at the terminal end (5b) of the word line (5) (see Fig. 6), Fig. 7(c) shows the waveform of the φG signal, and Fig. 7(d) shows the waveform at the terminal end (5b) of the word line (5) (see Fig. 6). discharge end (8b
) (see Fig. 6), and Fig. 7(e) is a diagram showing the discharge waveform at the terminal end (8g) of the cell plate (8) (see Fig. 6). The operation of the MOS dynamic memory will be explained with reference to FIG. First, the X decoder←
When the word line (5) selected by η is driven by the word line driver Q1G, the word line signal is output from the driving end (the rising edge of As shown in FIG. 7 (+,), the rise of the word line end (5b) is delayed with respect to the upper shift.
When the word line signal rises with a delay as shown in FIG.
d) is delayed as shown in FIG. 7(e). The cell plate discharge corresponding to the waveform shown in FIG. 7(b) in which the rise of the word line signal is the most delayed is shown in FIG. 7(d).
As shown in , it becomes faster. In addition, since the word line signal shown in FIG. 7 (,) corresponding to the cell rate with delayed discharge shown in FIG. 7 (,) rises at μ speed, the memory cell (
Transfer of signal charges from bit line (1) to bit line (4) is performed at high speed, and word line signal delay is compensated for.

Furthermore, the word line (5
It can be seen that even if the level of ) is vDD, no loss occurs due to the threshold voltage vi of the transfer gate. On the other hand, charging of the cell plate (8) is done by the sense amplifier circuit 0)
After detection and amplification of new data or after a write operation, this is done by setting the signal φG times high level before the word line (5) is closed. If the data is 11/r, φG
The voltage at the memory terminal I, which was (VDD - Vt) when the double signal was at a low level, is boosted to (VDD - vT + αvDD) (When the data is %1, the transfer gate is cut off. (α is boost efficiency)
. If the data is %0〃, φ. The voltage of the memory terminal aυ, which was Ov when the signal was low level, is held at Ov even when the signal becomes high level φG times (when the data is 'ON', the transfer gate is conductive and the bit line is clamped to Ov by the sense amplifier).Then, the word line (5) is closed and the data is taken into the memory cell.As a result, approximately es (V
aa-V clove αVoa) (α is boost efficiency, usually ~
0,9) will be accumulated. As is clear from the circuit shown in FIG. 6, this cell plate voltage is charged and discharged only for the selected word line (5). Cell plate of unselected memory cell (1) (
8), since the unselected word line potential is Ov, the power supply voltage VD is increased by the conduction of the P-channel transistor (14M).
It is designed to be held at D level.

Note that even when the circuit shown in FIG. 5 is used as the cell plate voltage control circuit Q3, when the word line (5) becomes high level as in the case of FIG. 4, the cell plate voltage ( 8) is discharged and the cell plate (8) is recharged when the φG signal is set to high level while the word line is selectively driven. In this case as well, the cell plate voltage is discharged only for the selected word line (5). The cell plate (8) corresponding to the unselected word line (5) is held at the power supply voltage "DD" through the P-channel transistor (15a).On the other hand, the N-channel transistor (15c)
The function of is φ. When the signal remains at a high level, the gate capacitance of the N-channel transistor (15b) boots the level of the node to a level higher than the power supply voltage 11B by more than the threshold voltage of the N-channel transistor (15b). This is to fully transmit the φG signal level to the cell plate (8).

Further, in the above embodiment, the case of an N-channel type memory cell has been described, but it goes without saying that the same can be applied to the case of a P-channel type memory cell.

〔Effect of the invention〕

As explained in detail above, according to the MOS dynamic memory according to the present invention, the amount of signal charge in a one-transistor memory can be changed by changing the structure of the memory cell, or by using a high voltage higher than vDD for the word line signal. Without a doubt, 1.
Furthermore, word line delays due to RC components are compensated for, and a large signal voltage can be obtained at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory array of a conventional MOS dynamic memory, FIG. 2 is a cross-sectional view of a memory cell in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of a MOS dynamic memory according to the present invention. , FIG. 4 is a circuit diagram showing one embodiment of the cell plate voltage control circuit of FIG. 3, and FIG. 5 is a circuit diagram showing another embodiment of the cell plate voltage control circuit of FIG. 3. , FIG. 6 is a circuit diagram for one word line in FIG. 3, and FIG. 7(,) to FIG. 7(e)
6 is a diagram showing waveforms at various parts in FIG. 6. FIG. (1)...Memory cell, (2)...Sense amplifier circuit, (3)...Dummy cell, (4)...Bit line, (5)...Word line, (6)...Dummy word line, (7)...φ, line, (8)...Cell plate, (9)...Power line, ao...Gate oxide film , ao...Memory terminal, 07J...Field oxide film, (11...Cell plate voltage control times %, (14a)...P channel transistor, (14b)...Bone/N Channel transistor, (15a) ψ...P channel transistor, (15
b) and (15C)...N-channel transistor, (161...φ. Signal line, αη...X decoder, αυ...Word line driver, a9...
node. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A plurality of memory cells each consisting of one transistor and a memory capacity are arranged in the row and column directions, word lines are arranged in the row direction (or column direction), and bit lines are arranged in the column direction (
or row direction), and includes at least one transistor, discharges the voltage applied to the cell plate of each memory capacitor by the word line signal, and discharges the voltage applied to the cell plate of each memory capacitor by the word line signal, and the cell plate of the memory capacitor is In a MOS dynamic memory with a cell plate voltage control circuit for recharging the word line, the cell plate voltage control circuit is composed of one or two enhancement type N-channel transistors and one enhancement type P channel transistor, A MOS dynamic memory characterized in that it is arranged at a terminal end.