JPS5863161A - Mos dynamic memory - Google Patents

Abstract

PURPOSE:To obtain an MOS dynamic memory capable of transferring a large signal charge to a bit line at a high speed by discharging a cell-plate voltage with a word line signal, and recharging the plate within the time selectively driven at the word line, thereby compensating the delay of the word line signal by remarkably increasing the signal charge amount. CONSTITUTION:When a word line 5 selected by an X decoder 17 is driven by a word line driver 18, the rise of the end 5b of the word line is delayed as shown in Fig. c to the rise of the drive end 5a of the word line 5 as shown in Fig. b. At this time, the voltage of the cell-plate 8 charged in advance to the power voltage VDD is discharged by the rise of the word line signal shown in Fig. c, and it is also delayed to Fig. e as shown in Fig. f. The discharge of the cell-plate corresponding to the waveform shown in Fig. c delayed mostly at the rise of the word line signal is accelerated as shown in Fig. e. Since the word line signal shown in Fig. b corresponding to the cell-plate delayed in discharge shown in Fig. f is risen at a high speed, the transfer of the signal charge from the memory cell 1 to the bit line 4 is performed at a high speed, and the delay of the word line signal can be compensated.

Description

[Detailed Description of the Invention] This invention is a one-transistor type MOS dynamic RAM.
In the MO, it is possible to obtain a large signal at high speed by controlling the cell plate voltage with a word line signal.
This relates to S dynamic memory.

Generally, in a transistor-type MOS dynamic RAM, the presence or absence of charge accumulated in a MOS capacitor corresponds to binary information "1111%"0.''Then, the transfer 1 gate is turned on and charge is accumulated in the MOS capacitor. The generated charge is transferred to the bit line. At this time, a sense amplifier circuit detects minute voltage changes that occur on the bit line depending on the presence or absence of charge.

FIG. 1 is a block diagram showing a memory array of a conventional MOS dynamic memory. (1) is a memory cell arranged in a matrix on the left and right sides, and a detailed cross section thereof is shown in FIG. (2) is a sense amplifier circuit provided for each row of memory cells (1) arranged in a matrix, and (3) is a sense amplifier circuit provided for each row of memory cells (1) and on the left side and across the sense amplifier circuit. Dummy cells (4) provided on the right side are provided for each row of memory cells (1) and tummy cells (3),
Bit lines with sense amplifier circuits (2) arranged on the left and right sides respectively, word lines (5) arranged for each column of memory cells (1) on the left and right sides, and word lines (6) arranged on the left and right sides respectively. The dummy word lines (7) arranged in the dummy cells (3) on the right side are respectively connected to the dummy cells (3) on the left and right sides, and the 1P line to which the φ trend signal is sent, (
8) is a cell plate that applies voltage VDD connected to the left and right memory cells (1) and dummy cells (3).

Next, the operation of the MOS dynamic memory shown in FIG. 1 will be briefly explained. First, for example, when one of the word lines (5) on the left side is selected, the dummy word II on the right side is connected to a dummy cell with a capacity approximately 1/2 of the memory capacity! (6) is selected. Therefore, the signal charge is transferred to the corresponding left bit line (4) and the corresponding right bit line (4), and the minute potential difference that occurs at this time is detected and amplified by the sense amplifier circuit (2). be.

In conventional memory operation, the amount of signal charge transferred to the bit line (4) when the word line voltage reaches the VDD level is:
When the memory capacity is c8 and the threshold voltage of the transfer gate is vT, it was Cs (VDn-V7).

Furthermore, if the RC component of the word line is large, the word line signal is delayed and the read speed at the terminal end is delayed, making it unsuitable for high-speed operation.

Therefore, an object of the present invention is to provide a MOS dynamic memory that can dramatically increase the amount of signal charge that can be handled, compensate for delays in word line signals, and transfer large signal charges to bit lines at high speed. be.

To achieve this purpose, the present invention discharges the cell plate voltage with a word line signal and recharges the plate during the time when the word line is selectively driven. Explain in detail.

FIG. 2 is a block diagram showing an embodiment of a MOS dynamic memory according to the present invention. (2) is a cell plate voltage control circuit whose detailed circuits are shown in FIGS. 8 to 5.

In the cell plate voltage control circuit shown in FIG. 8, (14a) to (14c) are enhancement type transistors, and the cell plate voltage control circuit shown in FIG. In the voltage control circuit, (15a) is a depletion type transistor, (15b) is an enhancement type transistor, and in the cell plate voltage control circuit shown in FIG. 5, (16a) is a resistance element, and (16b) is an enhancement type transistor. FIG. 6 is a circuit diagram for one word line shown in FIG. 2, and shows an example in which the cell plate voltage control circuit shown in FIG. 8 is connected. In the figure, Q71 is an X decoder, α is a word line driver, Ql is a PR line to which the -PR signal shown in FIG. 7(a) is sent, and (e) is a line shown in FIG. 7(d).
The φG line (5a) to which the φG signal shown in FIG.
), the driving end of the word line (5) rises with the waveform shown in (5
b) is a word line (5) that rises with the waveform shown in FIG. 7(c).
), (8b) is the discharge end of the cell plate (8) that discharges with the waveform shown in FIG. 7(e), □ (8a) is the seventh
This is the end of the cell plate (8) shown in Figure (f).

Next, the operation of the MOS dynamic memory having the above configuration will be explained with reference to FIG. First, X decoder a
When the word line (5) selected at η is driven by the word line driver (to), the word line signal is transmitted to the drive end (5aX) of the word line (5) as shown in FIG. 7(b). As shown in FIG. 7(c), the rising edge of the word line terminal (5b) is delayed relative to the rising edge of the word line signal.At this time, due to the delayed rising of the word line signal shown in FIG. 7(c), the power supply voltage VDD is The voltage of the cell plate (8) that has been charged is discharged, but this discharge waveform is also delayed as shown in FIG. The discharge of the cell plate corresponding to the waveform shown in FIG. 7(c) where the discharge is the slowest is faster as shown in FIG. 7(e).In addition, the discharge of the cell plate corresponding to the waveform shown in FIG. Since the corresponding word line signal shown in FIG. 7(b) rises at high speed, the signal charge is transferred from the memory cell (1) to the bit line (4) at high speed.
Word line signal delays will be compensated for. moreover,
It can be seen that there is no loss in the signal charge read out at this time due to the threshold voltage of the transfer gate even if the level of the word line (5) is VDD. On the other hand, the cell plate (8) is charged by setting the φG signal to a high level after data detection and amplification by the sense amplifier circuit (2) or after a write operation and before the word line (5) is closed. When the data is 1'', the voltage at the memory terminal θυ, which was (VDD VT) when φG is low level, is boosted to (Vnn VT + αVDD) (when the data is 1'', the transfer gate is This is due to the cutoff; α is boost efficiency).

When the data is 0'', the voltage at the memory terminal aη, which was Ov when da was low level, is held at Ov even if φG becomes high level (when the data is 0'', the voltage at the memory terminal aη is Ov). The gate is conductive and the bit line is clamped to Ov by the sense amplifier).

Thereafter, the word line (5) is closed and data is taken into the memory cell. As a result, the signal charge is approximately C3
(VDD-V7+αVnn) (a is boost efficiency, usually ~09) will be accumulated. As is clear from the circuit shown in FIG. 6, this cell plate voltage is charged and discharged only for the selected word line (5). The cell plate (8) of the unselected memory cell (1) receives the precharge signal - during the precharge time.
It is maintained at the power supply voltage VDD level by PH.

Next, an example of the structure of the above memory will be explained using FIGS. 8 and 9. Here, a memory cell (1) is shown in which the bit line (4) is made of metal and the word line is made of an electrode material such as silicon, (8) is the cell plate of the memory capacity, and QQ is the cell plate of the memory capacity. The gate oxide film, αη, is an N shadow region constituting a memory terminal, (2) is a thick field oxide film separating memory cells from each other, and (2) is a P shadow region separating memory cells from each other.

In the memory cell according to the present invention, only the plate potential of the memory cell connected only to the selected word line changes, and the cell plate potential of the memory cell connected to other unselected word lines changes. Since it is clamped to the vDD potential, it is necessary to separate the cell plate electrodes of memory cells adjacent to each other in the pitch:1) line direction.

FIG. 8 shows the cell plate electrodes (8) of adjacent memory cells.
) is separated by a thick field oxide film @, high precision is required for positioning the field diffusion layer αη and the cell plate electrode (8).

FIG. 9 shows a structure that does not require alignment between the field diffusion layer αυ and the cell plate electrode (8), which is required in the structure of FIG. In this structure, cell plate electrodes (8) of adjacent memory cells are separated by P-type diffusion regions (b).

In this structure, after forming a word line (5) and a cell plate electrode (8) on the field diffusion layer Oυ by the usual method, P-type impurities are implanted using the cell plate electrode (8) itself as a mask. It is clear that the formed P-type diffusion region is self-aligned with the cell plate electrode (8).

Furthermore, it is clear that the structure shown in FIG. 9 allows higher integration than the structure shown in FIG.

As explained in detail above, according to the MOS dynamic memory according to the present invention, it is possible to change the signal charge amount of a one-transistor memory by changing the structure of the memory cell, or to use a high voltage higher than VDD for the word line signal. Furthermore, the word line delay due to the RC component is compensated for, and it becomes possible to obtain a large signal voltage at high speed. Further, according to the MOS dynamic memory according to the present invention, high integration of memory cells is possible while maintaining a large amount of signal charge.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a memory array of a conventional MOS dynamic memory, Fig. 2 is a block diagram showing an embodiment of a MOS dynamic memory according to the present invention, and Fig. 8 is a cell plate voltage control circuit of Fig. 2. FIG. 4 is a circuit diagram showing another embodiment of the cell plate voltage control circuit in FIG. 2, and FIG. 5 is a circuit diagram showing another embodiment of the cell plate voltage control circuit in FIG. 2. A circuit diagram showing an example, FIG. 6 is a circuit diagram for one word line in FIG. 2, FIGS. 7(a) to (f) are diagrams showing waveforms of each part in FIG. 6, and FIG. FIG. 9 is a structural diagram showing one embodiment of the memory cell of the MOS dynamic memory according to the present invention. FIG. 9 is a structural diagram showing another embodiment of the memory cell of the MOS dynamic memory according to the present invention. (1)...Memory cell, (2)...Sense amplifier circuit, (3)...Dummy cell, (4)...Bit line,
(5)...word line, (6)...dummy word line,
(7)...-P line 48)...Cell plate electrode, (
9)...Power supply line, 01...Gate oxide film, αη...
・Memory terminal, (6)...Field oxide film, α1・
... Cell plate voltage control circuit, (14a) ~
(14c)...Enhancement type transistor, (
15a)...Depression type transistor, (15
b)...Enhancement type transistor, (16a
)...Resistance element, (16b)...Enhancement type transistor, a7)...X decoder, (to)...
・Word line driver, 0... φRP line, (a)...
φG line, e])... P-type diffusion region agent Makoto Kuzuno - aη Figure 3 Figure 4 Figure 5 (φPR) (φq) Figure 7 Figure 8 Figure 9 Procedural amendment (voluntary) Patent Director-General of the Agency 1, Indication of the incident, Patent Application No. 161607/1982 2
, Title of the invention MOS dynamic memory 3, Person making the amendment 5, Detailed description of the invention column of the specification to be amended, and Specification of contents of the amendment are corrected as follows. -Peichi (2)

Claims (2)

[Claims] (1) Arrange the word lines in the row direction (or column direction) and the bit lines in the column direction (or row direction), discharge the cell plate voltage with the word line signal, and during the time when the word line is selectively driven. In a MOS dynamic memory that recharges its cell plate, the MOS dynamic memory is characterized in that the separation between cell plate electrodes of MOS capacitors of adjacent memory cells is formed by a diffusion layer having the same conductivity as the substrate. memory. (2) The M according to claim 1, wherein the diffusion layer is self-aligned with the cell plate electrode.
OS dynamic memory.