JPS592168A - Disconnection correction system - Google Patents

Abstract

PURPOSE:To reduce an error in the circumference of a terminal position of a symbol and to prevent a disconnection accident, by correcting the disconnection in the circumference of the terminal position of the symbol by a simple processing basing on an information of a lattice point label code, in an automatic input processing to a calculator of a logical circuit mixed with a handwritten inter- symbol connecting line and a character for signifying a name of a symbol, etc. CONSTITUTION:A logical circuit figure is read by an input device 10 and is sotred in a picture memory 12. A lattice point label code containing a four directions code for indicating a direction of a segment at each lattice point is found from a video signal obtained from the memory 12, and a logical gate symbol and wiring are recognized from the label code. Subsequently, terminal position and its direction of the recognized logical gate symbol, and the label code of the lattice point being close to the terminal position are compared by a lattice point label code decision circuit 48, and in case when the bit of the four directions code for indicating the connection between them indicates that there is no wiring, the bit of each four directions label code of the terminal position and its close lattice point is switched to a state that there is wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to symbols in logical notation handwritten with reference to predetermined grid axes, inter-symbol connection lines handwritten along the grid axes, and symbols. The present invention relates to a method for correcting disconnection of connection lines around the terminal positions of symbols in the automatic input processing into a computer of logic circuit drawings in which characters meaning names, etc., are mixed.

Background of the Technology Conventionally, logic circuit drawings were input into computers by hand using card punches or digitizers. In particular, when inputting connection lines into a computer, a person finds the terminal position of a symbol in the drawing, traces the connection line visually from there, and indicates the inflection point on the digitizer. A line was drawn between the terminal position and the inflection point). This method is not only very time consuming, but also a tedious and painful task for humans, and there is a considerable risk of input errors.

Therefore, automatic input devices are being actively developed, and the inventors and others are able to read logic circuit drawings that include a mixture of line figures and characters drawn along predetermined lattice axes using input devices such as FAX. 1. Automatic recognition method for handwritten line figures that compresses the information contained in the input video as a grid point label code that expresses the graphic structure in the vicinity of the grid points in units of grid points.''
6-48252) and ``Recognition method for line figures with circular shapes'' (Japanese Patent Application No. 56-201465), ``Pattern matching considering ambiguity'' that classifies and extracts single gate cell symbols based on the compressed information. Lag method" (Tokugan Sho-), "Recognition method for complex gate cell symbols in logic circuit drawings" (Tokugan Sho-), which recognizes composite gate cell symbols and single gate cell symbols from the classification results, and "Logic Numerous applications, including "Method for Recognizing Single Gate Cell Symbols in Circuit Drawings" (Patent Application Sho-) and "Method for Recognizing Terminal Positions of Cell Symbols in Logic Circuit Drawings" (Patent Application Sho-), which determines the terminal position of the symbol. doing.

Prior art and problems By the way, line breaks often occur in handwritten logic circuit diagrams. Line breakage is particularly likely to occur at the beginning and end of a line; for example, a connection line that should be drawn to the input/output end of a logic symbol often ends just before that. If such a drawing is input directly into a computer and automatically designed, the resulting circuit will have a disconnection just before and after the input/output of the logic gate, so it will be necessary to correct it at the stage of inputting it to the computer.

Purpose of invention The present invention attempts to correct such line breaks.

Line breaks also occur in the logic symbol itself, but this is corrected during the logic symbol recognition stage (by virtue of the logic symbol being li&ed).

Furthermore, although line breaks rarely occur during wiring, this correction has been considered separately, and what the present invention attempts to do is to There is a disconnection.

Structure of the Invention The present invention reads a logic circuit drawing including logic gate symbols and their wiring drawn along a lattice axis using an input device, and uses the obtained video signal to detect four directions indicating the directions of line segments at each lattice point. Find the grid point label code containing the code,
From the label code, select the logic gate symbol and wiring.
! ! In the line breakage correction method between the terminal position of the logic gate symbol and the wiring in the recognition method, the recognized terminal position and direction of the logic gate symbol are compared with the label code of the grid point closest to the terminal position. , when the bit of the 4-way code indicating the connection between them indicates no wiring, the bit of each 4-way label code of the terminal position and its nearest grid point is switched to indicate that there is wiring. However, this will be explained next with reference to the drawings.

Logic symbols appearing in logic circuit diagrams of embodiments of the invention include single gate cell symbols such as a Nand gate Ta), a flip-flop (b), and an AND and a NAND (c), as shown in FIG.
There are compound gate cell symbols such as , OR and NAND (d). The portion indicated by a thick line or a black circle is herein referred to as a terminal position. These, along with their connections, are handwritten along the predetermined lattice axes, that is, the vertical and/or horizontal lines of a lattice strip consisting of a large number of equally spaced parallel vertical and horizontal lines, and are handwritten along with similarly handwritten characters, etc. Logic circuits are constructed, automatically recognized, and input to a computer. Prior to that, the video signal is read by a reading device such as a facsimile, and the information contained in the obtained video signal is analyzed in grid units to determine the graphical structure near the grid points. Compress it into the grid point label code that represents it. This process is described above [
The format of the obtained lattice point label code is shown in FIG. 2.

As shown in the figure, this code consists of multiple bits (21 bits in this example), and the 17th to 20th bits are a 4-way code,
At the grid point (viewed as a rectangular area with a slightly enlarged field of view), it indicates whether the line runs up, down, left, right, or UDLR. For example, if it starts from the grid point and extends to the right, R=1 and U.

D and L are set to 0. If it extends vertically, U and D are 1, and R is O. The 13th to 16th bits indicate an ambiguous direction, and a bit 1 indicates "does not look like a line of a logical symbol". This corresponds to a four-way code, and for example, R=1, but if it is determined from the line width that this is not a logical symbol line, then FR=1. 12th
The bit is a misalignment flag. This flag F1 indicates whether a deviation exists or not, and the direction of the deviation is from the 8th to the 11th
It is indicated by ZD=Zn of the bit. Specifically, if a line segment drawn along a vertical or horizontal line (lattice axis) is not on the line correctly but is shifted above, below, to the left, or to the right, F1 = 1, and if it is shifted to the right. ZR=1. This has the purpose of preventing double selection. In other words, the field of view is wide enough to detect the line segment even if it shifts, so if it shifts to the right, the next grid point may appear to shift to the left (if it shifts to the center between the grid points) ), there will be double selection, but
This is to prevent this. The seventh bit is a bit indicating the presence or absence of an inverted logic symbol, and if this bit I is "1", it indicates that there is a small circle in FIG. 1, that is, an inverted mark.

The 6th bit is an ambiguity flag, and if this bit F2 is 1, the 13th to 16th bits are set to "1", specifically indicating that the grid point information is likely to be a character rather than a line segment. The second to fifth bits are bits provided in the present invention, and details will be described later.

The lattice point label code is extracted from the entire video signal of the logic circuit diagram developed in memory, and the above-mentioned "pattern matching method considering ambiguity" is applied to this result, as shown in Figure 1. Logic symbols as shown in FIG. 3 are recognized and a classification table of single gate cell symbols shown in FIG. 3 is created.

1 in Figure 3. j indicates the lattice point coordinates of the representative point of the logic symbol (indicated by a * mark in FIG. 1), No indicates the number of the logic symbol, and 5DRCT indicates the direction of the logic symbol.

Here, the direction indicates whether the logical symbol is pointing rightward, upward, leftward, or downward, and these are expressed as 0, 1, or 2.3. 5NO1 is the name of a single gate constituting the composite group l-, and is given here for now. The last FLAG is a flag indicating whether the search has been completed or not, and is used to prevent double selection. 1, 2, 3, etc. arranged in the vertical direction of the table indicate the order of logical symbols extracted and stored in the classification table, and T
OTAL is the number of logical symbols stored here.

After creating the classification table, "Recognition method for complex gate cell symbols in logic circuit drawings", "Recognition method for single gate cell symbols in logic circuit drawings", and "Recognition method for terminal positions of cell symbols in logic circuit drawings"
, to recognize a composite gate cell symbol and a single gate cell symbol, and extract the terminal position of the symbol and the direction of the connecting line coming out from the terminal position. The direction of the connection line coming out from the terminal position is represented by the second to fifth bits 5D-3R in FIG. The first bit ST is a terminal position flag, and when this flag is set (1), it means that the lattice point label code is located at the input/output terminal of the logic symbol.

1st bit I. indicates a confirmed reverse logic symbol,
The final result of the 7th bit is shown.

In the present invention, the lattice point label code of the terminal part of a logic symbol, especially the second to fifth bits S, indicating the terminal position and direction.
Detect line breakage using I3 to SR and the label code of the grid point next to the terminal part, especially its 4-way code D-R,
to correct. The procedure is shown in Figure 4.

Figure 4 (al is the case where the terminal direction is left, so the 2nd to 5th bits so""so of the lattice point label code are 0100. The 5th column in the figure shows the terminal direction, in detail, the terminal part of the recognized logic symbol. This diagram schematically shows the 2nd to 5th bits of the lattice point label code, and the 4th column shows the lattice points one lattice axis to the left (the lattice spacing is 2 mm in this example, so 2 mm to the left). The 17th to 20th bits of the label code are shown diagrammatically. Cases 1 and 2°3 are shown, and case l is when the 4-way code is 0100, that is, the line segment extends from the left and stops at the corresponding grid point. In case 2, the 4-way code is 0010, that is, the line segment comes down from above and stops at the grid point, and in case 3, the 4-way code is 100.
0 indicates that the line segment starts from below and stops at the corresponding 0 grid point. However, since there is a logic symbol terminal in this part as shown in the fifth column, the present invention determines that this is a line break caused by inaccurate drawing, and that it originally extends to the right by one grid interval. , the line segments are added as shown in the sixth and seventh columns. Specifically, L of the 4-way code of the terminal section is set to 1, and R of the 4-way code of the lattice point adjacent to the left thereof is set to 1. These glue, R
was, of course, 0 before this correction.

FIG. 4 tb) shows the case where the terminal direction is upward, and the fifth line illustrates this, and the fourth line schematically illustrates the four-way code of the grid point adjacent above. In cases 1, 2.3, the 4-way code is 00
In the case of 10.01.00.0001, it is determined that the connection from the grid point to the terminal part is missing, and the 6th to
As shown in the 8th column, D of the 4-way code of the grid point is set to 1, and U of the 4-way code of the terminal part is set to 1. Figure 4 (
C1 is for the case where the terminal direction is on the right, and dl is for the case where the terminal direction is at the bottom, and in both cases, the correction as shown in the figure is performed in accordance with the above.

Terminal position 1 that is likely to occur due to handwriting Neighboring line breaks can be corrected and line breaks can be avoided.

5 and 6 show an outline of an embodiment of the present invention.

10 is an image input device such as a facsimile; 12 is an image memory into which the output video signal of the device 10 is written;
14 is an address control section that generates an address signal for accessing the memory; 15 is an overall control section; 16, 18, 20
, 22. and 24 are a Higasaki circuit 16 which receives the readout output of the memory 12, a reference point detection circuit, a lattice conversion circuit (horizontal), a lattice conversion circuit (vertical), and an LB3 generation circuit.

26 is a table storing grid points detected by the reference point detection circuit 18, 28 and 30 are grid point label code generation circuits (horizontal) and the same (vertical), 32 is an LBL table, and 34, 36.38 are LBI ~LB3 table, 40
42.44 is the setting circuit of the verification window W, and 42.44 is the SXI, SYl, SX2. A table storing SY2, 46 is an address conversion circuit, 52, 54, 56, 5
8. and 60 are a pair processing circuit, a line pattern breakage correction circuit, a character removal circuit, a shift correction circuit, and an ambiguity correction circuit which perform processing upon input of the second line from the label table 50 of FIG. Furthermore, in FIG. 6, 62 is a symbol classification dictionary memory, 64 is a similarity calculation circuit, 66 is a classification table that stores the logical symbols recognized by the circuit, 68 is a composite gate cell recognition circuit, and 70 is a composite gate cell symbol recognition circuit. A dictionary 72 is a terminal position dictionary of composite gate cell symbols, 74 is a single gate cell recognition circuit, 76 is a candidate table for single gate cell symbols, and 78 is a recognition dictionary for single gate cell symbols. These are the same as the embodiment of the "method for recognizing terminal positions of cell symbols in logic circuit drawings", and the present invention adds a line breakage correction circuit 80 to this. The line breakage correction procedure performed by this circuit 80 is as described above.

Effects of the Invention According to the present invention, it is possible to correct line breaks around the terminal position of a symbol by simple processing based on the information of the grid point label code. Errors in the surrounding areas are reduced by 3, making it easier to extract connection lines and avoiding disconnection accidents.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of cell symbols and their terminal positions, Fig. 2 is an explanatory diagram of lattice point label codes, Fig. 3 is a classification table of single gate cell symbols, Fig. 4 is an explanatory diagram of line breakage correction processing, FIGS. 5 and 6 are block diagrams showing one embodiment of the present invention. In the drawing, DLUR is a 4-way code, 5D-s, and is a bit indicating the terminal position and its direction. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi 4

Claims (1)

[Claims] A logic circuit drawing including logic gate symbols and their wiring drawn along a grid axis is read by an input device, and the direction of a line segment at each grid point is indicated from the obtained video signal.
In a method of calculating a lattice point label code including a direction code and recognizing a logic gate symbol and wiring from the label code, in a method of correcting line breakage between the terminal position of the logic gate symbol and the wiring, Compare the terminal position and its direction with the label code of the grid point closest to the terminal position, and if the bit of the 4-way code indicating the connection between them indicates no wiring, compare the terminal position and its nearest grid point. each 4 of
A line breakage correction method characterized in that the bit of the direction label code is switched to indicate the presence of wiring.