JPS6322349B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to symbols in logical notation handwritten with reference to predetermined grid axes, inter-symbol connection lines handwritten along the grid axes, and symbols. In the process of automatically inputting logic circuit drawings that contain characters that mean names, etc. into a computer,
The present invention relates to a method for correcting disconnection of connection lines around terminal positions of symbols in the drawing.

Background of the Technology Conventionally, logic circuit drawings were input into computers by hand using card punches or digitizers. In particular, when inputting connection lines into a computer, a human finds the terminal position of a symbol in the drawing, traces the connection line visually from there, and indicates the inflection point on the digitizer (this A line is drawn between the terminal position and the inflection point)
This method was used. This method is not only very time consuming, but also a tedious and painful task for humans, and there is a considerable risk of input errors. Therefore, automatic input devices are being actively developed, and the present inventors use an input device such as a fax machine to read a logic circuit drawing containing a mixture of line figures and characters drawn along predetermined grid axes, ``Line pattern automatic recognition method'' (Japanese Patent Application No. 56-48252, Japanese Unexamined Patent Publication No. 57-162059) that compresses the information of the input video as a grid point label code that expresses the graphical structure in the vicinity of the grid points in units of grids and ``Circular "Recognition method for line figures" (Patent application 1983-201465;
103074), a "pattern matching method" that classifies and extracts single gate cell symbols based on the compressed information (Japanese Patent Application No. 57-43954;
161088), ``Composite figure pattern extraction processing method'' that recognizes compound gate cell symbols and single gate cell symbols from the classification results (Patent application No. 1610-
212792, Japanese Unexamined Patent Publication No. 58-117081), and "Single Gate Cell Symbol Recognition Method" (Japanese Patent Application No. 57-43953,
He has filed numerous applications, including ``Recognition method for the terminal position of a gate cell symbol'' (Japanese patent application No. 57-162473, Japanese Patent Application Laid-open No. 59-52385), which determines the terminal position of the symbol. .

Prior Art and Problems By the way, line breaks often occur in hand-drawn logic circuit diagrams. Line breakage is particularly likely to occur at the beginning and end of a line; for example, a connection line that should be drawn to the input/output end of a logic symbol often ends just before that. If you input such a drawing directly into a computer and have it automatically designed, the resulting circuit will have a disconnection just before and after the input/output of the logic gate.
It is necessary to correct it at the input stage to the calculator.

OBJECT OF THE INVENTION The present invention attempts to correct such line breaks. Line breaks also occur in the logic symbol itself, but this is corrected during the logic symbol recognition stage (because the logic symbol has been recognized). Furthermore, although line breaks rarely occur during wiring, this correction has been considered separately, and what the present invention attempts to do is to There is a disconnection.

Structure of the Invention The present invention reads a logic circuit drawing including logic gate symbols and their wiring drawn along a lattice axis using an input device, and uses the obtained video signal in four directions indicating the direction of line segments at each lattice point. In a method that obtains a lattice point label code including a code and recognizes a logic gate symbol (a composite gate cell symbol consisting of a single gate cell symbol and a set of single gate cell symbols) and wiring from the lattice point label code, the logic In the line breakage correction method between the gate symbol terminal position and wiring, a symbol classification dictionary pattern that classifies a single gate cell symbol to be recognized and describes the shape, etc. within a small rectangular area that constitutes a symbol for each classification group. and means for classifying and extracting single gate cell symbols by matching the four-way code of the grid point label code; The composite gate cell symbol recognition dictionary described by the address and the symbol classification extraction result are matched to recognize the composite gate cell symbol and each single gate cell symbol that constitutes the composite gate cell symbol, and further, the composite gate cell symbol By referring to the composite gate cell symbol terminal dictionary that describes the terminal position and status (the direction in which the wiring lines come out and the presence or absence of reverse logic symbols), the lattice point label code that constitutes the composite gate cell symbol can be determined. By referring to a means for setting information indicating the terminal position and its state, a single gate cell symbol recognition dictionary that describes the terminal position and its state of each single gate cell symbol, and the symbol classification extraction result, By performing matching with the four-way code of the lattice point label code that constitutes the classified and extracted symbol and the presence/absence information of the inverse logic symbol, single gates other than the individual single gate cell symbols that constitute the composite gate cell symbol are identified. means for recognizing a cell symbol and setting information indicating a terminal position and its state in a grid point label code constituting a single gate cell symbol; and based on the set grid point label code of the terminal position and its state. , examine the shape of the 4-way code of the grid point label code adjacent to the direction in which the wiring line exits from the terminal position, and check whether the lattice point label code adjacent to the direction of the wiring line from the terminal position is connected. The present invention is characterized by comprising means for setting the four-way code of each lattice point label code so that the four-way code of each lattice point label code is connected according to the shape of the adjacent lattice point label code when there is no lattice point label code. This will be explained with reference to

Embodiments of the invention Logic symbols appearing in logic circuit drawings include the first
As shown in the figure, there are single gate cell symbols such as NAND gate a and flip-flop b, and composite gate cell symbols such as AND and NAND c, and OR and NAND d. The portion indicated by a thick line or a black circle is herein referred to as a terminal position. These, along with their connections, are handwritten along the predetermined lattice axes, that is, the vertical and/or horizontal lines of a checkered strip consisting of a large number of equally spaced parallel vertical and horizontal lines, and are handwritten along with similarly handwritten characters, etc. Logic circuits are configured, automatically recognized, and input to a computer. Prior to that, the video signal is read using a reading device such as a facsimile machine, and the information contained in the obtained video signal is analyzed in lattice units to determine the graphical structure near the lattice points. Compress it into the grid point label code that represents it. This process is carried out using the above-mentioned ``line pattern automatic recognition method'' and ``circular line figure recognition method,'' and the format of the resulting lattice point label code is shown in FIG.

As shown, this code is multi-bit, 21 in this example.
The 17th to 20th bits are a 4-way code that indicates whether the line runs up, down, left, right, or UDLR at the grid point (viewed as a rectangular area with a slightly larger field of view). For example, if it starts from the grid point and extends to the right, R=1 and U, D, L
is set to 0. If it extends vertically, U and D are 1 and L and R are 0. The 13th to 16th bits indicate an ambiguous direction, and a bit 1 indicates "it does not look like a line of a logical symbol". This corresponds to a 4-way code, for example R = 1, but if it is determined that this is not a logical symbol line based on the line width etc.
F _R =1. The 12th bit is a deviation flag.
This flag F ₁ indicates whether a deviation exists or not,
The direction of the shift is indicated by Z _D to Z _R of the 8th to 11th bits. Specifically, the line segments drawn along the vertical and horizontal lines (lattice axes) are not on the line correctly, but above, below, to the left,
Alternatively, if it is shifted to the right, F ₁ =1, and if it is shifted to the right, Z _R =1. This has the purpose of preventing double selection. In other words, the field of view is widened so that the line segment can be detected even if it shifts, so if it shifts to the right, the next grid point may appear to shift to the left (if it shifts to the center between the grid points) ), double selection will occur, but this is to prevent this. The seventh bit is a bit that indicates the presence or absence of an inverse logic symbol, and if this bit is "1", it indicates that there is a small circle mark in FIG. 1, that is, an inverted mark. The 6th bit is an ambiguous flag, and if this bit _F2 is 1, the 13th to 16th bits are set to “1”.
Specifically, it indicates that the grid point information is likely to be a character rather than a line segment. The 0th to 5th bits are provided in the present invention, and the details will be described later.

Such lattice point label codes are extracted from the entire video signal of the logic circuit drawing developed on the memory, and the above-mentioned "pattern matching method" is applied to the result to create logic symbols as shown in Figure 1. are classified and extracted, and a classification table of single gate cell symbols shown in FIG. 3 is created. i in Figure 3,
j indicates the lattice point coordinates of the representative point of the logic symbol (indicated by a * in FIG. 1), NO. indicates the classification number of the logic symbol, and SDRCT indicates the direction of the logic symbol. Here, direction means that the logic symbol is facing right,
Indicates whether the direction is upward, leftward, or downward, and these are expressed as 0, 1, 2, or 3. SNO. is the name of the recognized single gate cell symbol and CNO. is the name of the recognized compound gate cell symbol. The last FLAG is a flag indicating that the symbol has already been recognized as a single gate cell symbol, or that it has finally been determined that it is not a symbol.
1, 2, 3, etc. arranged in the vertical direction of the table indicate the order of logical symbols extracted and stored in the classification table,
TOTAL is the number of logical symbols stored here.

After creating the classification table, use the "Composite figure pattern extraction processing method,""Single gate cell symbol recognition method," and "Gate cell symbol terminal position recognition method" to extract composite gate cell symbols and single Recognize the gate cell symbol, extract the terminal position of the symbol and the direction of the connection line coming out from the terminal position, and determine the presence or absence of the reverse logic symbol (2φ). The direction of the connection line coming out from the terminal position is represented by the second to fifth bits S _D to S _R in FIG. The 0th bit _ST is a terminal position flag, and when this flag is set (1), the lattice point label code is for the input/output terminal of the logic symbol. The first bit ₀ indicates a confirmed inverse logic symbol, and the seventh bit indicates a confirmed result.

In the present invention, the grid point label code of the terminal part of the logic symbol, especially the second label code indicating the terminal position and direction.
Line breakage is detected using the 5th bits S _D to S _R and the label codes of the lattice points adjacent to the terminal, especially the four-way codes D to R, and these four-way codes are corrected. The procedure is shown in Figure 4.

FIG. 4a shows a case where the terminal direction is to the left, so the second to fifth bits S _D to S _R of the grid point label code are 0100. Column 5 in the figure shows the terminal direction, specifically the second to second grid point label codes of the terminal part of the recognized logic symbol.
The 4th column shows the 17th to 20th bits of the label code of the lattice point one lattice axis to the left (the lattice spacing is 2 mm in this example, so 2 mm to the left). Shown diagrammatically. 1, 2, and 3 indicate cases, and case 1 indicates that the four-way code is 0100, that is, the line segment extends from the left and stops at the grid point. Case 2 has a 4-way code
[0010] That is, the line segment descends from above and stops at the grid point, and case 3 indicates that the four-way code is 1000, that is, the line segment moves up from the bottom and stops at the grid point. However, since there are logic symbol terminals in this part as shown in the fifth column, the present invention determines that these are line breaks caused by inaccurate drawing, and that they originally extend to the right by one grid interval. Add the line segments as shown in the sixth and seventh columns. Specifically, the L of the 4-way code of the terminal section is set to 1, and the R of the 4-way code of the grid point to the left of it is set to 1.
Make it. Of course, these L and R were 0 before this correction.

FIG. 4b shows a case in which the terminal direction is upward, and the fifth line illustrates this, and the fourth line schematically illustrates the four-way code of the lattice point adjacent thereto. Cases 1, 2, and 3 are 4
When the direction code is 0010, 0100, 0001, it is determined that there is a connection from the grid point to the terminal part, and the D of the 4-way code of the grid point is determined as shown in the 6th to 8th columns. 1, and also set U of the 4-way code of the terminal section to 1. FIG. 4c shows a case where the terminal direction is on the right, and FIG. 4d shows a case where the terminal direction is downward, and in both cases, the correction as shown in the figures is carried out in accordance with the above. By using such means, it is possible to correct line breakage near the terminal position, which is likely to occur due to handwriting, and avoid line breakage.

5 and 6 show an outline of an embodiment of the present invention. 10 is an image input device such as a facsimile; 12 is an image memory into which the output video signal of the device 10 is written; 14 is an address control unit that generates an address signal for accessing the memory; 15;
16, 18, 20, 22, and 24 are a verification circuit that receives the readout output of the memory 12, a reference point detection circuit, a grid conversion circuit (horizontal),
Same (vertical), and LB3 generation circuit. 26 is a table that stores the grid points detected by the reference point detection circuit 18, 28 and 30 are grid point label code generation circuits (horizontal) and the same (vertical), and 32 is LBL.
Tables 34, 36, 38 are LB1 to LB3 tables, 40 is a verification window W setting circuit, 42, 44 are SX1, SX1, SX2 output from the verification circuit 16,
SY2 is stored in the table; 46 is an address conversion circuit; 52, 54, 56, 58, and 60 are pair processing circuits that receive labels from the label table 50 in FIG. 11 and process them; a line pattern breakage correction circuit; They are a removal circuit, a deviation correction circuit, and an ambiguity correction circuit. Further, 62 in FIG. 6 is a symbol classification dictionary memory that stores a dictionary of logical symbols to be recognized and classified, and 64 is a symbol classification dictionary memory 62 and a four-way code of the grid point label code stored in the LABEL table 50. A similarity calculation circuit 66 calculates the similarity of
This is a symbol classification table that stores extracted logical symbols. Further, 68 is a composite gate cell symbol recognition circuit that utilizes a composite gate cell symbol recognition dictionary 70 that describes single gate cell symbols, which are individual logical symbols constituting a composite gate cell symbol, and their relative positions. hand,
The relative positional relationship of the single gate cell symbols stored in the symbol classification table 66 is examined to recognize the composite gate cell symbol. Reference numeral 72 is a terminal position dictionary of composite gate cell symbols, which contains the terminal positions of composite gate cell symbols (described by relative grid point addresses from the representative points of individual single gate cell symbols constituting the composite gate cell symbol). Its state (direction in which the connection line exits and information on the presence or absence of the reverse logic symbol (2φ)) is described. The composite gate cell symbol recognition circuit 68 further refers to the terminal position dictionary 72 of the recognized composite gate cell symbol and sets the 0th to 5th bits of the lattice point label code corresponding to the composite gate cell symbol. 74 is a single gate cell symbol recognition circuit, which includes a single gate cell symbol 76 that describes the number and number of single gate cell symbols belonging to each group for each classification group of single gate cell symbols; The symbols are classified and extracted on the symbol classification table using the single gate cell symbol recognition dictionary 78 that describes the symbol's terminal position (described as a relative grid point address from the symbol's representative point) and its state. In addition, lattice point label codes (four-way codes and inverse logic symbols (2φ)) corresponding to single gate cell symbols other than those recognized as individual single gate cell symbols constituting a composite gate cell symbol
(presence/absence information) and the single gate cell symbol recognition dictionary 78 (similarity calculation),
Recognize single gate cell symbols. Furthermore, the single gate cell symbol recognition circuit 74 refers to the recognition dictionary of the recognized single gate cell symbol and selects the 0th point label code of the grid point label code corresponding to that symbol.
~ Configure 5 bits. 80 is a line breakage correction circuit, and the line breakage correction procedure performed by this circuit 80 is as described above.

Here, we will provide additional explanations regarding the recognition of logical symbols and the creation of classification tables.

(a) Regarding "Logic symbol recognition": Logic symbols include single gate cell symbols and composite gate cell symbols consisting of a collection of single gate cell symbols. In order to recognize these logical symbols, the present invention uses three methods: "classification of single gate cell symbols", "recognition of composite gate cell symbols", and "recognition of single gate cell symbols".
The process consists of steps.

(a1) “Single gate cell symbol classification” =
"Creating a symbol classification table": Create and prepare symbol classification dictionaries (basically consisting of 4-way codes and don't care codes) corresponding to the single gate cell symbol to be classified, as many as the number of classification groups. , the four-way code of the grid point label code extracted from the input image data and the four-way code written in the symbol classification dictionary.
Logical symbols are classified and extracted by similarity calculation (matching) using a don't care code with a direction code, and a symbol classification table is created.

The similarity calculation starts from the grid point in the upper left corner (addresses are 1, 1), and first calculates the grid points in the size range described in the symbol classification dictionary from the grid point position 1, 1 in the upper left corner. Calculate the similarity of the label code with the four-way code. If this similarity is above a certain threshold,
i in the symbol classification table shown in Figure 3,
1, 1 is stored in the j column, and the classification number of the classification group of the single gate cell symbol corresponding to the symbol classification dictionary is stored in the NO column.
If the degree of similarity is below a certain threshold, a degree of similarity calculation is performed with the next symbol classification dictionary (classification dictionary for another classification group). In other words, for one grid point address, matching with all symbol classification dictionaries is performed until an address whose similarity is greater than a certain threshold appears. If it does not exist, move to the next grid point).
After completing the similarity calculation at grid point address 1, 1, move to the next grid point address 2, 1, perform similarity calculation, and if there is a similarity above a certain threshold, similarly, the symbol Store the grid point address and classification number in the classification table. In this way, similarity calculations are performed on all grid points to create a symbol classification table.

When performing similarity calculations, don't cares are effectively used to ensure that even if there are characters written inside or around the symbol to be classified, it can be classified and extracted without any problems.

For details, please refer to "Pattern Matching Method" (Japanese Patent Application No. 57-43954, Japanese Patent Application Laid-open No. 161088-1988).

(a2) "Recognition of composite gate cell symbols": A dictionary for composite gate cell symbol recognition that describes the positional relationship of each single gate cell symbol that constitutes a composite gate cell symbol using relative grid point addresses, and a composite gate cell symbol recognition dictionary. Uses a terminal position dictionary of composite gate cell symbols that describes the position and status of the terminals (the direction in which the connection line comes out from the terminal, and the presence or absence of the reverse logic symbol (2φ)).

First, matching is performed to check whether there is a symbol on the symbol classification table that matches the relative positional relationship of each single gate cell symbol of the component described in the compound gate cell symbol recognition dictionary. Recognize a composite gate cell symbol and identify the single gate cell symbols on the symbol classification table that constitute it. Next, referring to the terminal position dictionary of the recognized composite gate cell symbol, terminal state information is set in the 0th to 5th bits of the lattice point label code corresponding to the composite gate cell symbol.

For details, see "Composite figure pattern extraction processing method."
(Japanese Patent Application No. 56-212792, Japanese Patent Application No. 58-17081)
“Gate cell symbol terminal position recognition method”
(Patent Application No. 57-162473, Japanese Patent Application No. 59-52385)
Please refer to

(a3) “Single gate cell symbol recognition”: Terminal position and status of the single gate cell symbol to be recognized (direction of connection line, presence/absence information of reverse logic symbol (2φ))
Create and prepare a single gate cell symbol recognition dictionary that describes the compound gate cell symbols. Matching using a single gate cell symbol recognition dictionary for a single gate cell symbol (on the table) (4-way code of the actually extracted grid point label code and inverse logic symbol (2φ)
The single gate cell symbol that has been classified and extracted is finally recognized as a single gate cell symbol of one category.

At the same time, with reference to the symbol recognition dictionary of the recognized single gate cell symbol, terminal state information is set in the 0th to 5th bits of the lattice point label code corresponding to the single gate cell symbol.

For details, see "Single Gate Cell Symbol Recognition Method" (Japanese Patent Application No. 57-43953;
161087), ``Method for recognizing terminal positions of gate cell symbols'' (Patent Application No. 162473, 1983, Japanese Patent Application No. 162473,
59-52385).

(b) Regarding the creation of a "classification table": Logic is calculated by calculating the similarity between the 4-way code of the grid point label code extracted from the input drawing, the 4-way code written in the symbol classification dictionary, and the don't care bit. Recognize and classify symbols and create a classification table.

The similarity calculation starts from the grid point in the upper left corner (address is 1, 1), and first, from the grid point position 1, 1 in the upper left corner, the symbol corresponding to the dictionary described in the symbol classification dictionary is calculated. Calculate the similarity of the grid point label code within the size with the four-way code. If this degree of similarity is high, 1 and 1 are stored in the i and j columns of the symbol classification table shown in FIG. 3, and the logical symbol number corresponding to the dictionary is stored in the NO column. If the degree of similarity is low, a degree of similarity calculation is performed with the next dictionary (dictionary for another logical symbol). That is, for one grid point, matching (similarity calculation) with all logical symbols in the dictionary is performed until one with a high degree of similarity appears. After completing the similarity calculation at grid point address 1, 1, proceed to the next grid point address 2, 1 and perform similarity calculation, and if there is one with high similarity, similarly,
Store the address and logical symbol number in the symbol classification table. In this way, similarity calculations are performed on all grid points to create a symbol classification table.

For details, see "Pattern matching method (Special application
57-43954, Japanese Unexamined Patent Publication No. 58-161088).

(c) Regarding the specific mode of acquiring the "lattice point label code": Using the "line pattern automatic recognition method",
The 17th to 20th bits (four-way code), the 13th to 16th bits (ambiguous direction), and the
12 bits (misalignment flag: flag indicating that any of the 8th to 11th bits is 1), 8th to 11th bits (misalignment direction), 6th bit (ambiguous flag: flag indicating that it is likely to be a character rather than a line segment) ) is set. These pieces of information are extracted by processing the input drawing information in units of rectangular areas centered on grid points. Basically, it is extracted by projection processing of black pixels within a rectangular area and various window calculations. For details, see "Line pattern automatic recognition method (Japanese Patent Application No. 56-48252, Japanese Patent Application Laid-open No. 57-162059.
Please refer to ``No.

A reverse logic symbol (reversed mark) in the drawing is extracted using the "recognition method for line figures having a circular shape", and 1 is set in the seventh bit of the grid point label code at the extraction position. For details, see ``Recognition method for line figures with circles (patent application 1982-
201465, Japanese Unexamined Patent Publication No. 58-1030).

Using the "gate cell symbol terminal position recognition method", the lattice point label code extracted from the terminal position of the symbol is recognized, and the 2nd to 5th bits of the lattice point label code (of the connection line coming out from the terminal position) are recognized. direction), 0th bit (terminal position flag: indicates that any of the 2nd to 5th bits is 1), and 1st bit (confirmed inverse logic symbol: ``Recognition method for line figures with a circle'' The information of the 7th bit of the inverse logic symbol set by " is set for the lattice point label code of the candidate position where the inverse logic symbol may exist. Terminal position recognition method”
The candidates are narrowed down and the location of the inverse logic symbol is finally determined. The first bit is set to "1" for the lattice point label code at the position where the determined inverse logic symbol exists.

For details, see ``Gate Cell Symbol Terminal Position Recognition Method''
52385).

Effects of the Invention According to the present invention, it is possible to correct line breaks around the terminal position of a symbol by simple processing based on the information of the lattice point label code. Errors in the surrounding area are reduced, making it easier to extract connection lines and avoiding disconnection accidents.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of cell symbols and their terminal positions, Figure 2 is an explanatory diagram of grid point label codes, and Figure 3 is an explanatory diagram of cell symbols and their terminal positions.
FIG. 4 is an explanatory diagram of line breakage correction processing, and FIGS. 5 and 6 are block diagrams showing an embodiment of the present invention. In the drawing, DLUR is a 4-way code, and S _D to S _R are bits that indicate the terminal position and its direction.

Claims (1)

[Claims] 1. A logic circuit drawing including logic gate symbols and their wiring drawn along the grid axis is read by an input device, and the direction of the line segment at each grid point is indicated from the obtained video signal. 4. A grid point label code including a direction code is obtained, and a logic gate symbol (a composite gate cell symbol consisting of a single gate cell symbol and a set of single gate cell symbols) and wiring is recognized from the grid point label code. A symbol classification dictionary that classifies a single gate cell symbol to be recognized and describes the shape, etc. within a small rectangular area that constitutes a symbol for each classification group in the line breakage correction method between the terminal position and wiring of a logic gate symbol. Means for classifying and extracting single gate cell symbols by matching the pattern with the four-way code of the grid point label code; By matching the composite gate cell symbol recognition dictionary described by the grid address with the symbol classification extraction results, the composite gate cell symbol and each single gate cell symbol constituting it are recognized, and further, the composite gate cell symbol is recognized. By referring to the composite gate cell symbol terminal dictionary that describes the terminal position and status of the symbol (the direction in which the wiring lines come out and the presence or absence of reverse logic symbols), the lattice point label code that constitutes the composite gate cell symbol can be obtained. A means for setting information indicating the terminal position and its state in a single gate cell symbol, a single gate cell symbol recognition dictionary that describes the terminal position and its state of each single gate cell symbol, and by referring to the symbol classification extraction result. , the four-way code of the lattice point label code constituting the classified and extracted symbol and the presence/absence information of the inverse logic symbol are matched, and single gate cell symbols other than the individual single gate cell symbols constituting the composite gate cell symbol are means for recognizing a gate cell symbol and setting information indicating a terminal position and its state in a grid point label code constituting a single gate cell symbol; and a means for recognizing the terminal position and its state based on the set grid point label code. Then, check the shape of the four-way code of the lattice point label code adjacent to the direction in which the wiring line comes out from the terminal position, and check whether the 4-way code is connected to the lattice point label code adjacent to the direction of the wiring line from the terminal position. 1. A line breakage correction method characterized by comprising means for setting a four-way code of each lattice point label code so that the four-way code of each lattice point label code is connected according to the shape of the adjacent lattice point label code when the line breakage correction method is not connected.