JPH0430634B2 - - Google Patents

Description

[Detailed description of the invention]

(A) Technical Field of the Invention The present invention relates to a logic circuit diagram processing device, in particular, which reads handwritten drawings in which line figures drawn along lattice axes and graphic figures including characters are mixed, and extracts logic symbols and line segments. , and a logic circuit diagram processing device that recognizes and extracts graphic parts, is configured to summarize image data near grid points into an intensive grid point label code, and performs the above processing based on the intensive grid point label code. The present invention relates to a logic circuit diagram processing device that performs recognition processing. (B) Technical Background and Problems Conventionally, hand-drawn logic circuit diagrams have been input into data processing devices. It was supposed to be entered. In this case, for example, considering inputting a straight line, for each line, the operator needs to indicate the coordinates of one end of the line and the coordinates of the other end, and also input information indicating that it is a straight line. be. For this reason, this is not a problem when inputting relatively simple circuit diagrams, but when inputting extremely complex circuit diagrams such as IC circuits, data input becomes extremely complicated and requires considerable patience on the part of the operator. requires,
Furthermore, input errors are likely to occur. (C) Object and Structure of the Invention In view of the above points, the present invention aims to provide a processing device that automates the input processing of logic circuit diagrams, and it It is an object of the present invention to provide a processing device that performs the above processing by employing a method of consolidating image data in the vicinity of lattice points into an intensive lattice point label code for a drawn line figure. Therefore, the logic circuit diagram processing device of the present invention obtains symbols drawn along predetermined grid axes and connections between symbols by reading a handwritten drawing in which line figures and graphic figures including characters exist. In a logic circuit diagram processing device that recognizes and extracts line figures and drawing figure parts from image data obtained by processing a grid point, a lattice point label code generating means 107 generates a lattice point label code indicating the possibility of the existence of image data near a lattice point. , 109; a positional deviation verification means 103 for verifying the positional deviation of the image data with respect to the grid points based on the grid point label code; local shape extraction means 119 for identifying the possibility of the existence of a connector at the intersection when the image data intersects at the grid point; circular shape extraction means () for determining the possibility of the existence of circular image data in the vicinity; at least the grid point label code obtained from the grid point label code generation means; and the grid point label code obtained from the positional deviation verification means. Based on positional deviation information, local shape label information obtained from the local shape extraction means, line connector information obtained from the line connector extraction means, and circular shape information obtained from the circular shape extraction means. an intensive lattice point label code generating means 121 for determining an intensive lattice point label code that aggregates image data information in the vicinity of the lattice points; and recognition of single and compound symbols based on the intensive lattice point label code. Symbol recognition means 1
28, 129, 130, 131, 132, 13
3, 134, 135, 136, 137), and line segment extraction means 142, 14 for extracting symbol connection lines from the symbol information obtained by the intensive grid point label code and the symbol recognition means.
4, 145, 146, 148, and character area extracting means 147 for extracting character examples and separating characters from the intensive grid point label code and the image data. In addition, in the above, for example, code 1 is used for the lattice point label code generation means.
The reason why 07 and 109 are added is to clearly illustrate the correspondence with FIG. 4 and FIGS. 99A and B in the explanation that follows with reference to the drawings. The generation means is number 1 in the figure.
This does not indicate that it is unrelated to constituent units other than those shown as 07,109. The same applies to other codes. This will be explained below with reference to the drawings. (D) Embodiments of the Invention In the present invention, drawings drawn along the grid axes (X-axis and Y-axis) as shown in FIG. A drawing containing a mixture of drawings and figures is read with an optical reading device such as a facsimile input device, the read image data is aggregated as data on grid points (lattice axis intersection points), and then logical symbols and line segments are , and character parts, which are then processed for recognition, and then input to the data processing apparatus. Furthermore, the grid point G ₅ shown in Figure 2
If, for example, a line figure V shown in FIG. 3 exists around the grid point _G5 , as will be described later,
Within the range of the arrow shown in Figure ₂ centered on Whether the line segment exists, the deviation of the line segment to the existing position, etc. are extracted, aggregated, and stored as information on the grid point _G5 . Then, characters, logical symbols, etc. are recognized based on each aggregated lattice point label code, and inputted into the data processing device. FIG. 4 shows the overall configuration of an embodiment of a logic circuit diagram processing apparatus according to the present invention. Reference numeral 1 in the figure represents a drawing to be processed, and 2 represents processing result information extracted by the logic circuit diagram processing apparatus according to the present invention. Below, each component shown in Figure 4,...
Although a detailed explanation will be given according to the following, each component processing section, etc. can be roughly considered as follows. Input processing unit for drawings and various information. Drawing 1 is read by an input device such as a facsimile or a drum scanner, and the read image data is subjected to so-called preprocessing such as noise removal and smoothing, and then stored in an image memory. and,
Enter various information such as the size and orientation of the input drawing, the number of grids, etc. interactively using a display, keyboard, light pen, etc. In addition, in order to correct the input drawing's inclination and set the recognition area,
Input the coordinate position of the reference point (the "+" mark shown in FIG. 1) written in the corner. Label code generation processing section. The image data address of each grid point is calculated from information such as the orientation of the input drawing, the number of grids between reference points, and the position of the reference points, image data tilt is corrected, and images near each grid point are calculated. The lattice point labels and codes shown in Figure 5 show the shape features of the data.
Express as LOGLBL. Note that the lattice point label code first obtained in the processing section is called an initial lattice point label code LBL. Based on the label code LBL, an intensive lattice point label code is generated through processing by a first verification processing section, a second verification processing section, a local shape extraction processing section, etc., which will be described later. Here, each bit of the lattice point label code LBL or LOGLBL will be briefly summarized. #28 to #31 bit This bit is a direction code, and as described later, it expresses the direction in which the line segment extends when viewed from grid point _G5 .
(D), leftward direction (L), upward direction (U), and rightward direction (R), a logic "1" is set in the direction in which the line segment extends. Bits #24 to #27 These bits are "fuzzy" direction codes that indicate whether the line segment, if any, has a complex shape. In other words, whether or not it seems to be part of a character is expressed using logic "1". For example #24
Bit F _D being logic "1" indicates that the line segment (D=1) extending below the grid is likely to be part of a character. #19 to #22 bits These bits are deviation direction codes and indicate in which direction the existing line segment is deviation from the grid point. #12 to #15 bits These bits are gap direction codes, and indicate whether a break exists in a line segment extending in any direction, up, down, left, or right of the grid. #16 bit This bit is an "ambiguous" flag and is set to logic "1" when any one of bits #24 to #27 is logic "1". #23 bit This bit is a “deviation” flag,
When any one of #19 to #22 is logic "1", it is set to logic "1". #11 bit This bit is a gap flag,
When any one of bits #12 to #15 is logic "1", it is set to logic "1". #18 bit This bit is a line connector display flag, which means that the connection lines in the logic circuit diagram are electrically connected. This indicates whether or not a flag (referred to as a flag) exists at the grid point, and if it exists, it is set to logic "1". #9 bit This bit is a triangular display flag, and is set to logic "1" when a triangular pattern exists corresponding to the grid point. #10 bit This bit is a large circular shape display flag, and is set to logic "1" when a large circular pattern exists corresponding to the grid point. #17 bit This bit is a small circular shape display flag, and is set to logic "1" when a small circular shape pattern exists corresponding to the grid point.
It is said that #8 bit This bit is a symbol area flag and indicates that a logical symbol is written corresponding to the grid point. #0 bit The bit is a start point flag and indicates that the grid point is the start point (terminal position) of a logic symbol. #1 bit This bit is a reverse logic symbol display flag, and indicates that a small circular pattern (reverse logic symbol) that provides negative logic is attached to the start point indicated by the #0 bit. #2 and #5 bit This bit is a start point direction code, and indicates in which direction, up, down, left, or right, the connection line connected to the start point indicated by the #0 bit extends. Circle/triangle extraction processing section. It is extracted whether each pattern having the shape as shown in bit #9, bit #10, and bit #17 in the lattice point label code shown in FIG. 5 exists. Label code/noise processing section. Corresponding to the information of #11 to #31 bits of the generated initial grid point label code, noise existing in each piece of information is removed. Outward arm removal unit. The direction code corresponding to the arm protruding outside the frame of Drawing 1 is set to logic "0". Pair processing unit. Between mutually adjacent grid points, if there is an arm pointing toward the other at one of the grid points, and if there is no arm to be paired at the other grid point, the direction corresponding to the arm. Set the code to logic “0”. Line breakage correction unit. To correct line segments that should originally exist as one line into a connected form for line breaks within one grid interval. Misalignment correction 1 unit Extra misalignment direction code (#19 to #22 bit) and misalignment flag (#23)
bit) is set to logic "0". Ambiguity correction 1 unit Focusing on one grid point, ambiguous direction codes (#24 to #27 bits), etc. are corrected based on the grid point label codes of adjacent grid points in four directions. Symbol classification processing section. Based on the four-way code in the grid point label code, the position and shape (type) of the logical symbol in drawing 1 are extracted. However, in this process, it may be considered that classification is performed at the level of major classification. Complex gate symbol recognition processing unit. As shown in FIG. 6, the logic circuit diagram processing device of the present invention recognizes a set of a plurality of logic symbols as a so-called composite gate symbol C-G having a certain meaning. ing. This recognition processing unit recognizes composite gate symbols based on the type and positional relationship of each symbol. Then, for the recognized composite gate symbol, the lattice point label code at the start point position includes the start point flag (#0 bit), the start point code (#2 to #5 bit), and the inverse logic symbol display flag ( #1 bit). Symbol area setting processing section. Among the logic symbols to be read by the logic circuit diagram processing device of the present invention, one symbol may be extracted redundantly as different symbols depending on the reading state, as shown by arrows a and b shown in FIG. may occur. In order to correctly detect symbols that have been extracted repeatedly in this way, or to ensure that subsequent processing is performed correctly, a flag is set to clearly indicate that the information on the grid points is determined as part of the symbol. urge That is, the symbol area flag (#8 bit) shown in FIG. 5 is set to logic "1". Line segment confirmation processing section. After the symbol areas are determined, connection lines connecting the symbols are determined. Gap/vague arm processing part. After the connection line is established, the four-way code in that direction is set to logic "0" for the grid point that has the gap direction code (#12 to #15 bits) and the ambiguous direction code (#24 to #27 bits). Then, the same processing as that of the processing unit described above is performed. Single gate symbol recognition processor. In the symbol classification in the processing unit described above, extraction was performed based on the rough shape characteristics of the symbols, but in this processing unit, the two symbols in Figure 8A and the two symbols in Figure 8B As shown in the figure, symbols belonging to the same group are distinguished from each other by, for example, whether or not an inverse logic symbol C is attached as shown in the figure. make a decision Then, for the recognized single gate symbol, the start point flag (#0 bit), the start point code (#2 to #5 bit), and the inverse logic symbol are added to the grid point label code at the start point position. Set the display flag (#1 bit). Start point setting processing section. 2 symbols in Figure 9A, 2 in Figure 9B
Regarding the three symbols in FIG. 9C, etc., the shapes of the symbols are the same, but the directions and positions in which the connecting lines are drawn vary. To distinguish and identify each of these symbols, we examine the state of the symbol's starting point candidates,
The starting points of these symbols are determined and the starting point information is set in the grid point label code. Reverse logic symbol processing section. When processing symbols with inverse logic symbols as shown in Figure 10A, Figure 10B
As shown in three typical examples, the four-way code (#28 to #31 bits) in each lattice point label code near the inverse logic symbol is
It appears in various ways. If such a situation exists, it will have an adverse effect on later tracking processing, so as shown in Figure 10C, the extra 4
Make sure to drop the direction code. This processing section performs such processing. Line breakage correction processing unit near the start point. A so-called line break (gap) is likely to occur near the starting point position of a symbol. This processing section performs this correction processing. Preprocessing part for line segment extraction. Before finally extracting the connecting lines connecting symbols, preprocessing is performed. Gap/ambiguous arm processing unit At this point, the gap direction code (#12 to #15 bits) and the ambiguous direction code (#24 to #27 bits) are set at the lattice point, and the 4 in the corresponding direction is Drop the direction code (#28 to #31 bit). Then, a pair of processes similar to those of the above processing unit is performed. Line connector processing unit Performs predetermined processing (described later) on line connectors corresponding to branch points of connection lines. Line segment erasure processing unit in composite gate symbol The connection line in the composite gate symbol is a predetermined pattern, and there is no need to recognize this connection line. This unit erases this line segment. Connection line extraction processing section. In order to extract connection lines as individual vectors, start point - start point Branch point - branch point Bend point - bend point Start point - branch point Branch point - bend point Bend point - Track the 4-way code between starting points. Then, connect lines are extracted. For lines for which tracing is not completed, there is a possibility that the line is part of a character, and the ambiguity flag (#16 bit) of the grid point label code is set to logic "1". Character area extraction processing section. Once the symbols and connection lines have been extracted from the drawing 1, what remains are graphics such as characters. This processing section extracts a character area (image/figure area) based on the ambiguity flag (#16 bit) of the grid point label code. Character separation/recognition processing unit. For example, each character of the character example extracted by the processing unit is separated character by character, and character recognition is performed using character recognition processing technology. Result output processing section. The symbol information, connection line information, and character information extracted as described above are output to an external storage medium such as a floppy disk, or transmitted to another data processing device via a line. In the above, the processing carried out by each component processing section of the logic circuit diagram processing apparatus shown in FIG. [] Input processing unit for drawings and various information This processing unit correctly indicates the coordinates of the reference points (“+” marks at the four corners) shown in Figure 1 for subsequent correction of inclination and distortion. This is necessary. That is, the results inputted by this processing unit (contents on the image memory) are displayed on the television monitor, the coordinate position of the reference point on the display screen is indicated, and the subsequent processing is performed. At the time of correction, the correction is performed based on the coordinate position that should originally exist and the coordinate position of the input result. The input figure is stored on the image memory as having a size of, for example, 2048×3072 dots.
For this reason, the entire input graphic cannot be displayed as is on the television monitor at once, but is displayed in a reduced form. As a result, even if the reference point is indicated on the reduced display screen, sufficient accuracy cannot necessarily be obtained. In order to overcome this problem, the reference point is indicated with high precision by the procedure shown in the flowchart shown in FIG. That is, (1) First, the video data of the input figure is reduced to a magnification rate of 1/8, and the first half of the input figure (2048×1536
(dot) minutes. (2) Next, use the light pen to indicate the area where one of the reference points exists, and then display the area at a magnification of 1. (3) Next, write the area where the reference point exists.
After specifying with a pen, the area is displayed at a magnification of 8. (4) In this state, indicate the one reference point with a light pen. If the instruction cannot be made correctly, corrections are made until the instruction is made correctly, and when the instruction is made correctly, the instruction point is sent out as one of the reference points (written on the image memory as the first reference point). (5) Next, the first half of the input figure (2048 x 1536 dots) is displayed again at a magnification rate of 1/8, and the second standard is A point is written onto the image memory. (6) Next, the second half of the input shape (2048 x 1536 dots) will be displayed at a magnification rate of 1/8, and the above operation will be performed.
The third reference point is written on the image memory by operations similar to (2) to (4). (7) After that, the second half of the input figure (2048 x 1536 dots) is displayed again at a magnification rate of 1/8, and the fourth standard is A point is written on the image memory and becomes the end. [] Tilt correction of image data in the label code generation processing section. In the label code generation processing unit, based on the coordinates of the reference point input as described above, it detects how the reference point deviates from its original position and corrects the tilt and distortion of the image data. There is a need to. This process will be described below. Generally, the coordinates of the reference point are (0, 0), (X _W , 0), (0, Y _W ), (X _W , Y _W ) as shown in Figure 12A.
When the input drawing 1 given by is stored in an image memory, it may be stored in a rotationally distorted state as shown in FIG. 12B. For this purpose, as described above, when a reference point is indicated with a light pen on the input drawing 1-1 stored on the image memory, this indicated reference point becomes the first reference point.
In Figure 2B, for example, the coordinates (0, 0), (Xa,
Ya), (Xb, Yb), (Xc, Yc). Assuming that the input drawing 1 shown in FIG. 12 and the stored input drawing 1-1 match at the illustration origin (0, 0), the point (x, y) on the input drawing 1 is When compared with the point (x'-y') on Drawing 1-1 which has undergone rotational distortion, there is the following relationship: x'=xcosθ+ysinθ y'=ycosθ−Xsinθ --(1). Therefore, the point (x, y) on the input drawing 1 becomes the point (x', y') on the image memory.
It is sufficient to perform the correction assuming that the position is located at . However, performing the above correction for each pixel on the figure requires an extremely large amount of processing. For this reason, in the case of the present invention, the following correction is limited to the minimum amount of correction within the permissible range. That is, the input drawing 1 is divided into divided areas 3 each consisting of m×n pixels, and the coordinate position on the image memory of each divided area, for example, the upper left corner point (x ₀ , y ₀ ) of area 3-1, is determined. Determine whether it exists. In other words, the correspondence between (x ₀ , y ₀ ) and (x ₀ ′, y ₀ ′) shown in the diagram is
Determine based on formula (1). Then, the m×n
It is as if the divided area 3-1 given by pixels is the first
It will be assumed that the divided area 3'-1 is given by m×n pixels as indicated by the dotted line in FIG. 2B.
In other words, regarding drawing 1, if it is found that the upper left corner point (x ₀ , y ₀ ) of segmented area 3-1 corresponds to the coordinates (x ₀ ', y ₀ '), then the segmented area 3
In processing each pixel in -1 as being read, extract m pixels in the horizontal direction and n pixels in the vertical direction from the coordinate point (x ₀ ′, y ₀ ′) on Drawing 1-1. The m×n pixel segmented area 3'-1 thus obtained is read and processed. It will be easily understood that by adopting this method of dividing into each divided area, the amount of correction processing becomes 1/m·n. However, by adopting such a simplified method, the segmented area 3′−
It is necessary to evaluate how much error is included in each pixel within 1. When the size of segmented area 3'-1 is selected to be 10 x 10 pixels, and if an error of up to 2 pixels is allowed with respect to the true pixel position on input drawing 1, the calculated rotation angle θ is approximately 11 It is sufficient if it is less than ゜. Further, assuming that an error of at most one pixel is allowed, it is sufficient that the rotation angle is 5 degrees or less. Conversely, if there is actually a rotation of about 20 degrees,
Assuming that an error of up to 2 pixels is allowed,
This means that the size of the segmented area 3'-1 should be selected to be 5×5 pixels. Even when performing error correction using the simplified method described with reference to FIGS. 12A and 12B, it is complicated to measure the rotation angle θ, and measurement errors are likely to be introduced. For this purpose, the following process is taken. 13A and B are for example 4 of input drawing 1.
three reference points (0,0), (X _w ,0), (0,Y _W ),
It is assumed that (X _W , Y _W ) are given, and an arbitrary point (X, Y) becomes a point (X'-Y') on the rotationally distorted figure 1-1. From the above equation (1), there is a relationship of X'=Xcosθ+Ysinθ Y'=Ycosθ−Xsinθ. Here, as shown, X _W , Y _W ,
Considering X _L , Y _L , △X, △Y, X″, Y″, or Therefore, Also, X″=XX _L /X _W (∵X/X _W =X″/X _L ) Y″=YY _L /Y _W (∵Y/Y _W =Y″/Y _L ) Therefore It is expressed as Here, the above reference point (0,0) on input drawing 1,
(X _W , 0), (0, Y _W ), and (X _W , Y _W ) are known in advance. Then, display the figure 1-1 on, for example, a television monitor, and input the coordinates of the point corresponding to the reference point using a light pen or the like (0, 0).
If it is specified as (Xa, Ya), (Xb, Yb), (Xc, Yc), it is given as a known value as _XL = Xc - Xb △X = Xb Y _L = Yc - Ya △Y = Ya. [] Initial grid point label/code generation in the label code generation processing unit. When the inclination of the image data read onto the image memory is corrected as described above, in the present invention, as described above in connection with FIGS. 2 and 3,
Image data in the vicinity of grid point _G5 is expressed in the form of a grid point label code. The initial lattice point label code roughly grasps the graphical structure in the vicinity of the lattice point, and its generation method will be explained below. First, the image data obtained by reading a handwritten drawing is divided into grid axes X ₁ to X ₃ and grid axes Y ₁ to Y ₃ as shown in FIG. Window portions W _1-x and 1 of n×1 pixel size corresponding to grid axis n are centered on C ₅ .
A window W _1-Y with a size of ×n pixels is scanned in the X direction and Y direction, respectively. When even one black spot exists within this window, this is determined as the black spot detection output of each window "1". Hold this as part R _1-X and
Let R _1-Y hold each. As a result, for example, when the image data shown in FIG. 14 is scanned by the windows W _1-X and W _1-Y , the holding parts R _1-X and R _1-Y are in a state as shown by hatched areas, respectively. Above window W _1-X , W _1-Y
The output ``1'' as black point information from ``1'' will be retained as the projection result on each lattice axis. Next, as shown in FIG. 15A, rightward regions R ₀ and R ₁ are defined for the holding portion R _1-X, and the sum of "1" (indicating black point information) in these regions is determined. , if it is above a certain threshold, the grid point
The information "R=1" indicating that there is a possibility that a line segment exists in the right direction of _G5 is determined, and the information "R=0" indicating that there is no possibility if it is less than a threshold value is determined. In the same way, left direction regions L ₀ and L ₁ are defined and the sum of "1" in each region is calculated, and if this is more than the threshold value, there is information "L = 1" indicating that there is a possibility that a line segment exists in the left direction. ” is determined, and if it is less than the threshold, “L=
0" is determined. Of course, as shown in Figure 15B,
Also for the holding part R _1-Y , there are upper and lower regions U ₀ ,
U ₁ and _the downward regions D ₀ , D ₁ are defined _, and _the upward direction information _“ U=1 or 0'' and downward direction information ``D=1 or 0'' are determined. In this way, the initial grid point label code (LBL) D,
L, U, and R are calculated, and for example, for the image data in Figure 14, there is a possibility that line segments exist above and below, as shown in Figure 16A, but there is no possibility on the left and right. As shown in FIG. 16B, the grid point G <sub>5</sub>
Initial grid point label code for "LBL=1010"
is determined. In this way, for the image data as shown in FIG. 17A, the upper, lower, and
The initial grid point label code "LBL=1111" shown in Figure 17C is obtained to indicate that there is a possibility that line segments exist on the left and right sides, and for the image data shown in Figure 18A, , the left, right, and
"LBL=0111" shown in Fig. 18C is obtained to indicate that there is a possibility that a line segment exists in the upward direction.
Similarly, "LBL=0111" is obtained for the image data shown in FIG. 19A. [] Processing of the first verification processing unit in the label code generation processing statement. The first verification process is based on the above initial grid point label code.
Based on the LBL, it is verified whether a line segment actually exists in the vicinity of the grid point in the direction corresponding to the initial grid point label code LBL. First, as shown in Fig. 20, W <sub>V0</sub> , W <sub>V2</sub> , W <sub>H0</sub>
~W <sub>H2</sub> each first verification window section is provided. The first of these
The verification window is determined based on LBL, and when "R=1, L=1", the verification window is 1×n pixels.
Using the first verification window W <sub>V0</sub> , "R=0, L=1"
When "R=1, L=0", the first verification window section <sub>WV1</sub> of 1×(n/2+1) pixels is used, and when "R=1, L=0", the first verification window section of 1×(n/2+1) pixels is used. Use W <sub>V2</sub> . When "U=1, D=1", the first verification window section W <sub>Hp</sub> of n×1 pixels is used, and when "U=0, D=1", the first verification window section W Hp of (n/2+1)×1 pixels is used. One verification window W <sub>H1</sub> is used, and when "U=1, D=0", a first verification window W <sub>H2</sub> of (n/2+1)×1 pixels is used. and the second
As shown in Figure 1A and B, these first verification windows are set at the horizontal grid axis (or vertical grid axis) as the starting point,
The black point information is accumulated by sliding in the vertical direction (or horizontal direction), and the position where the first verification window is completely filled with "1" which is the black point information is first detected.
The slide width of this slide operation is half the distance between the grids in both the vertical and horizontal directions, that is, Fig. 21A and B
is within the range of n. This slide operation allows you to determine whether there is a line segment in the vicinity of the grid point in the direction according to the initial grid point label code, and if so, how far that line segment deviates from the grid axis. can be detected. Then, use these deviation information as the first
Extracted as verification deviation information SX1 and SY1. Here, the codes of SX1 and SY1 are displayed as follows. SX1: Horizontal shift + right direction; - left direction SY1: Vertical shift + downward direction; - upward direction However, there was no condition in which the black dot completely filled the window within the slide width of n pixels. In this case, set the value "999" for SX1 and SY1. If no line segment in the horizontal or vertical direction is detected as the initial grid point label code LBL, set the value "1000" for SX1 and SY1 to indicate that no slide operation was performed in that direction. do. FIGS. 22 to 25 show the state in which the first verification process is performed on various figures to verify their deviations. In Figure 22, the second
When the first verification window W <sub>H0</sub> in Figure 0 is slid four pixels to the right from the grid axis, the first verification window W <sub>H0</sub> can be filled with black dots, so "SX1 = +4". However, since "LBL=1010" there is no need to perform a sliding operation in the vertical direction, so "SY1=1000" is used to indicate this. Also, in Figure 23,
"LBL=1111", and at this time the first verification window
Since the first verification window portions W <sub>H0</sub> and W <sub>V0</sub> are filled with black dots on the lattice axes without the need to slide W <sub>H0</sub> and W <sub>V0</sub> , "SX1=0=0.SY1=0". In FIG. 24, "LBL=0111", and in this case, when the first verification window W <sub>H2</sub> is slid one pixel to the left, the first verification window W <sub>H2</sub> becomes a black dot, and the first verification window W H2 becomes a black dot. When W <sub>V0</sub> is slid 3 pixels downward, all of these can be made into black points, so "SX1=-1, SY1=+3". However, in the figure of FIG. 25, "LBL=0111", and when the first verification window W <sub>H2</sub> is slid one pixel to the left, all of the first verification window W <sub>H2</sub> can be made into black points. The second verification window uses the first verification window W <sub>V0</sub> .
Even if it slides by the width n shown in FIG. 1A, this first verification window <sub>WV0</sub> cannot be filled with black dots, and therefore "SX1=-1, SY1=999". The first verification deviation information SX1 obtained as above,
Based on SY1, move the rectangular area that captures the graphic structure near the lattice points, normalize the line segments within the rectangular area so that they are located on the lattice axes, and then
A lattice point label code is obtained again using the same method as the method used to extract the initial lattice point label code (LBL) above, and this is used as the first verification label code (LB1).
shall be. In this case, the normal compound in the X direction is as follows. In the case of "SX1=1000", "SX1=999", "SX1=0), the rectangular area does not move. And SX1>0"
When , the rectangular area is moved to the right by |SX1|, and when "SX1<0", the rectangular area is moved to the left |
Move only SX1｜. Similarly, normalization processing in the Y direction is performed as follows. In the case of "SY1=1000", "SY1=999", and "SY1=0", the rectangular area does not move. And “SY1＞
0", the rectangular area is moved downward by |SY1|, and when "SY1<0", the rectangular area is moved upward by |SY1|. For example, in the case of image data as shown in FIG. 26A, the rectangular area for "SX1=4" is moved by 4 pixels to the right (relatively, to the left of the image data). Since "SY1=1000", the rectangular area does not move in the vertical direction. As a result, a figure as shown in FIG. 26B is obtained, which is scanned by the windows W <sub>1-X</sub> and W <sub>1 -Y</sub> as shown in FIG. <sub>1-Y</sub> , black point information as shown in the shaded area in FIG. 26B is obtained. Based on this, the same process as explained in connection with FIG. 15 is performed to obtain the first verification label code LB1.
(LB1=DURL), and thus, in the figure of FIG. 26B, the first verification label code "LB1
＝1010'' is obtained. In the case of the image data shown in FIG. 27A, since "SX1=0, SY1=0", no movement is performed in the horizontal and vertical directions, and as a result, the first verification label code is "LB1=1111". , is the same as the initial grid point label code. Furthermore, in the case of the image data shown in FIG. 28A,
Because "SX1=-1, SY1=3", move the rectangular area by 1 pixel to the left and 3 pixels to the bottom (relatively, move the image data by 1 pixel to the right and 3 pixels to the top)
pixel movement) and performs the above processing, resulting in the first grid point label code LBL being the same as the initial grid point label code LBL.
Obtain verification label code "LB1=0111". Furthermore, in the case of the image data shown in FIG. 29A, since "SX1=-1, SY1=999", the rectangular area is moved by one pixel to the left and the first verification label code "LB1=0111" is added. get. [] Processing of the second verification processing section in the label code generation processing section. The second verification process includes the above first verification label code.
Based on LB1, the vicinity of the grid point is actually
Detects whether a line segment exists in the direction corresponding to verification label code LB1, and generates a second verification label code.
This is a process to obtain LB2, and according to the first verification label code LB1, as shown in Fig. 30, the second
Verification windows BW <sub>V0</sub> ~ BW <sub>V2</sub> , BW <sub>H0</sub> ~ BW <sub>H2</sub> are provided,
Verification is performed using the same method as the first verification process described above. As shown in FIG. 3, the size of each of these second verification windows is determined as follows, where WD is the width between the lattice axes on both sides of the lattice point <sub>G5</sub> . The manner in which these second verification windows are used is determined as follows. In other words, "R=1, L=1"
When , the second verification window BW <sub>Vp</sub> of 1×WD pixel is used, and when “R=0, L=1”, the second verification window BW <sub>V1</sub> of 1×(WD/2+1) pixel is used. "R=
1, L=0'', the second verification window BW <sub>V2</sub> of 1×(WD/2+1) pixels is used. And “U=1,
When D=1, the second verification window of WD×1 pixel
When “U=0, D=1”, use the second verification window BW <sub>H1</sub> of (WD/2+1)×1 pixel, and when “U=1, D=0”, use BW <sub>H0.</sub> A second verification window BW <sub>H2</sub> of (WD/2+1)×1 pixel is used. Then, each of these second verification windows is slid vertically (or horizontally) from the horizontal grid axis (or vertical grid axis) to accumulate black point information, and first, all of the second verification windows are The position to be filled with "1" which is black point information is detected. The sliding width of this sliding operation is within the range of n in FIGS. 21A and 21B, both vertically and horizontally, as in the case of the first verification window. Then, the deviation information obtained as a result is determined as second verification deviation information SX2, SY2 in the same manner as SX1, SY1 described above. For example, for the figure in Figure 30, "LB1=
When using the second verification window BW <sub>H0</sub> according to "1010" and sliding it one pixel from the grid axis, this second verification window BW <sub>H0</sub> can be filled with black dots, so "SX2 = 1 ”. However, “LB1=
Since there is no need to perform a sliding operation in the vertical direction from "1010", "SY2=1000" is used to indicate this. Furthermore, in FIG. 31, the second verification window portions BW <sub>H0</sub> and BW <sub>V0</sub> are used due to "LB1=1111". At this time, the second
The verification window BW <sub>H0</sub> is filled with black dots on the lattice axis, so there is no need to slide it and "SX2 = 0".
When the second verification window BW <sub>V0</sub> is slid downward by one pixel, it becomes a black dot, so "SY2=1". In FIG. 32, the second verification window portions BW <sub>H2</sub> and BW <sub>V0</sub> are used with "LB1=0111". At this time, when the second verification window parts BW <sub>H2</sub> and BW <sub>V0</sub> are located on the grid axis, they all become black dots, so "SX2
= 0, SY2 = 0''. However, in Fig. 33, the second verification window parts BW <sub>H2</sub> and BW <sub>V0</sub> are used due to "LB1 = 0111", but these second verification window parts BW <sub>H2</sub> and BW <sub>V0</sub> are changed to A and B in Fig. 21. Even if you slide within the indicated width n, it will not be possible to make all black points, so
"SX2=999, SY2=999". Second verification deviation information obtained as above
Based on SX2 and SY2, after further moving the rectangular area that captures the graphical structure near the lattice points and normalizing the line segments to more accurately position them on the lattice axes,
Again, the second verification label code LB2 is obtained in the same manner as the initial lattice point label code LBL and the first verification label code LB1 were extracted. That is, in FIG. 34A, "SX2=1, SY2=
1000'', so based on this, the rectangular area is moved one pixel to the right. At this time "SY2=1000"
Therefore, the rectangular area does not move in the vertical direction. As a result, a figure as shown in FIG. 34B is obtained, and based on this, the second verification label code "LB2=1010" is extracted in the same manner as when the above-mentioned initial lattice point label code LBL and first verification label code LB1 are extracted.
can be found. Also, in the figure of Figure 35A, “SX2=0, SY2=
1'' and moves the rectangular area downward by one pixel. As a result, a figure as shown in FIG. 35B is obtained, and based on this, the second verification label code "LB2=
1111". In the figure of Figure 36A, “SX2=0, SY2
= 0'', and the second verification label code ``LB2 = 0111'' can be obtained as shown in FIG. 36B. Furthermore, in the figure of FIG. 37A, “SX2=999,
SY2=999'', and the second verification label code ``LB2=0111'' can be obtained as shown in FIG. 37B. [] Processing of the local shape extraction processing section in the label code generation processing section. LBL, SX1, SY1, determined above
LB1, SX2, SY2, LB2, etc. represent the following items. Whether a line segment exists near the grid point. If a line segment exists near a lattice point, which of the four directions (up, down, left, and right) does the line segment belong to? When a line segment exists near a lattice point, how far does the line segment deviate from the lattice axis? This local shape extraction process is provided to capture even more detailed local shape features in addition to these graphic representations, and uses the first extraction window SW′ shown in FIG. 38 to extract grid points. It expresses the possibility of whether a line segment existing in the vicinity is a line segment of a line figure or a part of a character stroke. This local shape extraction processing is performed on the figure normalized by the processing up to the second verification processing section. In this case, within the rectangular area on each side of the first extraction window SW', the four
Define three regions R′ ₃ , U′ ₃ , L′ ₃ , D′ ₃ and
The following processing is performed on R′ ₃ to D′ ₃ . (1) As shown in FIG. 39A, each region R' ₃ , U' ₃ ,
Subdivide L′ ₃ and D′ ₃ to 1×n pixels or n×
It is regarded as a set of regions of one pixel. in this case,
Region R' ₃ is divided into sub-regions R' ₃₁ , R' ₃₂ , R' ₃₃ , region U' ₃ is divided into sub-regions U' ₃₁ , U' ₃₂ , U' ₃₃ , and region L' _{3 is divided into sub-regions R' 31 , R' 32 , R' 33} , It is divided into subdivision areas L′ ₃₁ , L′ ₃₂ , L′ ₃₃ , and area D′ ₃ is divided into subdivision areas D′ ₃₁ , D′ ₃₂ , D′ ₃₃
It is divided into (2) In each subdivision area, (i) the number of black dot clusters (the number of line segments) LSEG, (ii) the number of black dot clusters where the number of black dots (corresponding to the line width) is less than or equal to the threshold L _TH (The number of black dot clusters that can be considered as line width) ARi is counted. Note that the threshold value L _TH here is a threshold value of the line width determined from the resolution of the writing instrument, the input device, and the like. (3) Number of clusters of black dots in each subdivision area
LSEG, the ambiguity flag is set based on the number ARi of sunspot condensation lengths below the threshold L _TH .
Generate the following 2-bit information indicating FA and continuous arm CAM. LSEG=1, ARi=1 →FA=0.CAM=1 LSEG=0 →FA=0, CAM=0 Others →FA=1, CAM=1 (4) Area R' ₃ , U' ₃ , L' ₃ , the above (3) for each region of D′ ₃
Take the logical sum of the information obtained from , and divide this into 4
Two bits of information are provided for each region R' ₃ , U' ₃ , L' ₃ , and D' ₃ . ( _{5 )} The first extracted label _{code LB} shown in FIG. ′3. Here, the last 4 bits D', L', U', and R' in FIG. 39B are "1".
When , it indicates that a line segment runs in that direction, and F' _R ~ F' _D indicates that, for example, when F' _R is "1", a line segment running in the right direction is ambiguous. In other words, it indicates that the noise is hanging from a part of a line segment of a line figure, or that it is part of a character. When F′ _U is “1”, it means that the line segment running upward is ambiguous, that is, the same thing as explained above for F′ _R exists in the upward direction, and F′ _L is “ 1”, the line segment running to the left is ambiguous, and when F′ _D is “1”, the line segment running downward is ambiguous, as explained above for F′ _R. This means that these things also exist. When F' _F is "1", it indicates that one of the above F' _R to F' _D is "1". Therefore, the figure in Fig. 40 is used as the first extraction window.
When using SW′ to create the first extracted label code LB′3 based on the processing principles of (1) to (5) above,
Obtain “LB′3=000001010”. In this case, the fourth
There is no ambiguity in the figure in Figure 0, which shows that line segments run up and down. Then, if the first extracted label code LB'3 is created for the figure shown in FIG. 41, "LB'3=000001111" is obtained. In this case, there is no ambiguity, indicating that the line segments run vertically and horizontally. Also, if we create the first extracted label code LB'3 for the figure in Figure 42, we get "LB'3 = 000000111", which indicates that there is no ambiguity and that the line runs upward and left and right. ing. However, if you create the first extracted label code LB'3 for the figure in Figure 43, it will be "LB'3-100111111".
get. This indicates that although line segments exist above, below, to the left, and to the right with respect to the first extraction window SW', there is ambiguity in those in the upper and right directions. Generally, it is sufficient to perform the local shape extraction process using the first extraction window SW', but if an undesired break G exists in the line segment as shown in FIG. 44A, for example, the first extraction label code LB In '3, the third
Bit U' shown in FIG. 9B indicates logic "0". In order to improve this point, a second extraction window SW'' shown in FIG. 44 is used.The second extraction window SW'' is similar to the first extraction window SW shown in FIG. 38B. ′ and includes the above-mentioned region R′ ₃ ,
In addition to U′ ₃ , L′ ₃ , D′ ₃ , as shown in FIG. 44B,
It has areas R″ ₃ , U″ ₃ , L″ ₃ , and D″ ₃ . and,
In the same way that the first extracted label code LB′ ₃ was extracted above, the second extracted label code LB″ 3 is extracted using the above regions R′ ₃ , _U ′ ₃ , L″ ₃ , and D″ ₃ 45A and B show areas R' ₃ , U' ₃ , L' ₃ ,
It shows a state in which the first extracted label code LB'3 is extracted using D' ₃ . In addition, Fig. 45C and D are
Similarly, for the image data shown in FIG. 44A,
Second extraction label using R″ ₃ , U″ ₃ , L′ ₃ , D″ ₃
This shows the state in which the code LB″ ₃ has been extracted. When the first extracted label code _LB′3 and the second extracted label code LB″3 have been extracted, using these two codes, the local Shape extraction label/
Determine code LB3. each code

When displaying as shown in [Table], the local shape extraction label code LB3 is determined by the following logic. That is, first, LB'3 is assigned to LB3. And then, 〓 ｜ ｜ 〓 ｜ ｜ ｜ 〓R″=1&R=0→R=1, F _R =1, F _F =1, G _R =1
, G _F =1 | 〓R″=1&R=0→R=1, F _R =1, F _F =1, G _R =1
, G _F =1 U''=1&U=0→U=1, F _U =1, F _F =1, G _U =1, G
_F = 1 | 〓R″=1&R=0→R=1, F _R =1, F _F =1, G _R =1
, G _F =1 U''=1&U=0→U=1, F _U =1, F _F =1, G _U =1, G
_F = 1 L'' = 1 & L = 0 → L = 1, F _L = 1, F _F = 1, G _L = 1, G
_F = 1 | 〓R″=1&R=0→R=1, F _R =1, F _F =1, G _R =1
, G _F =1 U''=1&U=0→U=1, F _U =1, F _F =1, G _U =1, G
_F = 1 L'' = 1 & L = 0 → L = 1, F _L = 1, F _F = 1, G _L = 1, G
_F = 1 D″ = 1 & D = 0 → D = 1, F _D = 1, F _F = 1, G _D = 1, G
Execute the process of _F = 1, correct the LB3 obtained by substitution, and set the gap flag shown in Figure 5.
Generate information on G _F and gap direction codes G _D , G _L , G _U , and G _R. By the above processing, the breakage of the line pattern as shown in FIG. 44A can be sufficiently absorbed. Figure 46 shows
The local shape extraction label code LB3 obtained based on the code LB'3 shown in FIG. 45B and the code LB''3 shown in FIG. 45D, and the gap-related bits G _F , G _D , G _L , G _U , and G _R. Note that the extraction process in the gap direction is the same as the second one described above.
After normalizing the input image on the lattice axes through verification processing, projection processing is performed to extract the second verification label code. Extraction of the gap direction is based on the projection results in each direction. This is done by determining whether or not the results are consecutive. 47th
An example of processing is shown in FIG. [] Determination processing of the collective grid point label code (LOGLBL) in the label generation processing section. According to [] or [] above, initial grid point label code LBL; first verification deviation information SX1, SY,
1st verification label code LB1: 2nd verification deviation information
SX2, SY2, second verification label code LB2, and local shape extraction label code LB3 can be extracted. Then, all these extracted information are summarized in the fifth
A 32-bit aggregate grid point label code LOGLBL in the form shown in the figure is determined as follows. (1) When the initial lattice point label code LBL is all 0, the lattice point label code LOGLBL sets all 32 bits to "0", but when LBL is not all "0", the local shape extraction label code
If LB3 is all "0", only the #16th bit of the ambiguous flag in LOGLBL is set to "1", and the remaining 31 bits are set to "0". (2) If the first verification deviation information SX1, SY1 and the second verification deviation information SX2, SY2 are not "999", calculate SX, SY by the following formula. SX=SX1+SX2 SY=SY1+SY2 However, "SX1=1000" or "SX2=1000"
When "SX=0" is set, and when "SY=100" or "SY2=1000", "SY=0" is set. (3) Using this result, first clear LOGLBL, and then clear the lower 4 of LBL, LB1, LB2, and LB3.
The bits are ANDed and set in the lower bits of LOGLBL, ie, bits #28 to #31 in FIG. (4) Next, the absolute values of SX and SY above |SX|, |SY|
A deviation threshold value A _TH is set for , and the following processing is performed. This threshold value A _TH is set, for example, to half of n, which is the maximum movement distance of the window portion, or n/2. (4-1) If |SX|>A _TH , set the shift flag, #23 bit of LOGLBL shown in Figure 5, to "1". When "SX>0", the shift is to the right, so set bit #22 of LOGLBL to "1".
When "SX<0", the #20 bit of LOGLBL is set to "1" because it is shifted to the left. In addition, in order to prevent problems caused by moving the rectangular area too much, a threshold ^O _TH that is slightly smaller than the above A _TH is set, and the following processing is performed. |SX|＞ ^O In the case of _TH , if "SX>0", if the R bit of LBL is "1", it means that the right side of the lattice axis has been shifted too much, and the first trust in the situation
Set #31 bit of LOGLBL to "1". If "SX<0", and the L bit of LBL is "1", the #29 bit of LOGLBL is similarly set to "1". (4-2) If |SY|> _TTH , similarly to (4-1) above, set the shift flag, which is bit #23 of LOGLBL, to "1". When "SY>0", the shift is downward, so set bit #19 of LOGLBL to "1".
When "SY<0", there is an upward shift, so the #21 bit is set to "1". Also, if |SY|> ^O _TH , if "SY>0", if bit U of LBL is "1", then
Set #30 bit of LOGLBL to “1”. If “SY<0”, if the D bit of LBL is “1”, then
Set bit #28 of LOGLBL to “1”. (5) Then, process the ambiguous direction. (5-1) #31 bit of LOGLBL is “1” and
If the bit of _FR of LB3 is “1”, then
Set each bit of #27 and #16 of LOGLBL to "1". (5-2) #30 bit of LOGLBL is “1” and
If the F _U bit of LB3 is “1”, then
Set each bit of #26 and #16 of LOGLBL to "1". (5-3) #29 bit of LOGLBL is “1” and
If the F _L bit of LB3 is “1”, then
Set each bit of #25 and #16 of LOGLBL to "1". (5-4) #28 bit of LOGLBL is “1” and
If the bit of F _D of LB3 is “1”, then
Set each bit of #24 and #16 of LOGLBL to "1". (6) If the first verification deviation information SX1, SY1 and the second verification deviation information SX2, SY2 are both "999", the following processing is performed. (6-1) Clear LOGLBL, LBL, LB1,
Take the AND of the lower 4 bits of LB2 and LB3,
The lower 4 bits of LOGLBL, ie, bits #28 to #31, are set to the above logical product. (6-2) Set #16 bit of LOGLBL to “1”,
Indicates that the line segment is ambiguous and may be a character. (7) First verification deviation information SX1 and second verification deviation information
If both SX2 are "999" and the first verification deviation information is "SY1=1000", the same process as in (6) above is performed. (8) If the first verification deviation information SX1 is "1000" and the first verification deviation information SY1 and the second verification deviation information SY2 are "999", the same process as in (6) above is performed. (9) The first verification deviation information SX1 is “999” and the first verification deviation information SY1 and the second verification deviation information
This shows that both SX2 and SY2 were verified.
If it is smaller than "999", SX=SX2 SY=SY1+SY2 and processes (3) to (5) above are performed. (10) The first verification deviation information SX1, SY1 and the second verification deviation information SX2, SY2 are “SX1<999” and “SY1
=999” and “SX2<999” and “SY2<999”
In this case, SX = SX1 + SX2 SY = SY2 and process (3) to (5) above. (11) In cases other than (1) to (10) above, perform the following processing. SX1999→SX1=0 SX2999→SX2=0 SY1999→SY1=0 SY2999→SY2=0 SX=SX1+SX2 SY=SY1+SY2 and set bit #16 of LOGLBL to "1".
Perform the processing in (4) and (5) above. The expression of the aggregated grid point label code LOGLBL generated by the processes (1) to (11) above can be summarized as follows. (a) Is there a line segment near the grid point? this is
This can be determined by the 4-way code of #28 to #31 bits of LOGLBL. (b) If a line segment exists near a grid point, which direction of the four directions (left, right, top, and bottom) does the line segment belong to? Or is it a part of a line figure or a character? represents the possibility that it is part of the
This can be recognized by the #16 bit and #24 to #27 bits of LOGLBL, that is, the ambiguous flag and the ambiguous direction code. (c) If a line segment exists near a lattice point, in what direction is the line segment offset from the lattice axis? This can be determined by the #19 to #23 bits of LOGLBL indicating the shift flag and shift direction code. The aggregate grid point label code LOGLBL determined as described above is shown in FIGS. 49 to 52. In the case of the figure shown in Figure 49A, its LBL,
LB1~LB3, SX1, SY1, SX2, SY2 are (A)~
As shown in (G), based on these,
LOGLBL as shown in is obtained. For the figure in FIG. 50A, the LOGLBL shown in FIG. 50D is obtained in the same way, and the same is true for FIGS. 51 and 52. In this manner, according to the present invention, input image information can be compressed into grid point label codes, which are code information on grid points, by means of graphic representations near grid points. [] Recognition processing for line connectors in the label code generation processing section. The label code generation processing section checks whether or not the #18 bit (line connector display flag) in the illustrated code LOGLBL in FIG. 5 is set. As described above, the line connector may be considered to be a minute black circle indicating whether or not the connection line intersections on the logic circuit diagram are electrically connected. In detecting the presence or absence of the black circle, it goes without saying that the existence of the connecting line is correctly discovered, and then the pattern of the image data is examined at the position corresponding to the intersection. The processing mode will be described below. A partial image of the image data stored in the image memory is cut out based on the grid coordinates. That is, as shown in FIG. 53A, the vertical lattice axis X ₀ ,
A partial image is cut out based on the grid coordinates (X ₀ , Y ₀ ) of the horizontal grid axis Y ₀ . In this state, as shown in FIG. 53B and C, two types of horizontal windows HW1,
Two types of vertical windows are set: HW2 (each size is 1 x m pixels) and vertical direction VW1 and VW2 (top and bottom) (each size is m x 1 pixel), and as shown in Fig. 53. As shown, the horizontal window is slid from top to bottom in the preset slide range WH, and the vertical window is slid from left to right in the slide range WV. In the process of sliding these windows, the total number of "1"s (black dots) within the window is determined for each unit distance, for example, one pixel movement, and it is checked whether the total number exceeds a preset threshold. If it is exceeded, that position is regarded as a line part, and the detection is continued until the end of the slide range to detect the presence or absence of a line in each of the up, down, left and right directions, and its position. The line detected in this way is a line that exists in the middle of the sliding range of the window, that is, a line that is sandwiched between non-line parts. Figure 54 shows the upper window VW1
An example of line detection is shown below. Note that DTL indicates the detected line position. As described above, by setting the threshold value, it is possible to detect lines that are broken, and also to relatively accurately detect the position of distorted lines. Note that the threshold value is set to a value slightly smaller than m. Based on the presence or absence of a line detected in this manner and its position, line position correction processing is performed. The correction process is performed according to the logic shown in Table 1.

[Table] In other words, there is no upward (or leftward) line as in the case, and there is no downward (or rightward) line.
If there is no line heading toward , it is assumed that there is no line in the vertical direction (or horizontal direction).
Also, in cases where there is no upward (or leftward) line and there is a downward (or rightward) line, there is a downward (or rightward) line. Assume that there is an upward (or leftward) line at the same position. Furthermore, in the case, it is assumed that a vertical (or horizontal) line exists at the detected position. The reason for performing this kind of correction is to temporarily correct for lines in all four directions not being detected in cases such as T-shaped intersections or poor input image quality. . In this correction process, in the case shown in Table 1, there are no lines in the vertical or horizontal direction, so there is no need to cut out the area near the intersection, perform matching calculations, and make judgments, which will be described later. It can be determined that it does not exist. Therefore, each process described later is omitted. In the case shown in the table above, lines exist or are assumed in the up, down, left, and right directions, so based on the output value of this correction process, the area near the intersection, which is the shape feature of the line connector, is extracted from the partial image. break the ice. The cutout area is as shown in FIG.
There are four rectangular areas C1 to C4 of size n×n, which are sandwiched by lines in four directions that are set based on the output value of the correction process. This cutting process is performed by cutting out a ⁴ⁿ² bit pattern for the area near the intersection. In FIG. 55, LU is an upward line, LL is a leftward line, LD is a downward line, and LR is a rightward line. The area bit pattern thus cut out is subjected to the following matching operation with, for example, a dictionary bit pattern read from the dictionary memory. T= _k 〓 ^j=1 _4o ^{2 i=1} (Ci+Dij) However, in the above formula, Ci is the i-th bit of the extracted area bit pattern, Dij is the i-th bit of the j-th dictionary bit pattern, and k represents the number of patterns registered in the dictionary memory, and 4n ² represents the size of each pattern described above. If the above-described matching calculation result T is less than or equal to the threshold value, it is determined that no line connector exists at that intersection, and if it is greater than or equal to the threshold value, it is determined that a line connector exists at that intersection. [] Processing for extracting small circular patterns in the circle/triangle extraction processing section. The small circular pattern in the logic circuit diagram is the 56th
Those that mean reversal as in Figures A and B, and the 56th
There are some words that mean a combination as shown in Figure C. 56th
In the case of diagram A, if there is no circular pattern figure M, it is an AND gate, and if there is, it is a NAND gate, so the figure M
It is important to check that it is a circle and the surrounding figure N to which it connects. In the case of the surrounding figure N of the circular figure M, that is, the AND symbol in FIG. He is trying to understand the meaning of the circular pattern figure M. The position of the small circular pattern drawn on the drawing is more misaligned than other line figures. To deal with this, it is necessary to flexibly respond to positional shifts so that the presence of the object is recognized no matter where it is drawn. A circular pattern of 2 mmφ that often appears in logic circuit diagrams will be described below as an example. 1
When the resolution is 8 lines per mmφ, the field of view is 25
If a rectangular area of ×25 pixels is used, there is a margin of 4 pixels on each side for a circular pattern of 2 mmφ, so that a positional deviation of up to 0.5 mm will fall within the rectangular area of the visual field. FIG. 57 shows the relative relationship between the rectangular area 4 and the circular pattern 5 in this visual field.
FIG. 57 shows a case where the circular pattern 5 is located in the center of the area 4. Next, features are extracted to determine whether or not a circular pattern 5 exists in this area 4, but the manner of extracting features of this circular pattern is well known and will not be described here. FIG. 58 shows the manner in which the image data is scanned by the area 4 and the candidate points 5' of the circular pattern 5. In FIG. 58, G5 indicates each grid point, and the grid points exist with a distance interval of 2 mm, and a rectangular area 4 of 25×25 pixels is scanned along these grid points. Since the allowable displacement of the circular pattern 5 within one region 4 is 0.5 mm, the region 4 is scanned at a pitch of 1 mm. By doing so, extraction is possible no matter where the circular pattern 5 is drawn. Further, as candidate points 5' for the existing position of the circular pattern 5, points 6a and 6 in FIG.
#17 of the aggregate grid point label code LOGLBL which is determined as b, 6c, 6d and its grid point position
Set the bit to "1". Due to its nature, the 2mmφ circular pattern has meaning attached to other symbols. Therefore, the position of the circular pattern is determined by estimating the position where the circular pattern should be based on the recognition results of other symbols, and if that position is a candidate point, it is determined as a circular pattern. [] Processing of the outward facing arm removal unit. The aggregated grid point label code LOGLBL extracted as described above generally contains undesired noise. In this process, for example, as shown in FIG. 59, the arms 7 (the above-mentioned LU, LL, LD,
If a line segment such as LR exists, this arm 7 is considered to be undesired noise and is deleted. Then, any ambiguous direction code or gap direction code that may exist related to that arm is deleted. The process for this is to compare the aggregate grid point label code LOGLBL for each grid point with the coordinates of the grid point, and if the grid point is (1) j=NY (lower side), # Set the 28 bit (D), #24 bit (F _{D )} , and #12 bit (G _D ) to "0." (2) If j = 1 (left side), set the #29 bit (L), #25 bit ( F _L ), #13 bit (G _L ) are set to 0. (3) If j = 1 (upper side), #30 bit (U), #26 bit (F _{U )} , #14 bit (G _U ) is set to "0". (4) If j = NX (right side), set #31 bit (R), #27 bit (F _R ), #15 bit (GR) to "0". However, NX, NY is the number of lattice axes in the X-axis and Y-axis directions, respectively, in Figure 1. [XI] Processing of a pair of processing units. In this process, for example,
As shown in C and D, the existence of arms 7 is checked for two opposing grid points, and unpaired arms 7 are removed. In this processing, after removing unpaired arms, predetermined supplementary processing is performed as follows. That is, (1) Removal of unpaired arms a LOGLBL(j, j) and LOGLBL(i+1,
When paying attention to j) #31 bit (R) of LOGLBL (i, j) is “1” and #29 of LOGLBL (i+1, j)
If bit (L) is “0” -→LOGLBL
Set #31 bit (R), #27 bit (F _R ), and #15 bit (G _R ) of (i, j) to "0". ●#31 bit (R) of LOGLBL (i, j) is “0” and #29 of LOGLBL (i+1, j)
If the bit (L) is "1" - → LOGLBL
Set #29 bit (L), #25 bit (F _L ), and #13 bit (G _L ) of (i+1, j) to "0." b LOGLBL (i, j) and LOGLBL (i, j+
When paying attention to 1) #28 bit (D) of LOGLBL (i, j) is “1” and #30 of LOGLBL (i, J+1)
If bit (U) is “0” - → LOGLBL
Set #28 bit (D), #24 bit (F _D ), and #12 bit (G _D ) of (i, j) to "0". ●#28 bit (D) of LOGLBL (i, j) is “0” and #30 of LOGLBL (i, j+1)
If bit (U) is “1” -→LOGLBL
Set #30 bit (U), #26 bit (F _U ), and #14 bit (G _U ) of (i, j+1) to “0”. (2) After removing the arm, each LOGLBL (i, j) For, if all #28 to #31 bits (D, L, U, R) of a LOGLBL (i, j) are “0”, then
-→ #11 to #15 bits of LOGLBL (i, j) (G _F , G _D , G _L , G _U , G _R ), #19 to #27
Bits (Z _D , Z _L , Z _U , Z _R , Z _F , F _D , F _L , F _U ,
Set F _R to "0". b If #12 to #15 bits (G _D , G _L , G _U G _R ) of LOGLBL (i, j) are all “0”, then
-→ Set #11 bit (G _F ) of LOGLBL (i, j) to “0”. Note that processing (2) corresponds to the removal of the arm,
It supports the process of erasing ambiguous codes. [XII] Line breakage correction unit processing. In this process, for example, as shown in FIGS. 61A and 61B, the existence of the arm 7 is checked for four corresponding grid points, and the arm that should be there is added as a missing arm to correct line breakage. In FIG. 61, 8 represents a don't care arm in which arm 7 may or may not exist, and 9 represents an arm added through the process. That is, (1) LOGLBL(i-1,j) and LOGLBL(i,
j) and LOGLBL(i+1,j) and LOGLBL(i
+2, j); R of LOGLBL (i-1, j) L of LOGLBL (i, j) R of LOGLBL (i+1, j) L of LOGLBL (i+2, j) are all “1” and R, U, D of LOGLBL (i, j) R, U, D of LOGLBL (i, j) If L, U, D of LOGLBL (i+1, j) are all “0”, then LOGLBL (i, j) “R=1, F _R =1, F _F =
1, G _R = 1, G _F = 1” LOGLBL (i+1, j) “L = 1, F _L = 1, F _F
= 1, G _L = 1, G _F = 1''. That is, arm 9 is attached. (2) LOGLBL(i, j−1) and LOGLBL(i,
j) and LOGLBL (i, j+1) and LOGLBL
When paying attention to (i, j+2); D of LOGLBL (i, j-1) U of LOGLBL (i, j) D of LOGLBL (i, j+1) All U of LOGLBL (i, j+2) are “1”. And if R, L, and D of LOGLBL (i, j) are all "0", then "D = 1, F _D = 1, F of LOGLBL (i, j)" _F =
1, G _D = 1, G _F = 1” LOGLBL (i, j+1) “U = 1, F _U = 1, F _F
= 1, G _U = 1, G _F = 1. That is, attach arm 9. [] Processing of misalignment correction unit. In this process, generally a certain grid point (i,
If there is a shift in the line segment corresponding to j), even at the grid point (io, jo) in the direction of the shift,
Focusing on the points where a corresponding shift may appear, the grid point label/code in the direction of the shift is determined.
If there is no deviation in LOGLBL, the deviation flag existing at the certain grid point (i, j) is dropped. The process is as follows. (1) The deviation flag Z _F (#23 bit) is “1”
Detect LOGLBL(i,j). (2) When the LOGLBL(i,j) is detected, check the deviation direction code of the LOGLBL(i,j). Then, if a #22 bit “Z _R = 1”, LOGLBL(i
+1, j) b If #21 bit “Z _u = 1” then LOGLBL
(i, j−1) c If #20 bit “Z _L = 1”, LOGLBL(i
-1, j) d #19 bit “Z _D = 1” then LOGLBL
Pay attention to (i, J+1). (3) All LOGLBL (io, jo) of the target of interest have the following conditions: e all #28 to #31 bits are "0", f any of the 28 to #31 bits is "1", and the ambiguity flag is set. Find a case where F _F (#16 bit) is "0" and deviation flag Z _F (#23 bit) is "0". (4) And if the case is satisfied, the above
Set #19 bit to #23 bit of LOGLBL (i, j) to "0". That is, the deviation direction code and deviation flag are dropped. [] Processing of ambiguity correction unit. In this process, a certain code LOGLBL
(i, j), the codes LOGLBL(i+1,j), LOGLBL(i,
j-1), LOGLBL (i-1, j), LOGLBL
Examine (i, j+1) and correct ambiguous information.
That is, (1) LOGLBL(i,j) whose fuzzy flag F _F (#16 bit) is "1" is detected. (2) Initial settings; CNT=0, (ARM(io)=0, io
= 1, 4) (3) 4-way code of LOGLBL (i, j) (D・
LOGLBL(io,
jo) That is, a If "R=1", LOGLBL(i+1,
j) b If “U=1” then LOGLBL(i,j−
1) c If "L=1", LOGLBL(i-1,
j) d If “D=1”, LOGLBL(i, j+
1) Check. Let CFLG be the number of grid points to be examined. For example, "R=1, U=1, L=1, D=1" →
(CFLG=4” “R=1, U=0, L=0, D=0” →
"CFLG=1" (4) Arm in the corresponding direction of the target grid point label; e For LOGLBL (i+1, j), L
(#29 bit) is ARM(1), and f LOGLBL(i, j-1) is D
(#28 bit) is ARM(2), and gLOGLBL(i-1,j) is R
(#31 bit) is ARM(3), h LOGLBL (i, j+1) is U
(#30 bit) is ARM(4), and these ARM(1) to ARM(4) are logic "1", shift flag #23 bit "Z _F = 0", and ambiguity flag #16 bit "F If _F = 0, then add 1 to the above CNT and set ARM(io) to 1. (5) Judgment; i When CFLG≦1, no processing. j When CFLG=CNT (CFLG≧2), #16 bit (F _F ), #24 to #27 bit (F _D , F _L , F _U , F _R ) #11 of LOGLBL (i, j) Set the bit ( _GF ) and #12 to #15 bits ( _GD , _GL , _GU , _GR ) to "0". k CFLG≠CNT, and (i) LOBLBL(i-1,j) and LOGLBL(i
+1, j) satisfies the condition (4) above, the #16 bit (F _F , #24 to #27 bit (F _D , F _L , F _U , F _R ) of LOGLBL (i, j) # Set the 15 bit (G _R and #13 bit (G _L ) to 0. Also, if ARM(2) = 1, set the #14 bit (G _U ), and if ARM(4) = 1, set the #12 bit (G Set _D to "0".Furthermore, if all 12 to 15 bits (G _D , _GL , G _U , G _R ) are "0", set #11 bit ( _GF ) to "0". ( ii) LOGLBL(i,j-1) and
When LOGLBL (i, j+1) satisfies the condition (4) above, #16 bit (F _F ), #24 to #27 bit (F _D , F _L , F _U , F _R ) #14 bit (G Set _U , #12 bit (G _D ) to "0". Also, if ARM(1) = 1, set #15 bit (G _R ), and if ARM(3) = 1, set #13 bit (G _L ) to "0". In addition, #12 to 15 bits (G _D , G _L , G _U , G _R )
If all are “0”, #11 bit (G _F )
Set to "0". [] Processing of the symbol classification processing unit. 4-way code (D, L, U, R) in the grid point label code LOGLBL generated as above
Perform symbol group extraction processing based on . In recognizing a logic circuit diagram, it is necessary to identify similar symbols as shown in FIGS. 62A to 62C. Although there are slight differences between these symbols, the input drawing that is the target of this invention is a handwritten drawing with a mixture of characters, so if we take into account the variations due to handwriting and the influence of characters, these differences at the time of current processing. It is dangerous to determine individual symbols based on slight differences. Therefore, in this process, individual symbols are not directly extracted, but a major classification corresponding to a two-step process of major classification and minor classification is extracted. Regarding the symbols to be extracted, similar symbols as shown in FIGS. 62A to 62C are grouped in advance, and extraction is performed for each symbol group. The processing corresponding to the small classification will be explained in detail in the single gate symbol recognition processing section. Figures 63 (A) to (E) are graphic representations of how the four-way code (DLUR) appears at each grid point when the symbol group shown in Figure 62A is drawn by hand. For example, " ｜・−” is “1011”
, "・" means "0000". Also MX
and MY indicate the size of the area considered to be influenced by the shape of the symbol. Figure 63A
The reason why there are several different patterns such as E to E is because the symbol contains a curved line, and the way the four-way code appears at the grid points around the curved line is due to slight variations due to handwriting etc. This is because they are different. This also applies to symbols including diagonal lines as shown in FIG. 62B. In order to deal with such deformed patterns, basically all of these deformed patterns can be stored as dictionary patterns in, for example, a dictionary memory.
In this case, the number of dictionary patterns becomes enormous. Therefore, in the present invention, a dictionary pattern based on the method described below is used. First, Figure 63 A to E
If we focus on one coordinate (I, B) in each deformed pattern, we can see that for all of these patterns, there is a line segment to the left of the grid point, and a line segment to the top. Doesn't exist. Line segments exist in at least one direction below and to the right of the lattice points for one pattern. Also, if we pay attention to the coordinates (,B) of each deformation pattern in the same figure, we can see that there are no line segments at all in the downward and left directions, but there are line segments in the upward and right directions. Sometimes it exists and sometimes it doesn't exist. Therefore, in the present invention, by utilizing these conditions, for extraction of the symbol group in FIG. 62A,
A dictionary pattern as shown in FIG. 64 is used. In the figure, small circles represent grid points, and thick lines indicate that a pattern should exist in the up, down, left, and right directions at each grid point, and no lines indicate that no pattern should exist. A double line indicates that the existence of a pattern is not a concern (don't care), and a thin line indicates that two or more directions are necessarily specified, and it is sufficient that the pattern exists in at least one of these directions. Furthermore, MX and MY indicate the size of the dictionary pattern. By using a dictionary pattern of this type, the 63rd
Even for several types of modified patterns shown in FIGS. A to E, the symbol group shown in FIG. 62A can be extracted using only one type of dictionary pattern shown in FIG. 64. The coordinates of the dictionary pattern shown in FIG.
The reason why the right side of C) and (.C) is a double line is to absorb the negative influence of the reverse logic symbol (small circular pattern) written to the symbol output terminal. FIG. 65A shows the four-way _code part that is _the target _of matching with the dictionary pattern extracted from the intensive grid point label code LOGLBL as shown in FIG _. ] is equivalent. Further, FIG. 65B shows the code format per lattice point of the dictionary pattern used in the present invention. Bits #0 to #3 of the 9-bit division of this dictionary code DC are pattern codes (P _k ),
After considering the influence of handwriting variations when handwriting a symbol, draw it in four directions from the grid point [DLUR]
The presence or absence of a line segment is expressed as [P ₁ P ₂ P ₃ P ₄ ], and #4 to #7 bits are mode codes (M _k ), and the above four-way code and the above pattern This defines the mode for matching with the code, and [M ₁ M ₂ M ₃ M ₄ ] corresponds to [P ₁ P ₂ P ₃ P ₄ ]. This mode code determines whether (1) when "M _k = 0", P _k and T _k match or not (2) when " M _k = 1" and "P _k = 0", T _k is " It can be 0 or 1 (don't care) (3) When ``M <sub>k</sub> = 1'' and ``P _k = 1'', it is always 2.
Although more than one direction is specified, it has the meaning of whether or not at least one of the directions is "T _k =1". Further, a symbol area flag (S) indicating whether or not the lattice point itself becomes a matching target is provided at the #9th bit. FIG. 66 shows, as an example, a dictionary code corresponding to the graphic dictionary pattern of FIG. 64.
Conversion between this graphical dictionary pattern and dictionary code will be facilitated by Table 2.

[Table] Dictionary patterns using the above method are created for all symbol groups to be extracted and stored in the dictionary memory in descending order of dictionary patterns. Then, symbols are extracted from the input drawing by matching with the four-way code of each grid point obtained from the input image data. That is, in FIG. 67, the dictionary pattern of each symbol group stored in the dictionary memory and the four-way code of grids equal to the number of grids of this dictionary pattern are sequentially read out, and the dictionary eudo groups constituting these dictionary patterns are read out. Matching is performed between the DCC and the four-way code group TCC in correspondence with grid points. The matching operation for performing this matching is performed according to the following equation. That is, if the overall evaluation value of a certain symbol group is E _g , then E _g = _MX 〓 ^x=1 _MY 〓 ^y=1 W _xy --(5) Here, the evaluation value per lattice point W _xy is W _xy = S× [ ₄ 〓 ^k=1 {M _k ∧ (P _k T _k )} + F――(6) where F=(P ₁ ∧M ₁ ∨P ₂ ∧M ₂ ∨P ₃ ∧M ₃ ∨P ₄ ∧M ₄ )∧／P ₁
∧M ₁ ∧T ₁ ∨P ₂ ∧M ₂ ∧T ₂ ∨P ₃ ∧M ₃ ∧T ₃ ∨P ₄ ∧M ₄ ∧T ₄ --(7
) This evaluation value W _xy per grid point takes a value from "0" to "4". That is, if the dictionary code and the four-way code match perfectly, the minimum value is "0", and if they do not match at all, the maximum value is "4". The overall evaluation value E _g is expressed as the sum of the evaluation values of all grid points within the dictionary pattern area (represented by MX and MY). If this overall evaluation value E becomes "0", it means that the dictionary code and the 4-way code perfectly match at all grid points in the dictionary pattern, and the 4-way code group TCC is equal to the dictionary code group DCC. It is determined that the symbol belongs to the symbol group. However, as seen to the left of the coordinates (,A) in Figure 68B and above the coordinates (,A) in Figure 68B, the dictionary pattern is size (MX,
The optimal threshold value T _g is set for the overall evaluation value E _g for each dictionary pattern according to the degree of deformation caused by handwriting, etc., and the relationship E _g ≦T _g --(8) is established. If it is true, it is determined to be a symbol. In this way, matching is performed with all dictionary patterns in the dictionary memory at a certain grid point of the input drawing, and one actual symbol is determined from among those determined to be symbols. This satisfies equation (8)
E Adopt the smallest of _g . Also, if there are multiple minimum E _gs , the one with the largest dictionary pattern is adopted. As the above symbol extraction results, the input drawing coordinates corresponding to the dictionary pattern coordinates (,A),
The name of a predetermined symbol group and information as to whether it completely matches the dictionary pattern, that is, whether "E _g =0" is established, are stored in the symbol recognition table. The above matching process is performed while shifting the grid point positions of the input drawing one grid at a time. [] Multiple gate/symbol extraction processing in the complex gate/symbol recognition processing unit. As mentioned above, in the logic circuit diagram to be processed by the present invention, the symbols as shown in FIG. 62 and the composite gate symbol C-G as shown in FIG.
exists. In order to process these symbols correctly, the following table is prepared. That is, in response to the extraction of a single gate symbol as shown in FIG. 62, a single gate symbol recognition table SPTABLE as shown in FIG. 69A is prepared. The table SPTABLE is
It has the following columns. That is, (1) i, j... Enter the coordinate values of representative grid points for a single gate symbol. Figure 69B
The coordinate values (i, j) of the grid points as shown in the figure are entered. (2) NO. The name of the extracted single gate symbol is given by number. For example, the number "27" is given to the OR circuit, the number "7" is given to the NAND circuit, and so on. (3) SDRCT...Gives the output direction of the extracted single gate symbol. For example, the symbols shown in FIG. 69B are given numerical values "0" to "3" as shown. (4) SNO....If it is finally extracted as one composite gate symbol, the number that should be the single gate symbol that makes up the composite gate symbol is Given. For example, the above NO. was extracted as an AND circuit, but if the single gate symbol constituting one composite gate symbol was originally an OR circuit, then SNO. is the number corresponding to the OR circuit. and input it to the data processing device. However, the SNO. is given by extracting the composite gate symbol, and is initially set to the value "0". (5) CNO.....The single gate symbol is the core of the composite gate symbol (see Figure 70A, which will be described later).
The name of the composite gate symbol is given in the form of a number.
Initially, the value is set to "0". (6) STFLG...Logical "1" is set when one composite gate symbol is extracted and processed, and the value is "0" initially.
It is said that In addition, single gate symbol recognition table
The role of SPTABLE will be described later with reference to FIG. 71. The table SPTABLE is prepared as described above, and a composite gate/symbol dictionary memory MPDIC as shown in FIG. 70 is also prepared. The contents of FIG. 70A show the contents of the dictionary memory corresponding to one composite gate symbol CG shown in FIG. 70B. It also has the following columns: (7) i, j...The coordinate values of the core single gate symbol (K1 shown in Figure 70B) are (0,0)
Then, the single gate symbols K1, K2, K3, . . . constitute the composite gate symbol.
The coordinate values of ... are given as relative values. For example, for a single gate symbol K2 (-7,
−11). (8) SDRCT...each single gate symbol K1,
Information similar to that in FIG. 69A for K2, . . . is given. (9) NO. The name of each single gate symbol K1, K2,... making up the composite gate symbol is given by number. 69th
Same as in the case of Figure A (10) SNO. . . . The original number for each single gate symbol K1, K2, . . . composing the composite gate symbol is given. This role will be described later with reference to FIGS. 74 and 75. (11) SCNT: The number of single gate symbols K1, K2, etc. that make up the composite gate symbol is given. (12) CNO: The name of the composite gate symbol is given by number. For the composite gate symbol shown in Figure 70B, "CNO.=121"
It is said that The manner in which one composite gate symbol is extracted in a state where the single gate symbol recognition table SPTABLE and the composite gate symbol dictionary memory MPDIC are prepared as described above will be explained with reference to FIG. 71. . Assume that a single gate symbol recognition table SPTABLE as shown in FIG. 71A exists, and that the contents of the dictionary memory MPDIC corresponding to one composite gate symbol are as shown in FIG. 71B. . It is assumed that the extracted single gate symbols are stored in the single gate symbol recognition table SPTABLE, for example, in the order of their coordinate values. In addition, in the composite gate symbol dictionary memory MPDIC, a group of information corresponding to each composite gate symbol (as shown in FIG. 71B) is sorted in descending order of the number of the core unit gate symbol. If the numbers are the same, they are sorted in descending order of CNO. mentioned above. Plus single gate symbol recognition table
SPNT point indicating the beginning of SPTABLE
and the point that indicates the first piece of information in the composite gate/symbol dictionary memory is
Let it be FPNT. The processing is performed as follows. That is, (13) NO. and
SDRCT and NO. about the first single gate symbol (which is the core) in the first batch of information (as shown in Figure 71B) of the dictionary memory MPDIC.
Compare with SDRCT. (14) If there is a mismatch, the next batch of information (information at the position of FPNT+1) in the dictionary memory MPDIC is compared in the same way. The same applies below. (15) If all the dictionary memories MPDIC are searched and there is no match, the next single gate symbol in the table SPTABLE (the single gate symbol at the position of SPNT+1) is compared in the same way. (16) Suppose that the single gate #12 shown in Figure 71A
The NO. and SDRCT of the symbol are the same as the NOS. of the first single gate symbol shown in Figure 71B.
Suppose that it matches SDRCT. In this case #12
The single gate symbol located within a predetermined coordinate range from the coordinates (i ₁₂ , j ₁₂ ) of the single gate symbol in is examined and STFLG is set to logic “1”.
Make it. For anything out of range, set STFLG to logic '0'. (17) Then, compare this number CNT of "STFLG=1" with the SCNT shown in FIG. 71B. At this time, if "CNT<SCNT", it is determined that the single gate symbol #12 is not the nucleus of the composite gate symbol corresponding to the illustration in FIG. 71B, and the search proceeds to the next step. (18) If “CNT≧SCNT”, the buffer shown in Figure 71E
Clear the BUF, set i=i ₁₂ and j=j ₁₂ in the coordinate column of the #1 line of the dictionary buffer MPDIC/BUF shown in Figure 71C, and set i=i ₁₂ - in the coordinate column of the #2 line. 7. Set j=j ₁₂ -2, and set i=i ₁₂ -14, j=j ₁₂ -4 in the coordinate column of line #3. Also, the buffer shown in Figure 71E
Store in BUF in association with the fact that it is "#12" in table SPTABLE. (19) Next, it is checked whether a desired single gate symbol exists at the position corresponding to the coordinate value (i ₁₂ -7, j ₁₂ -2) shown in the #2 line of the dictionary buffer MPDIC.BUF. Table SPTABLE
If a corresponding item, such as #10, is found among the items whose STFLG is logical "1" above, the coordinate value (i ₁₂ −
7, j ₁₂ -2) is rewritten to (i ₁₀ , j ₁₀ ), and "#10" is written in the buffer BUF shown in FIG. 71E. In this case, even if the coordinate values (i ₁₂ −7) and i ₁₀ or the coordinate values (j ₁₂ −2) and j ₁₀ do not match completely, in order to allow for slight deviations, for example, the difference is expressed as an absolute value. If it is "2" or less, it is considered to be applicable. Therefore, there may be cases where more than one item is applicable. (20) Similarly, it is assumed that the single gate symbol #14 in the table SPTABLE is extracted and "#14" is written in the buffer BUF shown in FIG. 71E. (21) In this state, if the number written in the buffer BUF matches the above-mentioned SCNT, it is assumed that one composite gate symbol corresponding to the information shown in FIG. 71B has been extracted, and SNO and CNO are written in the table shown in Figure 71A and in SPTABLE as shown by the circles in the diagram. Then, proceed to the next search. The operation during this time is shown in more detail in the form of a flowchart as shown in FIGS. 72 and 73. The flowchart shown in FIG. 73 shows an embodiment of the process for extracting candidates for the core of the composite gate symbol shown in FIG. 72. As described above, the composite gate symbol is extracted and then input to the data processing device. In other words, in the example of Fig. 71, the i, j, SDRCT, and SNO columns shown in Fig. 71D, and the SCNT and
The CNO and the contents of the buffer BUF shown in FIG. 71E are output as information input to the data processing device. Utilizing this fact, it becomes possible to correct erroneous extraction during single gate symbol extraction and input it to the data processing device. That is, composite gate
When extracting symbols, in the single gate symbol extraction process described above, for some reason, as shown by arrow L in FIG. Suppose that it can be extracted as an AND circuit. In such a case, assuming that it is impossible for the part indicated by the arrow L to become an AND circuit, a dictionary as shown in FIG. 74B is prepared as a composite gate/symbol dictionary memory. Then, the single gate symbol at the arrow L is referred to as an AND circuit, and CNO=102 is given as the overall pattern. In this way, Figure 74A
With the pattern shown, it is recognized as a composite gate symbol with CNO=102, and when inputting it to the data processing device, the single gate symbol at the position of arrow L is connected to the OR circuit (SNO=102).
27) can be corrected and reported. FIG. 75 deals with the case where a single gate symbol at the position of arrow M, as shown in FIG. 75A, which should originally be a composite gate symbol, is likely to be extracted as a multi-input AND circuit like a single gate symbol. The figure shows how to do this. [] Starting point setting process in the complex gate/symbol recognition processing section. When extracting gate symbols in general, not just compound gate symbols related to the process, the start point (terminal position) of the gate symbol should be set correctly and used for the connection line extraction process described later. be made to do. For this purpose, the start point setting process is performed as follows. That is, when, for example, one compound gate symbol is extracted as described above, the position of the start point (connection point with the connection line) in the symbol can be determined from the matched contents of the dictionary memory. It is determined in the form of relative coordinates from the coordinates (i, j). In the present invention, based on this point, the absolute coordinates where the start point should be located are calculated, and the #0 bit on the grid point label code LOGLBL is set to logic "1" for the grid point corresponding to the absolute coordinates. At the same time, logic "1" is set in any of bits #2 to #5, corresponding to which direction the line segment extends from the starting point. Further, if an inverse logic symbol should be added to the lattice point, the #1 bit is set to logic "1". [] Processing in the symbol area setting processing section. As mentioned above, when symbols belonging to each group of single gate symbols or composite gate symbols are extracted at the major classification level, for the grid points at the boundaries of the area occupied by each symbol,
Set symbol area flag. That is, bit #8 (symbol area flag S) in the code shown in FIG. 5 is set to logic "1". In setting the symbol area flag S, the relative coordinates of the grid point where the symbol area flag S is logical "1" as shown in FIG. 66 are determined from the contents of the dictionary memory that are matched with the symbol. Therefore, calculate the absolute coordinates, and set bit #8 on the grid point label code LOGLBL to logic "1" for the grid point with the absolute coordinates.
Just do it. In this way, when attempting to set the #8 bit on the lattice point label code LOGLBL to logic "1" corresponding to the extracted symbol, logic "1" may already be set. In such a case, as described with reference to FIG. 7, there is a possibility that symbols are extracted twice, and a flag indicating this is set to SPTABLE as shown in FIG. 69A.
Set it in the STFLG field. FIG. 76B corresponds to the logic circuit diagram shown in FIG. 76A,
The bold line indicates how the symbol area flag S (#8 bit) is set. [] Line segment confirmation processing in the line segment confirmation processing section. As shown in FIG. 4, this processing consists of processing by a shift correction unit and processing by an ambiguity correction unit. When processing handwritten drawings, it is necessary to fully consider the positional deviation of line segments. Due to this positional shift, what is originally a single line segment may be extracted twice as a lattice point label code on two parallel lattice axes. The processing by the deviation correction unit estimates the state of the positional deviation of such line segments from the lattice point label code, and generates reliable lattice point label codes only on the lattice axes considered to be intended by the designer. Here, the reliable grid point label code is the gap direction code (#12 to #15 bit),
The gap direction code (bits #19 to #22) and ambiguous direction code (bits #24 to #27) are all 0, and the ambiguous grid point label code is the gap direction code,
Refers to a case where either bit of the misalignment direction code or the ambiguous direction code is "1". Fig. 77 is an example of this processing, in which a pair of adjacent grid point labels/codes with "shift directions" in opposite directions as shown in Fig. 77B is captured, and this is regarded as a result of a shift of a single line segment. The correction is made as shown in FIG. 77C. That is, the code shown in FIG. 77B is sequentially searched based on the four-way code to detect the axis on which the lattice to which the reliable lattice point label code is attached is present. Finally, raise that axis to a reliable grid point label code, and remove the other grid point label code. In the figure, 7-1
is an arm corresponding to a certain label code, 7-2 is an arm with a deviation flag, 10 is a deviation direction, and 11 is a line segment. Next, the processing by the ambiguity correction unit captures the ambiguity of the grid point label code from a broader perspective and improves it into a reliable grid point label code. Removes ambiguities caused by characters drawn close to. An ambiguous lattice point label code having a gap direction code or an ambiguous direction code of "1" is assigned to a lattice point having an incomplete form as a line segment. Naturally, the same ambiguous grid point label code is assigned to the grid point where the character is located, but here it is difficult to determine whether the ambiguity of this code information is due to local variations in the line segment or to the character itself. We provide an interpretation of the cause and make corrections based on that interpretation. FIG. 78 shows an example of this process. Specifically, first, an ambiguous grid point label code as shown in FIG. 78B is detected, and adjacent grid point labels located in the direction along the four-way code are Search code sequentially. In the process of this search, if a certain grid point label code appears between ambiguous grid point label codes as shown in Figure 78C, the ambiguity is interpreted to be due to local variations in line segments. , into a reliable grid point label code. In the figure, white circles 12 are reliable grid point labels.
The code, black circle 13 represents an ambiguous grid point label code, 14 represents an arm with an ambiguous flag, and 15 represents an arm in which arm 7-2 with the above-mentioned deviation flag and arm 14 with the above-mentioned ambiguity flag overlap. There is. Further, 16 represents a character, and 17 represents a line segment. [] Processing in the gap/ambiguous arm processing section. Since the connection line is substantially determined up to the above processing, at that point, the four-way code (D, L , U, R). #8 of grid point label code LOGLBL(i,j)
The following processing is performed for bits (S) of "0". (1) If #11 bit (G _F ) of LOGLBL (i, j) is "1" and (1-1) #15 bit (G _R ) of LOGLBL (i, j) is "1", then ,LOGLBL(i,j)
Set the #15 bit (G _R ) and #31 bit (R) to "0". (1-2) If #14 bit (G _U ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set #14 bit (G _U ) and #30 bit (U) to "0". (1-3) If #13 bit (G _L ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set #13 bit (G _L ) and #29 bit (L) to “0”
Make it. (1-4) If #12 bit (G _D ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set #12 bit (G _D ) and #28 bit (D) of
Make it. (1-5) Then, set #11 bit (G _F ) of LOGLBL (i, j) to "0". (2) If #16 bit (F _F ) of LOGLBL (i, j) is "1" and (2-1) #27 bit (F _R ) of LOGLBL (i, j) is "1", then ,LOGLBL(i,j)
Set the #27 bit (F _R ) and #31 bit (R) to "0". (2-2) If #26 bit (F _U ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set the #26 bit (F _U ) and #30 bit (U) to "0". (2-3) If #25 bit (F _L ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set #25 bit (F _L ) and #29 bit () to "0". (2-4) If #24 bit (F _D ) of LOGLBL (i, j) is “1”, then LOGLBL (i, j)
Set #24 bit (F _D ) and #28 bit (D) of
Make it. (3) For those processed in steps (1) and (2) above,
Paired processing is performed as performed by the paired processing units described above. [XI] Symbol recognition processing in the single gate symbol recognition processing unit. In this process, based on the results of the general classification performed by the symbol classification processing section mentioned above,
The same group can be further subdivided. For the symbols extracted as above,
A table SPTABLE as shown in FIG. 69A is obtained. Under this state, the following processing is performed. (1) Search table SPTABLE. For example, for a single gate symbol 18 as shown in FIG. 79A, search the table shown in FIG.
Take out the direction SDRCT. Here, “(i _S , j _S ), NO
=13, SDRCT=0" is extracted. (2) Search candidate symbol table. As shown in FIG. 79B, as shown in FIG. 69A,
A candidate symbol table 19 is provided that describes candidate symbol numbers and candidate number information corresponding to each NO. 13'' and the direction is ``SDRCT=0'', three candidate symbol numbers ` `13 '', `` 14 '', and `` 15 '' are extracted from the candidate symbol table 19. (3) Symbol recognition dictionary and conversion. FIG. 79 C, D, and E show the contents of symbol recognition dictionaries 20-1, 20-2, and 20-3 corresponding to candidate symbol numbers " 13 ,"" 14 ," and " 15 " extracted from FIG. show. The shape of the grid point label code (i, j) corresponding to each starting point position of each left gate is shown. Also, the * mark on the outside of the margin is information indicating that the state should not apply to the starting point. The left side of the bottom column shows the size of the dictionary, and the right side shows the number of inverse logic symbols (2 mmφ). These recognition dictionaries are converted using directional SDRCT. (4) Matching between symbol recognition dictionary and grid point label code. As shown in FIG. 79F, the symbol recognition dictionary 20
-1, 20-2, 20-3 and the small circular display flag (#17 bit) of the grid point label code and the 4-way code (#28 to #31 bit) are performed, and the results are shown in G of the same figure. It is stored in the recognition buffer 21. The column A of the recognition buffer 21 shows the degree of coincidence of four-way codes, the column B shows the degree of coincidence of reverse logic symbols, and the column C shows the degree of coincidence of reverse logic symbols described in the dictionary.
Indicates the degree of coincidence of symbol locations. (5) Judgment. (5-1) A+B is the maximum value, that is, A+B
If the value of is twice the size of the symbol recognition dictionary (the number of vertical columns shown), that candidate symbol is the maximum matching and becomes the answer of the recognition result.
This corresponds to the first candidate symbol number of the recognition buffer shown in FIG. and Figure 69A
Enter the symbol number 13 in the SNO column in the table SPTABLE shown. (5-2) If there is no item for which A+B is the maximum value, choose one whose C column has the maximum value, that is, one that matches the number of inverse logic symbols described in the symbol recognition dictionary and for which A+B is greater than a certain threshold. The one with the maximum frequency is taken as the answer of the recognition result. and the table
Enter the symbol number in the SNO field in SPTABLE. (5-3) If there is nothing that corresponds to either (5-1) or (5-2) above, set a threshold value for A+B+C and use the largest one that is greater than or equal to that value as the answer of the recognition result. do. and likewise
Enter the symbol number in the SNO field. (5-4) If there is no item that falls under (5-1) to (5-3) above, it is determined that it is not a symbol, and "1" is set in the STFLG column of the table SPTABLE. As described above, it is possible to give subclassifications to symbols. [XII] Processing of the start point setting processing section. This process is substantially the same as the above process [ ]. [] Processing of the reverse logic symbol processing section. The processing is as described in relation to FIG.
This is a process for temporarily shelving reverse logic symbols that may have an adverse effect on the process described later. In this case, since the processing is for the grid point corresponding to the start point,
#0 bit (S <sub>T</sub> ) is “1” and #1 bit (S <sub>2</sub> )
The grid point label code LOGLBL(i,
Execute the following processing only for j). (1) If #5 bit (S <sub>R</sub> ) of LOGLBL (i, j) is “1”, a #31 bit (R), #16 bit (F <sub>F</sub> ) of LOGLBL (i, j-1) b LOGLBL #29 bit of (i+1,j-1)
(L), #28 bit (D), #16 bit ( <sub>FF</sub> ) c #30 bit (U) of LOGLBL (i+1, j), #28 bit (D) d #30 bit of LOGLBL (i+1, j+1) (U), #29 bit (L), #16 bit (F <sub>F</sub> ) e Set #31 bit (R), #16 bit (F <sub>F</sub> ) of LOGLBL (i, j+1) to "0". (2) If #4 bit (S <sub>U</sub> ) of LOGLBL (i, j) is “1”, a #30 bit (U), #16 bit (F <sub>F</sub> ) of LOGLBL (i-1, j) b LOGLBL (i-1, j-1) #31 bit (R), #28 bit (D), #16 bit ( <sub>FF</sub> ) c LOGLBL (i, j-1) #31 bit (R), #29 Bit (L) d #29 bit of LOGLBL (i+1, j-1)
(L), #28 bit (D), #16 bit (F <sub>F</sub> ) e Set #30 bit (U), #16 bit (F <sub>F</sub> ) of LOGLBL (i+1, j) to "0". (3) If #3 bit (S <sub>L</sub> ) of LOGLBL (i, j) is “1”, a #29 bit (L) of LOGLBL (i, j−1),
#16 bit ( <sub>FF</sub> ) b #31 bit (R) of LOGLBL (i-1, j-1), #28 bit (D), #16 bit (F <sub>F</sub> ) c LOGLBL (i-1, j) #30 bit (U), #28 bit (D) d #31 bit (R) of LOGLBL (i-1, j+1), #30 bit (U), #16 bit ( <sub>FF</sub> ) e LOGLBL (i, j+1) ) #29 bit (L),
Set #16 bit (F <sub>F</sub> ) to “0”. (4) If #2 bit (S <sub>D</sub> ) of LOGLBL (i, j) is “1”, a #28 bit (D) of LOGLBL (i-1, j),
#16 bit (F <sub>F</sub> ) b #31 bit (R), #30 bit (U), #16 bit (F F ) of LOGLBL (i-1, j+1) c #31 bit (F <sub>F</sub> ) of LOGLBL (i, j+1) R), #29 bit (L) d #30 bit (U), #29 bit (L), #16 bit (FF) of LOGLBL (i+1, j+1) e #28 bit (F <sub>F</sub> ) of LOGLBL (i+1, j) D),
Set #16 bit (F <sub>F</sub> ) to “0”. [] Processing in the line breakage correction processing section near the start point. As described above, line breakage tends to occur on the lattice point label code LOGLBL in the vicinity of the starting point position of the symbol. This process corrects the existence of this undesired line break. In Fig. 80A, the starting direction is on the left, so bits #2 to #5 of the grid point label code are "0100".
This is the case. Column 5 in the figure schematically shows bits #2 to #5 of the grid point label code of the start point of the recognized logic symbol in detail, and column 4 shows the start direction (lattice point) one grid axis to the left. In this example, when the interval is 2 mm, bits #28 to #31 of the lattice point label code (2 mm to the left) are shown schematically. Case 1 indicates that the four-way code is "0100", that is, the line segment extends from the left and stops at the grid point. In case 2, the 4-way code is "0010", that is, the line segment descends from the top and stops at the relevant grid point, and in case 3, the 4-way code is "1000", that is, the line segment goes up from the bottom and stops at the relevant grid point. It shows that it is on. However, since there is a logic symbol terminal in this part as shown in the 5th column, this broken trace is a line break caused by inaccurate drawing, and the line should originally have extended one grid interval to the right. I decided that
Add the line segments as shown in columns 6 and 7. Specifically, the L of the 4-way code at the starting point.
(#29 bit) is set to "1", and R (#31 bit) of the 4-way code of the grid point to the left of it is set to "1". Fig. 80B shows the case where the starting direction is upward, and the 5th row shows it, and the 4th row shows the 4th direction of the grid point next to the above.
Diagrammatically shows the direction code. Cases 1, 2, and 3 are cases where the 4-way code is "0010", "0100", and "0001", and in all cases it is determined that the connection from the grid point to the start point is missing, and the 6th and 7th rows are D (#28 bit) of the 4-way code of the upper adjacent grid point as shown in
is set to "1", and U (#30 bit) of the 4-way code at the start point is set to "1". 80C shows the case where the starting direction is to the right, and FIG. 80D shows the case when the starting direction is downward, and in both cases, the correction as shown in the figures is carried out in accordance with the above. Through this process, it is possible to correct line breaks near the terminal positions of logic symbols that tend to occur due to handwriting, and to avoid line breaks. [] Gap/ambiguous arm processing unit processing. This process is a process similar to the above process [ ] at that point in time. That is, (1) The following processing is executed for the grid point label code LOGLBL (i, j) whose #8 bit (S) is "1". a #16 bit (F <sub>F</sub> ) of LOGLBL (i, j),
Set #11 bit (G <sub>F</sub> ) to “0”. (2) Execute the following processing for grid point label code LOGLBL (i, j) whose #8 bit (S) is "0". (2-1) If #11 bit (G <sub>F</sub> ) of LOGLBL (i, j) is “1” then a #15 bit (G <sub>R</sub> ) of LOGLBL (i, j)
#15 of LOGLBL(i,j) when is "1"
Bit (G <sub>R</sub> ), #31 bit (R) is set to “0”
Make it. b #14 bit (G <sub>U</sub> ) of LOGLBL (i, j)
#14 of LOGLBL(i,j) when is "1"
Bit (G <sub>U</sub> ), #30 bit (U) is set to “0”
Make it. c #13 bit ( <sub>GL</sub> ) of LOGLBL(i,j)
#13 of LOGLBL(i,j) when is "1"
Set bit ( <sub>GL</sub> ) and #29 bit (L) to “0”. #12 bit (G <sub>D</sub> ) of d LOGLBL (i, j)
When is "1", #12 of LOGLBL(i,j)
Set bit (G <sub>D</sub> ) and #28 bit (D) to "0". e Then, set #11 bit (G <sub>F</sub> ) of LOGLBL (i, j) to "0". (2-2) If the #16 bit (F <sub>F</sub> ) of LOGLBL (i, j) is “1”, a The #24 to #31 bits (F <sub>D</sub> , F <sub>L</sub> , F <sub>U</sub> , F <sub>R</sub> , D, L, U, R)
Set to "0". (3) Then, perform pairwise processing on the results. [] Processing of the line connector processing unit. If the line combination display bit (#18 bit) is set in an undesired manner at this point, this is corrected.
That is, (1) If symbol area "S=1";#18 bit is set to "0". (2) If "S=0", which is not a symbol area; (2-1) Check the 4-way code (D, L, U, R), count the number of bits that are 1, and perform the following processing according to the number. I do. a) If the number is 2, set #18 bit to "0". b) If the number = 3, set bit #18 to 1. c) If the number = 4, leave as is (no processing) [] Processing of the line segment erasure processing unit in the composite gate symbol. Since the connection lines within the region of the composite gate symbol are a predetermined pattern and do not need to be extracted, processing is performed to erase them. That is, (1) Extract the symbols that are constituent elements of the composite gate symbol from the symbol recognition table SPTABLE. In other words, the coordinates (i,
j) and the symbol number SNO. (2) Take out the terminal dictionary (starting point dictionary 20) according to the symbol number SNO. (3) Compare the contents of the start point dictionary 20 and the grid point label code to detect terminal positions and connection directions where the start point information (#0 bit) is not "1". That is, the terminal position and direction of the line segment within the composite gate symbol area are detected. (4) Symbol area (#8 bit = 1) or
The four-way code is traced to the start point (#0 bit = 1) or end point (no trace direction), and the next process is executed. (4-1) Grid point labels reached by tracking
For LOGLBL (i, j), a When tracking is performed to the left, #29 bit (L) is set to "0". b When tracking upward, set #28 bit (D) to “0”. c When tracking to the right, set #31 bit (R) to "0". d When tracking downward, set #30 bit (U) to "0". e Then, set #16 bit (ambiguity flag) to "0". [] Processing in the connection line extraction processing section. In this process, for the connection line (i) between the start point and the start point (ii) between the branch point and the branch point (iii) between the bend point and the bend point (iv) between the start point and the branch point ( v) Between the branching point and the bending point (vi) Between the bending point and the starting point, and is tracked to extract it as a vector. This can be achieved by tracing the above-described intensive grid point label code based on a four-way code, and a detailed explanation of the process will be omitted. [] Processing in the character area extraction processing section. After the symbols and connection lines are extracted from the drawing, the rest are characters. In this process, the grid point label code LOGLBL with the fuzzy flag #16 bit (F <sub>F</sub> ) set is extracted, and the character area is extracted. The processing is performed as follows. That is, (1) Grouping of character flags (2) Extraction of character strings (2-1) Extraction of image data (2-2) Extraction of connectivity of image data (2-3) Removal of graphic patterns and extraction of adjacent areas It consists of each stage. The details of each of the above processes will be explained below. (1) Grouping of character flags For example, as shown in FIG. 81A, what is not needed for the time being in the grid point label code is temporarily deleted and one bit is created as a character string flag M <sub>F</sub> , which is used as grid point data. Prior to processing, the character string flag M <sub>F</sub> of all grid point label codes is cleared. Also, the fuzzy flag F <sub>F</sub> can be called a character flag. In this process, the character flag of the grid point label code
Search F <sub>F</sub> and extract a group of character flags 22 (for each character string). A processing example is shown in FIG. 81B, in which the character string flag M <sub>F</sub> of bit #7 of a block of lattice point data 23 is set to "1". (2) Extracting character strings (2-1) Cutting out image data Cut out a rectangular area with n×n (n is the distance between grid axes) pixels centered on the grid point where the character flag M <sub>F</sub> is "1". This process will be explained below with reference to FIGS. 82 and 83. FIGS. 82A and 82B show examples processed by the above-described processing. That is, character 24 and line segment 25 in figure A are processed, black circle mark 26 in figure B indicates a grid point where character flag F <sub>F</sub> is "1", and the arm corresponding to the white circle has logic "1". 4-way code (DLUR)
is shown diagrammatically. In the grouping process using character flags, as shown in FIG. 83A, image data in the vicinity of lattice points is divided into groups using ○× character string flags 27. Therefore, if the image data near the grid points marked with ○× are cut out by the rectangular area 28, the 83rd
Image data 29 shown in Figure B is extracted. However, simply extracting the image data near the grid points using the grouped character flags is not enough.
As shown in the figure, there are cases where it is difficult to extract a complete character string due to deletion of a part of the character or inclusion of other graphic images. For this purpose, the following process will be introduced. (2-2) Connectivity extraction of image data For the image data cut out in the rectangular area 28 near the grid point where the character string flag M <sub>F</sub> is "1", as shown in FIG. 84, the image data in the rectangular area is It is checked whether or not is in contact with the outer line 30 of the rectangular area. (a) If all n×1 (or 1×n) areas are “0”, it is indicated as “AM(k)=0” and is non-connected. (b) “1” in the n×1 (or 1×n) area
If there is, it is indicated as "AM(k)=1" and there is a possibility of connection to the adjacent area. However, “k=
1, 2, 3, 4”. Figure 85 shows an example of this connectivity extraction.
Among the four directions of the image data of the rectangular area 28,
Only "AM(3)=0" is unconcatenated, "AM(1)=1" and "AM(4)=1" in the other three directions are character data 31
Therefore, “AM(2)=1” means the adjacent lattice axis line 32
This indicates that image data exists. (2-3) Removal of graphic patterns and cutting out adjacent areas a. Removal of graphic patterns within rectangular areas As a result of the image data connectivity extraction process, “AM
(k) = 1'', as shown in ``AM(2) = 1'' in the upper direction of the image data shown in Figure 85, when the lines of adjacent lattice axes are shifted, part of that line It's possible that it's coming in. Therefore,
If “AM(k)=1”, as shown in Figure 86,
Check the adjacent grid point label code corresponding to that direction and perform the following processing. That is, (i) If character flag (F _F = 1), then "AM(k) =
0". (ii) If the character flag "F _F = 0" and any of the 4-way codes (DLUR) are "1", line pattern removal processing is performed. (iii) Otherwise, leave as is. The line pattern removal process within the rectangular area 28 is executed in each direction that satisfies the above condition (ii), and as an example, the case of "k=1" is taken as shown in FIGS. 87 and 88.
This will be explained using figures. An area of m pixels from the outer edge of the cut out rectangular area 28 in the vertical direction (when "K=2, 4", the horizontal direction)
Check whether there is a column that is all "0" and perform the following processing. (iv) If there is a column where all values are “0”, clear the black points outside that column and “AM(k)=
0". (v) If there is no column that is all “0”, leave it as is. Figure 87 is a schematic diagram of this process, Figure 88 is a diagram of the 85th
The results of applying this processing to image data within a rectangular area in the figure are shown. After applying this process, “AM(k)=
1'' indicates that character data is continuous in that direction. In addition, in Figure 88, even though the character data is continuous in the right direction, "AM(1)
= 0" because the character flag F _F of the grid point label code on the right side is set to "1". A region near the point is cut out. b Cutting out adjacent rectangular area For the rectangular area mentioned above, if “AM(k)=1”, image data near the adjacent grid point in that direction is
×n pixels are extracted and the following figure pattern removal process is executed. As an example, the case of "k=1" will be explained. For the image data within the cut out rectangular area 33,
As shown in Figure 89, from left to right, the first column to the
Sequentially count the number of sunspots B _CNT in each column (for example, in the case of "k=2", each row is from the nth row to the (n-w+1)th row from bottom to top), and calculate B _CNT ≧TH or B If _CNT = 0, all black points from that column to the w-th column including that column are cleared. Furthermore, all black pixels from the (w+1)th column to the nth column are unconditionally cleared. Note that TH is a predetermined threshold value. FIG. 90A shows the image data cut out near the adjacent grid points in the downward direction (AM(4)=1) of the rectangular area shown in FIG. 88, and FIG. 90B shows this image data according to the above a). The results of the graphic pattern removal process shown in FIG. All string flags M _F are "1"
By applying this to a character string, image data of one character string can be extracted. In FIGS. 91A and 91B, complete characters are extracted by removing unnecessary graphic patterns and complementing the partial patterns of the deleted characters. [] Character separation processing in the character separation/recognition processing unit. The characters of the string extracted in the above process [] are separated character by character in this process,
To facilitate recognition processing. The process is shown below. Here, "V _2B " shown in Figure 92 is used as a character string.
The following is a processing procedure for cases where separation is difficult as is. Figure 92 depicts character strings 31 ₁ to 31 ₃ in a rectangular frame 3 that is one pixel larger in each direction than its circumscribed rectangle.
The image cut out by 4 is shown. Scanning this image with a window 35 shown in the figure, that is, a window perpendicular to the character string direction and having a length equal to the vertical width of the rectangular frame 34 and having a width of 1 pixel, from one end of the area within the rectangular frame, First, the position where the black dot 36 appears within the window 35 is detected. FIG. 93 shows the positions where black dots 36 are detected by the window 35 for the character strings 33 ₁ to 33 ₃ in FIG. 92. Next, the shortest path between the white pixels at both end positions "S" and "E" of the window 35 at this position is found, and the search area is moved from the position of the window 35 in the scanning direction of the character string, that is, to the right in the figure. limited to direction. 93rd
The character end position 37 indicated by the "+" mark in the figure is a label indicating the limitation of the search area. That is, the area to the right of the "+" mark is the search area. Although various algorithms have been proposed to extract the shortest path, here, Lee's algorithm will be used for explanation. Two points “S” determined by the above processing,
One of “E” first, for example “S”
Choose as a starting point. First, a label "1" is given to the white point directly adjacent to "S" (four-way connection). Next, a label "2" is given to the white point adjacent to the pixel given the label "1". Label "3" is given to the white point adjacent to label "2". Further, a label "1" is given to the white point adjacent to the label "3". Repeat this below. This process ends at “E”
This procedure continues until reaching . Figure 94 shows the results of this labeling procedure. Next, this label is traced in the reverse order of labeling from the end point "E" in the order of "3" → "2" → "1" → "3" in the reverse order of labeling, until it reaches the start point "S". Find a path. Although this route is the shortest route, it is not necessarily determined uniquely. In order to uniquely determine this, as shown in FIG. 95, priorities are set in the direction of reverse tracking, and tracking is performed in accordance with these priorities. FIG. 96 shows the shortest path detected by back tracking, and the label "+" is given to the pixels 38 on the path during back tracking. Through the above processing, an area where one character in a character string exists is identified as an area surrounded by "+". Therefore, by cutting out the black dots within this area, the image of one character is separated and extracted. Figure 97 shows the rectangular frame 3 after separating and extracting one character.
This is an image of the character strings 33 ₂ and 33 ₃ in the area No. 4. Through the above process, each time a character is extracted, a white point,
After converting pixels with labels other than black dots to white dots, the process is repeated until no black dots are detected within the rectangular area, whereby each character of the character string can be separated and extracted one by one. That is, as shown in Figure 98, the next character 3
3. A window is set for ₂ , a label 39 representing the limit of the search area for the next character is determined, and the steps in FIGS. 93 to 97 are repeated. [XI] Character recognition processing in the character separation/recognition processing unit. In the above process [ ], a recognition process is performed on each character separated, but the mode of this process is arbitrary and is conventionally known, so a description thereof will be omitted. Although the processing is executed as described above, FIG.
1 shows a hardware block diagram of an embodiment for carrying out the above process. In the figure, 101 is an image input device, 102 is an image memory, 103 is a verification circuit, 104 is a reference point detection circuit, 105 is a grid point table, 106 is a grid conversion circuit (horizontal), and 107 is a grid point label code generation circuit. (horizontal), 108 is a grid conversion circuit (vertical), 109 is a grid point label code generation circuit (vertical), 110 is an address control section, 111 is a control section,
112 is a verification window setting circuit; 113 is an LBL table that sets the code LBL; 114;
is the LB1 table, 115 is the LB2 table, 11
6 is SX1, SY1 table, 117 is SX2, SY
2 tables, 118 is an address conversion circuit, 119
120 is an LB3 generation circuit that generates local shape label information; 120 is an LB3 table in which the local shape label information is set;
1 is a grid point label/code determination circuit, 122 is a label/code table, 123 is a pair processing circuit,
124 is a line pattern breakage correction circuit, 126 is a deviation correction circuit, 127 is an ambiguity correction circuit (), 1
28 is a symbol dictionary, 129 is a symbol extraction circuit,
130 is a symbol recognition table, 131 is a composite gate/symbol recognition dictionary, and 132 is a composite gate/symbol recognition dictionary.
Symbol terminal position dictionary, 133 is a composite gate/symbol recognition circuit, 134 is a single/gate symbol candidate dictionary, 135 is a single gate/symbol terminal position dictionary, 136 is a single gate/symbol recognition circuit, 137 is a symbol area setting circuit, 138 is a deviation correction circuit (), 139 is an ambiguity correction circuit (), 140 is a gap/ambiguity processing circuit, 1
41 is a page connector recognition processing circuit, 142 is an inverse logic/symbol processing circuit, 143 is a terminal position determination circuit, 144 is a terminal vicinity line breakage correction circuit, 14
Reference numeral 5 represents a line segment extraction circuit, 146 a line segment extraction preprocessing circuit, 147 a character area extraction circuit, 148 a line connector processing circuit, and 149 a recognition result output device. (E) Effects of the Invention As explained above, according to the present invention, it is possible to automatically read a handwritten logic circuit diagram and input information regarding the logic circuit diagram into a data processing device.

[Brief explanation of drawings]

FIG. 1 is an example of a logic circuit diagram processed by the present invention, FIG. 2 is a diagram explaining the processing range for obtaining lattice point label codes, and FIG. 3 is an example of the processing for obtaining lattice point label codes. 4 is an overall configuration diagram of an embodiment of the apparatus of the present invention, FIG. 5 is a format of an embodiment of the grid point label code used in the present invention, and FIGS. 6 to 10 are diagrams for explaining embodiments.
11 is an example of the drawing input process in the processing section shown in FIG. 4, and FIGS. Figures 14 to 52 are explanatory diagrams of an embodiment of distortion correction processing.
A 53rd diagram illustrating a processing mode for obtaining an intensive grid point label code in the illustrated processing unit.
55 to 55 are diagrams for explaining the processing mode for extracting line connectors, FIGS. 56 to 58 are diagrams for explaining the processing mode for extracting inverse logic symbols, and FIG. FIG. 60 is a diagram explaining the processing of the processing unit shown in FIG. 4, FIG. 61 is a diagram explaining the processing of the processing unit shown in FIG. 4, and FIGS. 68 is a diagram explaining the processing of the processing section shown in FIG. 4, and FIGS. 69 to 76
The figure is a diagram explaining the processing of the processing section shown in FIG.
77 and 78 are diagrams for explaining the processing of the processing section shown in FIG. 4, FIG. 79 is a diagram for explaining the processing of the processing section shown in FIG. 4, and FIG. 80 is a diagram for explaining the processing of the processing section shown in FIG. 4. Figures 81 to 91 are diagrams explaining the processing of the processing unit shown in Figure 4, and Figures 92 to 98 are diagrams explaining the processing of the processing unit shown in Figure 4. 99 shows a hardware block diagram of one embodiment for implementing the configuration shown in FIG. 4. In the figure, 1 is the drawing to be processed, 2 is the processing result information,
LOGLBL is the grid point label code, and _G5 represents the grid point.

Claims (1)

[Claims] 1. From image data obtained by reading a handwritten drawing in which there are symbols drawn along predetermined grid axes, line figures including connections between symbols, and drawing figures including characters, In a logic circuit diagram processing device that recognizes and extracts line figures and graphic figure parts, a lattice point label code generation means for generating a lattice point label code indicating the possibility of the existence of image data near a lattice point; a positional deviation verification means for verifying the positional deviation of the image data with respect to the grid points based on a code; and local shape extraction for determining the local shape of the image data and identifying the possibility of the existence of a line figure or a drawing figure. means for extracting a line connector for determining the possibility of the existence of a connector at the intersection when the image data intersects on the grid point; circular shape extraction means for determining the possibility; at least the lattice point label code obtained from the lattice point label code generation means; the positional deviation information obtained from the positional deviation verification means; and the positional deviation information obtained from the local shape extraction means. image data information in the vicinity of the lattice points was aggregated based on the local shape label information obtained from the above, the line connector information obtained from the line connector extraction means, and the circular shape information obtained from the circular shape extraction means. an intensive grid point label code generation unit that determines an intensive grid point label code; a symbol recognition unit that recognizes single and compound symbols based on the intensive grid point label code; and said intensive grid point label code. and a line segment extraction means for extracting connections between symbols from the symbol information obtained by the symbol recognition means; and a character region for extracting character strings and separating characters from the intensive grid point label code and the image data. 1. A logic circuit diagram processing device comprising: extraction means.