JPS6048580A - Processor logical circuit diagram - Google Patents

Abstract

PURPOSE:To attain the automatic input processing with a logical circuit diagram by recognizing and extracting a linear pattern and a picture pattern separately from each other on the basis of an intensive lattice point label code. CONSTITUTION:Both linear and picture patterns drawn along a prescribed lattice axis are read, and a lattice point label code showing the possibility for existence of the picture data at a place near the lattice point is produced at a label code generating part. Then the pattern of a prescribed form is extracted at a circle triangle extraction processing part. A label code noise processing part eliminates the noise of the produced lattice point label code. A composite gate symbol recognition processing part recognizes a composite gate symbol and fixes a symbol area. In addition, the recognition of a single gate symbol, the processing of a reverse logic symbol and the extraction processing of segments are carried out to separate and recognize the characters. Then these characters are delivered.

Description

Detailed Description of the Invention (A) Technical Field of the Invention The present invention relates to a logic circuit diagram processing device, particularly for reading handwritten drawings in which line figures drawn along lattice axes and graphic figures including characters are mixed. In the logic circuit diagram processing device that recognizes and extracts logic symbols, line segments, and graphic figure parts, the image data in the vicinity of the grid points is configured to be summarized into an intensive grid point label code, and the intensive grid point label - This invention relates to a logic circuit diagram processing device that performs the above-mentioned recognition processing based on a code.

(B) Technical Background and Problems Traditionally, hand-drawn logic circuit diagrams have been input into data processing equipment. Users were required to enter the information while inputting the information. In this case, for example, considering inputting a straight line, for each line, the operator should:
It is necessary to indicate the coordinates of one end of the line and the coordinates of the other end, and to input information indicating that the line is a straight line. For this reason, this is not much of a problem when inputting relatively simple circuit diagrams, but when inputting extremely complex circuit diagrams such as IC circuits, data input becomes extremely complicated and requires considerable patience on the part of the operator. Moreover, input errors are likely to occur.

(C) Object and Structure of the Invention In view of the above points, the present invention aims to provide a processing device that automates the input processing of logic circuit diagrams, and it It is an object of the present invention to provide a processing device that performs the above processing by employing a method of consolidating image data in the vicinity of lattice points into an intensive lattice point label code for a drawn line figure. Therefore, the logic circuit diagram processing device of the present invention is capable of processing logic circuits from image data obtained by reading a handwritten drawing in which there are line figures drawn along predetermined grid axes and graphics figures including characters. In a logic circuit diagram processing device that recognizes and extracts symbols, line segments, and graphics parts, a lattice point label code generating means for generating a lattice point label code indicating the possibility of the existence of image data near a lattice point; verification means for verifying the positional deviation of the image data with respect to the grid points based on the point label hood; a positional deviation information holding means for holding positional deviation information obtained from the verification means; and a local shape of the image data. a local shape extracting means for determining the possibility of the existence of a line figure or a drawing figure, a local shape label holding means for holding local shape label information output from the local shape extracting means, and at least the above-mentioned lattice points. a label code generation unit that determines an intensive grid point label code that aggregates image data in the vicinity of the grid point based on the label code, the positional deviation information, and the local shape label information; The present invention is characterized in that the line figure and the drawing figure are separately recognized and extracted based on the label code. This will be explained below with reference to the drawings.

(D) Embodiments of the Invention In the present invention, drawings drawn along the grid axes (X-axis and Y-axis) as shown in FIG. A drawing containing a mixture of drawings and figures is read with an optical reading device such as a facsimile input device, the read image data is aggregated as data on grid points (lattice axis intersection points), and then logical symbols and line segments are ,
It is attempted to separate the information into character parts, perform recognition processing, and then input the data to the data processing apparatus. Furthermore, if it is assumed that, for example, the line figure V shown in FIG. 3 exists around the grid point G5 shown in FIG.
As will be described later, within the range of the arrow shown in FIG. The direction in which the line segment exists (up, down, left or right), the deviation to the position where the line segment exists, etc. are extracted, aggregated, and stored as information on the grid point G5. Then, based on each intensive grid point label code, characters, logical symbols, etc. are recognized,
The information is input to a data processing device.

FIG. 4 shows the overall configuration of an embodiment of a logic circuit diagram processing apparatus according to the present invention. Reference numeral 1 in the figure represents a drawing to be processed, and 2 represents processing result information extracted by the logic circuit diagram processing apparatus according to the present invention. The following is a detailed explanation of each component (I), (2), etc. shown in Figure 4. The outline of each component processing section (1), (2), etc. You can think that.

(1) Input processing unit for drawings and various information.

Drawing 1 is read by an input device such as a facsimile or a drum scanner, and the read image data is subjected to so-called pre-processing such as noise removal and smoothing, and then stored in an image memory.

Then, various information such as the size and orientation of the input drawing, the number of grids, etc. are input interactively using a display, keyboard, light, pen, etc. Further, in order to correct the inclination of the input drawing, set the recognition area, etc., the coordinate positions of the reference points ("+" marks shown in FIG. 1) written at the four corners of the drawing are input.

(2) (a) Label code generation processing section.

The image data address of each grid point is calculated from information such as the orientation of the input drawing, the number of grids between reference points, and the position of the reference points, and the image data is corrected for tilt. The shape characteristics of the image data are expressed as a grid point label code LOGLBL shown in FIG. Note that the lattice point label code first obtained in the processing section (2) (a) is called an initial lattice point label code LBL. Then, based on the label code LBL, an intensive lattice point label code is generated through processing by the first verification processing section 2, the second verification processing section, the local shape extraction processing section, etc. as described later.

In addition, here, the above lattice point label code LBL or LO
Let me briefly summarize each bit of GLBL.

i) #28 to #31 bits These bits are direction codes, and as described later, represent the direction in which the line segment extends from the grid point G6, including downward direction (D), leftward direction ( Corresponding to L), upward direction (U), and rightward direction (R), logical "
1”.

ii) Bits #24 to #27 These bits are "fuzzy" direction codes, indicating whether a line segment, if present, has a complex shape. In other words, whether or not it seems to be part of a character is expressed using logic "1". For example, the #24 bit FD being logic "1" indicates that the line segment (D=1) extending below the grid is likely to be part of a character.

iii) #19 to #22 bits These bits are a deviation direction code, and indicate in which direction the existing line segment deviates from the grid point.

iv) #12 to #15 bits These bits are gap direction codes, and indicate whether a break exists in a line segment extending in any of the up, down, left, and right directions of the grid.

v) #16 bit This bit is an "ambiguous" flag, and is set to logic "1" when any one of bits #24 to #27 is logic "1".

vi) a23 bit This bit is a “deviation” flag, and #19 to #2
2 is set to logic "1" when any one of them is logic "1".

vii) #11 bit This bit is a gap flag, and #12 to #
When any one of the 15 bits is logic "1", logic "
1”.

viii) #18 bit The bit is a line connector display flag.

To indicate that the connection lines in the logic circuit diagram are electrically connected, check whether a black circle (called a line connector display flag) placed at the intersection of the connection lines exists at the relevant grid point. It represents something.

If it exists, it is set to logic "1".

ix) #9 bit This bit is a triangular display flag, and is set to logic "1" when a triangular pattern exists corresponding to the grid point.
”.

x) #10 bit This bit is a large circular shape display flag, and is set to logic "1" when a large circular pattern exists corresponding to the grid point.

xi) #17 bit This bit is a small circle shape display flag, and is set to logic "1" when a small circular shape pattern exists corresponding to the grid point.

xii) #8 bit This bit is a symbol area flag, and indicates that a logical symbol is written corresponding to the grid point.

xiii) #0 bit This bit is a start point flag, and indicates that the corresponding lattice point is the start point (terminal position) of a logic symbol.

X1v) #1 bit This bit is a reverse logic symbol display flag,
This indicates that a small circular pattern (reverse logic symbol) that provides negative logic is attached to the start point indicated by the #0 bit.

xv) #2 to #5 bits These bits are a start point direction code, and indicate in which direction, up, down, left, or right, the connection line connected to the start point indicated by the #0 bit extends.

(2) (b) Circle/triangle extraction processing section.

#9 bit in the grid point label code shown in Figure 5, #
It is extracted whether each pattern of the shape as shown in the 10th bit and the #17th bit exists.

(3) Label code/noise processing section.

#11 to # of the generated initial grid point label code
Corresponding to 31 bits of information, noise present in each piece of information is removed.

(3) (a) Outward arm removal unit.

The direction code corresponding to the arm protruding outside the frame of Drawing 1 is set to logic "0".

(3) (b) Pair of processing units.

Between mutually adjacent grid points, if there is an arm pointing toward the other at one of the grid points, and if there is no arm to be paired at the other grid point, the direction corresponding to the arm. Set the code to logic “0”.

(3) (c) Line breakage correction unit.

To correct line segments that should originally exist as one line into a connected form for line breaks within one grid interval.

(3) (d) Misalignment correction I unit Extra misalignment direction code (#1
9 to #22 bit) and deviation flag (#23 bit)
and is set to logic "0".

(3) (e) Ambiguous correction I unit Focusing on one grid point, correct the ambiguous direction code (#24 to #27 bits) etc. based on the grid point labels and codes of adjacent grid points in four directions. do.

(4) Symbol classification processing section.

Based on the 4-way code in the grid point label code, the position of the logical symbol (symbol) in drawing 1 and its shape (type)
and extract. However, in this process, it may be considered that classification is performed at the level of major classification.

(5) Composite gate/symbol recognition processing unit.

As shown in FIG. 6, the logic circuit diagram processing device of the present invention recognizes a set of a plurality of logic symbols as a composite gate symbol C-G having a certain meaning. . The recognition processing unit recognizes the composite gate symbol based on the type and positional relationship of each symbol. Then, for the recognized composite gate symbol, the start point flag (#0 bit) and start point code (#
2 to #5 bits) and the reverse logic symbol display flag (#1 bit).

(6) Symbol area setting processing unit.

Among the logic symbols to be read by the logic circuit diagram processing device of the present invention, one symbol may be extracted redundantly as different symbols depending on the reading state, as shown by arrows a and b in FIG. 7. There is a risk. In order to correctly detect symbols that have been extracted repeatedly in this way, or to ensure that subsequent processing is performed correctly, a flag is set to clearly indicate that the information on the grid points is determined as part of the symbol. urge That is, the symbol area flag (#8 bit) shown in FIG. 5 is set to logic "1".

(7) Line segment determination processing section.

After the symbol areas are determined, connection lines connecting the symbols are determined.

(8) Gap/ambiguity arm processing part I.

After the connection line is confirmed, the gap direction code (#
12 to #15 bits) and ambiguous direction code (#2
4 to #27 bits), the four-way code in that direction is set to logic "0", and then the same processing as that of the processing unit (3) (b) is performed.

(9) Single gate symbol recognition processing unit.

In the symbol classification in the processing unit (4) described above,
Extraction was performed based on the rough shape characteristics of the symbols, but the single processing unit (9) extracted the symbols as shown in the two symbols in Figure 8 (A) and the two symbols in Figure 8 (B). A single gate symbol is determined by distinguishing between symbols belonging to the same group, for example, by whether or not an inverted logic symbol C is attached as shown in the figure.

Then, for the recognized single gate symbol, the start point flag (#0 bit), start point code (#2 to #5 bit) and reverse logic symbol are displayed in the grid point label code at the start point position. flag (#1 bit).

(10) Start point setting processing section.

2 symbols in Figure 9(A), 2 in Figure 9 iBl
Regarding the three symbols in the N19 diagram tcl, the shapes of the symbols are the same, but the directions and positions in which the connection lines are drawn vary. In order to distinguish and identify each of these symbols, the state of the starting point candidates of one symbol is checked, the starting points of these symbols are determined, and starting point information is set in the grid point label code.

(11) Reverse logic symbol processing unit.

When processing a symbol with an inverted logic symbol as shown in FIG. 10(A), each symbol in the vicinity of the inverted logic symbol is 4-way code in grid point label code (
#28 to #31 bits) can appear in various ways. If such a condition exists, it will have an adverse effect on later tracking processing, so the excess four-way code should be temporarily removed as shown in FIG. 10(C). The main processing unit (11) performs such processing.

(12) Line breakage correction processing unit near the start point.

A so-called line break (gap) is likely to occur near the starting point position of a symbol. This processing section (13) performs this correction processing.

(13) Pre-processing section for line segment extraction.

Before finally extracting the connection lines connecting symbols, preprocessing is performed.

(13) (a) Gap/ambiguous arm processing II unit At this point, the gap direction code (#12 to #15
A four-way code (bits #28 to #31) of the corresponding direction is dropped to a grid point where a fuzzy direction code (bits #24 to #27) is set. Then, a pair of processes similar to those of the processing unit (3) (b) described above are performed.

(13) (b) Processing unit for line connector Performs predetermined processing (described later) on the line connector corresponding to the branch point of the connection line.

(13) (c) Line segment erasure processing unit in composite gate symbol The connection line in the composite gate symbol is a pattern known in advance, and there is no need to recognize this connection line. This unit (13) (c) erases this line segment.

(14) Connection line extraction processing section.

In order to extract the connecting lines as individual vectors, i) start point - start point ii) branch point - branch point iii) bend point - bend point iv) start point - branch point v) branch point - bend point vi) bend Track the 4-way code between point and start point. Then, connect lines are extracted. For lines for which tracing is not completed, there is a possibility that the line is part of a character, and the ambiguity flag (#16 bit) of the grid point label code is set to logic "1".

(15) Character area extraction processing unit.

After extracting the symbols and connection lines from the drawing 1, the remaining drawings and figures such as characters remain.

The main processing unit (15) extracts a character area (image/figure area) based on the ambiguity flag (#16 bit) of the lattice point label code.

(16) Character separation/recognition processing unit.

For example, each character of a character string extracted by the processing unit (15) is separated character by character and character recognition is performed using a single character recognition processing technique.

(17) Result output processing unit.

Each symbol information, connection line information, and character information extracted as described above is output to an external storage medium such as a floppy disk, or transmitted to another data processing device via a line.

In the above, we have outlined the processing performed by each constituent processing section (1), (2)... of the logic circuit diagram processing device shown in Fig. 4, but below we will explain more specifically the important processing in each processing section. I'm going to go.

[I] Drawing and various information input processing section (1) Main processing section (1)
In this case, it is necessary to correctly indicate the coordinates of the reference points (the "+" marks at the four corners) shown in FIG. 1 in order to correct the subsequent tilt and distortion. In other words, one processing unit (1
) displays the input results (contents on the image memory) on a television monitor, and instructs at which coordinate position the reference point is displayed on the display screen;
At the time of subsequent correction, correction is performed based on the coordinate position that should originally exist and the coordinate position as a result of the input.

The input figure is stored on the image memory as having a size of, for example, 2048×3072 dots.

For this reason, the entire input graphic cannot be displayed as is on the television monitor at once, but is displayed in a reduced form.

As a result, even if the reference point is indicated on the reduced display screen, it is not necessarily possible to obtain a higher degree of accuracy.

In order to overcome this problem, the reference point is specified with high precision by the procedure shown in the flowchart shown in FIG. That is, (1) First, the video data of the input figure is enlarged at a magnification rate of 1/
8 and displays the first half (2048×1536 dots) of the input figure.

(2) Next, write the area where one of the reference points exists.
After specifying with a pen, the area is displayed at a magnification of 1.

(3) Next, use a light pen to indicate the area where the reference point exists, and then display the area at a magnification of 8.

(4) In this state, write the one reference point.
Instruct by pen. If the instruction cannot be made correctly, the correction is made until the instruction is made correctly, and when the instruction is made correctly, the instruction point is sent out as one of the reference points (written on the image memory as the first reference point).

(5) Next, the first half (2048 x 1536 dots) of the input figure is displayed again at a magnification of 1/8, and the second reference point is set by the same operations as steps (2) to (4) above. written onto image memory.

(6) Next, the second half of the input figure (
2048 x 1536 dots) will be displayed, and the above operation (
The third reference point is written on the image memory by operations similar to 2) to (4).

(7) After that, the second half of the input figure (2048 x 1536 dots) is displayed again at a magnification rate of 1/8, and the fourth reference point is set by the same operations as steps (2) to (4) above. It is written to the image memory and becomes the end.

[II] Image data tilt correction in label code generation processing section (2) (a).

The label code generation processing unit (2) (a) detects how the reference point deviates from its original position based on the coordinates of the reference point input as described above, and converts the image data into It is necessary to correct the tilt and distortion of the image. This process will be described below.

Generally, the coordinates of the reference point are (0,
0), (XW, O), (0, YW) + (XW+YW), when the input drawing 1 given by It happens that it is stored. For this purpose, as described above, for the input drawing 1-1 stored on the image memory,
When a reference point is indicated with a light pen, the indicated reference point will be shown in FIG. 12(B) with the coordinates (0,
0), (Xa, Ya), (Xb, Yb), (Xc, Yc
) is given as

Input drawing 1 shown in Figure 12 and stored input drawing 1-1
Assuming that they coincide at the illustration origin (0, 0), the point (x, y) on the input drawing 1 is the point (x', y) on the drawing 1-1 that has undergone rotational distortion. ′), there is the following relationship. Therefore, the point (x,
y) is located at the point (x', y') on the image memory.

However, performing the above correction for each pixel on the figure is extremely difficult and requires a large amount of processing. For this reason, in the case of the present invention,
Limit the following corrections so that the minimum amount of correction is required within the allowable range.

That is, the input drawing 1 is divided into divided regions 3 each consisting of m×n pixels, and the coordinate position of each divided region, for example, the upper left corner point (x0, y0) of region 3-1, is located on the image memory. Determine. That is, the correspondence between the illustrated (x0, y0) and (x0', y0') is determined based on equation (1). Then, the segmented area 3-1 given by the m×n pixels is as if the m×n pixels shown by the dotted line in FIG. 12(B)
Let us assume that the divided region 3'-1 is given by n pixels. In other words, regarding drawing 1, the upper left corner point (xO, y0) of segmented area 3-1 has the coordinates (x0', y
0'), in processing each pixel in the segmented area 3-1 to be read, the coordinate point (x0', y0') on drawing 1-1 is ), an m×n pixel segmented area 3'-1 is read and processed by extracting m pixels in the horizontal direction and n pixels in the vertical direction.

It will be easily understood that by adopting this method of dividing into each divided area, the amount of correction processing becomes 1/m·n. However, by adopting such a simplified method, it is necessary to evaluate how much error is included in each pixel within the segmented area 3'-1. When the size of segmented area 3'-1 is selected to be 10 x 10 pixels, and if an error of up to 2 pixels is allowed with respect to the true pixel position on input drawing 1, the calculated rotation angle θ is approximately 11 It is sufficient if it is less than °. Further, assuming that an error of one pixel at most is allowed, it is sufficient that the two rotation angles are 5 degrees or less. Conversely, if a rotation of about 20 degrees actually occurs, assuming that an error of up to 2 pixels is allowed, the segmented area 3'-
This means that the size of 1 should be selected as 5×5 pixels.

Even when performing error correction using the simplified method described with reference to FIG. 12 (A) (b) above, it is complicated to measure the rotation angle θ, and measurement errors are likely to be introduced. The following processing is performed.

13(A) and (B) are for example 4 of the input drawing 1.
2 reference points (0, 0), (XW, 0), (0, YW),
(XW, YW) is given, and any point (X, YW) is given.
Point (X', Y') on figure 1-1 where Y) has undergone rotational distortion.
It shows that. From the above equation (1), there is a relationship as follows: X'=Xcosθ+Ysinθ Y'=Ycosθ−Xsinθ. Here, as shown, XW, YW, XL, Y
Considering L, ΔX, ΔY, X″, and Y″, it is expressed as follows.

Here, the above reference point (0, 0) on input drawing 1, (XW
, 0), (0, YW), and (XW, YW) are known in advance. Then, display the figure 1-1 on a TV monitor, for example, and input the coordinates of the point corresponding to the reference point using a light pen (0, 0), (Xa, Ya), (Xb
, Yb), (Xc, Yc), XL=X
It is given as a known value as c-Xb ΔX=Xb YL=Yc-Ya ΔY=Ya.

[III] Initial lattice point label/code generation in label code generation processing unit (2) (a).

When the inclination of the image data read onto the image memory is corrected as described above, in the present invention, as shown in FIG.
As described above with reference to FIG. 3, the image data in the vicinity of the grid point G5 is expressed in the form of a grid point label code.

The initial lattice point label code roughly grasps the graphical structure in the vicinity of the lattice point, and its generation method will be described below.

First, the image data obtained by reading the handwritten drawing is
As shown in the figure, lattice axes X1 to X3 and lattice axis Y1
As shown in FIG. 14, there is a window W1-X with a size of n×1 pixel corresponding to the grid width n and a window portion W1-X with a size of 1×n pixels centered on the grid point G5, as shown in FIG. Window part W1
-y to scan in the X and Y directions, respectively. When even one black point exists within this window, this is set as the black point detection output of each window as "1" and is stored in the holding section "1-
As a result, the image data shown in FIG. 14 is held in windows W1-X and W1-Y, respectively.
When scanning is performed with
The output "1" as black point information from -Y is held as the projection result on each grid axis.

Next, as shown in FIG. 15(A), rightward regions R0 and "1" are defined for the holding section "1-X," and the sum of "1" (indicating black point information) in these regions is calculated. Therefore, if it is above a certain threshold, the information "R=1" is determined that there is a possibility that a line segment exists to the right of the grid point G5, and if it is below the threshold, the information "R=1" is determined that there is a possibility that a line segment exists in the right direction of the grid point G5. R=0'' is determined. In the same way, left direction regions L0 and L1 are defined, and the sum of "1" in each region is calculated. If this is more than the threshold value, the information "L=
1" is determined, and if it is less than the threshold value, "L=0" is determined.

Of course, as shown in FIG. 15(B), the holding part "1-Y" also has upper and lower regions U0 and U1 and a lower region D.
0, D1 are determined and the upward direction information "
U=1 or 0" and downward direction information "D=1 or 0" are determined. In this way, the initial grid point label code (L
BL) D, L, U, and R are recognized, and for example, for the image data in Figure 14, as shown in Figure 16 (A), there may be line segments above and below, and there may be line segments on the left and right. It is said that there is no sex.

As shown in FIG. 16(B), the initial lattice point label code "LBL=1O1O" for the lattice point G5 is determined.

In this way, it is shown that for the image data as shown in FIG. 17(A), there is a possibility that line segments exist at the top, bottom, left, and right, as shown in FIG. 17(B). The initial grid point label code “LBL=111” shown in FIG. 17(C) in the form
1", and for the image data shown in FIG. 18(A), the image data shown in FIG. "LBL=0111" shown in FIG. 18(C) is set, and "LBL=0111" is similarly set for the image data shown in FIG. 19(A).
I get criticized.

[IV] Processing of the first verification processing section in the label code generation processing section (2) (a).

The first verification process is to verify, based on the initial lattice point label code LBL, whether a line segment actually exists in the vicinity of the lattice point in the direction corresponding to the initial lattice point label code LBL. be.

First, as shown in FIG. 20, WV0 to WV2. WH0～
Each first verification window portion of WH2 is provided. These first verification windows are determined based on the LBL, and “R=
1, when L=1, the first verification window WV0 of 1×n pixels
and when “R=0, L=1”, 1×(n/2+
1) Using the first verification window WV1 of the pixel, "R=1, L
=0'', the first verification window WV2 of 1×(n/2+1) pixels is used. When "U=1, D=1", the first verification window WH0 of n×1 pixels is used, and "U=0, D=1" is used.
When “D=1”, the first verification window WH1 of (n/2+1)×1 pixel is used, and when “U=1, D=0”, (n/2+1)×1 pixel is used.
2+1) A first verification window WH2 of X1 pixels is used. Then, as shown in FIGS. 21(A) and (B), these first verification windows are slid vertically (or horizontally) with the horizontal grid axis (or vertical grid axis) as the starting point, and the sunspot information is displayed. are accumulated, and first the position where the first verification window is completely filled with "1" which is black point information is detected. The slide width for this slide operation is half the grid distance in both the vertical and horizontal directions.
That is, it is within the range of n in FIGS. 21(A) and 21(B).

This sliding operation detects whether there is a line segment in the vicinity of the grid point in the direction according to the initial grid point label code, and if so, how far that line segment deviates from the grid axis. be able to. Then, these pieces of deviation information are extracted as first verification deviation information SX1 and SY1. Here, the signs of <SX1, SY1 are displayed as follows.

SX1: Lateral deviation +right direction; -left direction SY1:
Vertical shift +downward; -upward However, if the black dot does not completely fill the window within the n-pixel slide width, "99
Set the value "9". If a horizontal or vertical line segment is not detected as the initial grid point label code LBL, "1" is set as SX1 and SY1 to indicate that no slide operation was performed in that direction.
Set the value "000".

FIGS. 22 to 25 show states in which the first verification process is performed on various figures to verify their deviations.

In FIG. 22, when the first verification window WH0 in FIG. 20 is slid 4 pixels to the right from the lattice axis according to "LBL=1010", the first verification window WH0 can be filled with black dots. SX1=+4''.

However, since it is "LBL-1010", there is no need to perform vertical sliding operation, so to indicate this, "S
Y1=1000". Also, in Figure 23, “LBL
= 1111'', and at this time, the first verification windows WH0 and WV0 are filled with black dots on the lattice axis without the need to slide the first verification windows WH0 and WV0, so SX1 = 0.SY1 = 0". and the 24th
In the figure, "LBL=0111", and in this case, the first verification window WH2 is
The verification window WH2 is all black dots, and the first verification window WV0
If you slide 3 pixels downward, you can make all of them black points, so "SX1=-1, SY1=+3"
becomes. However, in the figure of Fig. 25, “LBL=
0111'', and when the first verification window part WH2 is slid one pixel to the left, the first verification window part WH2 can be completely turned into a black point. Even if it slides with the width n shown in Part 21 (A), this first verification window WV0 cannot be filled with black dots, and therefore "S
X1=-i, SY1=999''.

Based on the first verification deviation information SX1 and SY1 determined as above, the rectangular area that captures the graphic structure in the vicinity of the lattice point is moved to position the line segment within the rectangular area on the lattice axis. After normalizing to
LB1).

In this case, normalization processing in the X direction is performed as follows.

"SX1=1000", "SX1=999", "SX1
= 0'', the rectangular area is not moved. And SX1>
0”, the rectangular area is moved to the right by |5X1|, and when “SX1<0”, the rectangular area is moved to the left |SX1
Move only ｜.

Similarly, normalization processing in the Y direction is performed as follows.

"SY1=1000", "SY1=999", "SY1
= 0'', the rectangular area is not moved. Then ``SY1
> 0”, the rectangular area is moved downward by |SY1|, and when “SY1<0”, the rectangular area is moved upward by |SY
Move only 1｜.

For example, in the case of image data as shown in FIG. 26(A), the rectangular area for "SX1=4" is moved by 4 pixels to the right (relatively, to the left of the image data). ,
At this time, since "SY1=1000", the rectangular area is not moved in the vertical direction. As a result, a figure as shown in FIG. 26(B) is obtained.

This is scanned by windows W1-X and W1-Y as shown in FIG. 14, and black dot information as shown in the shaded area of FIG. Based on this, the same process as explained in connection with FIG. 15 is performed to obtain the bottle 11 verification label code LB1 (LB
1 = DURL), thus, Figure 26 (
In the figure B), the first verification label code “LB1=101
0” is obtained.

In the case of the image data shown in FIG. 27(A),
Because “SX1=0, SY1=0”, no movement is performed in the horizontal, vertical, and vertical directions, and as a result, the first verification label code “LB1
=1111'', which is the same as the initial grid point label code.

In addition, in the case of the copying data shown in FIG. 28(A), "S
X1=-1, SY1=3", move the rectangular area by 1 pixel to the left and 3 pixels downward (relatively, move the image data by 1 pixel to the right and 3 pixels upward) Then, the above processing is performed, and as a result, the first verification label code "LB1=01", which is the same as the initial grid point label code LBL, is
11".

Furthermore, in the case of the image data shown in FIG. 29(A),
Because “SX1=-1, SY1=999”, move the rectangular area by one pixel to the left and create the first verification label code “L”.
B1=0111" is obtained.

(V) Label code generation processing section (2) Processing of the second verification processing section in (a).

In the second verification process, based on the first verification label code LB1, it is detected whether or not a line segment actually exists in the direction corresponding to the first verification label code LB1 in the vicinity of the grid point. 2 verification label code LB2. According to the first verification label code LB1, as shown in FIG. 30, the second verification window BWV0=BWV2, BWH0
~BWH2 is provided, and verification is performed using the same method as the first verification process described above. As shown in FIG. 3, the size of each of these second verification windows is determined as follows, where WD is the width between the lattice axes on both sides of the lattice point G5.

The manner in which these second verification windows are used is determined as follows. In other words, when "R=1, L=1", 1XW
Using the second verification window BWV0 of the D pixel, "R=0, L
= 1", the second verification window BWV1 of 1x (WD/2+1) pixels is used, and when "R = 1, L = 0", 1x (WD/2+1) pixels are used.
A second verification window BWV2 of (WD/2+1) pixels is used. When "U=1, D=1", the second verification window BWH0 of WD×1 pixel is used, and "U=0, D=1"
When , the second verification window BW of (WD/2+1)×1 pixel
When using H1 and "U=1, D=0", (WD/2
+1)×1 pixel second verification window BWH2 is used.

Then, each of these second verification windows is slid vertically (or horizontally) from the horizontal grid axis (or vertical grid axis) to accumulate black point information, and first all 212 verification windows are black dots. The position to be filled with the information "1" is detected. The slide width for this slide operation is up, down, left, and right.
As in the case of the first verification window, FIGS. 21(A) and (B)
is within the range of n. Then, the deviation information obtained as a result is used as second verification deviation information SX2. The above SX1 as SY2,
This is determined in the same manner as SY1.

For example, for the figure in Figure 30, "LB1=101
0" and slide it one pixel to the right from the grid axis, this second verification window BWH0 can be filled with black dots, so "SX2
= 1". However, since it is not necessary to perform a sliding operation in the vertical direction from "LB1=1010", "SY2=1000" is used to indicate this.

Further, in FIG. 31, the second verification window portions BWH0 and BWV0 are used due to "LB1=1111". At this time, the second verification window BWH0 is filled with black dots on the grid axis, so there is no need to slide it, and "SX2 = 0", but when the September 12 verification window BWV0 is slid downward by one pixel, all black dots become. Therefore, "SY2=1".

In Fig. 32, “LB1=0111” causes the second
Verification windows BW2 and BWV0 are used. At this time, when the verification windows BWH2 and BWV0 are located on the lattice axis, they all become black dots, so "SX2=0, SY2=
0".

However, in FIG. 23, the second verification window parts BWH2 and BWV0 are used due to "LB1=0111", but these second verification window parts BWH2 and BWV
Even if 0 is slid within the width n shown in FIGS. 21(A) and (B), it is not possible to make all black points,
99, SY2=999''.

Second verification deviation information SX2, SY determined as above
2, after further moving the rectangular area that captures the graphical structure in the vicinity of the lattice points and normalizing the line segments to more accurately position them on the lattice axes, the initial lattice point label code LBL and the first A second verification label code LB2 is extracted in the same manner as the verification label code LB1 was extracted.

That is, in FIG. 34(A), "SX2=1, SY2=
1000'', the rectangular area is moved one pixel to the right based on this. At this time, since "SY2=1000", the rectangular area is not moved in the vertical direction. As a result,
A figure as shown in FIG. 34(B) is obtained, and based on this, the second verification label code "LB2=1010" is extracted in the same manner as when the above-mentioned initial grid point label code LBL and first verification label code LB1 were extracted. You can

Moreover, in the figure of FIG. 35(A), "SX2=0, SY2=
1'' and moves the rectangular area downward by one pixel. As a result, a figure as shown in FIG. 35(B) is obtained, and based on this, the second verification label code "LB2=1111" can be set.

In the figure of FIG. 36(A), "SX2=0, SY2
= 0'', and as shown in Figure 36 (B), the second
You can enter the verification label code "LB2=0111".

Furthermore, in the figure of FIG. 37(A), “SX2=999,
SY2=999'', and the second verification label code ``LB2=0111'' can be entered as is, as shown in FIG. 37(B).

(VI) Label code generation processing section (2) Processing of the local shape extraction processing section in (a).

LBL determined above, SX1, SY1, LB1,
SX2, SY2, LB2, etc. express the following items.

i) Whether a line segment exists near the grid point.

ii) If a line segment exists near the lattice point, which of the four directions (up, down, left, and right) does the line segment belong to?

iii) When a line segment exists near a lattice point, how far does the line segment deviate from the lattice axis?

This local shape extraction processing is provided to capture more detailed local shape features in addition to these graphic representations, and uses the first axis bay window SW' shown in FIG. 38 to extract grid points. It expresses the possibility of whether a line segment existing in the vicinity is a line segment of a line figure or a part of a character stroke.

This local shape extraction processing is performed on the figure normalized by the processing up to the second verification processing section.

In this case, within the rectangular area on each side of the first extraction window SW',
Figure 38 (B) and Figure 39 (A) Isometric view (A) 4
Three regions R3', U3', L3', and D3' are defined, and the following processing is performed for each region R3'-D3'.

(1) As shown in FIG. 39(A), each region R3', U3
', L3', and D3' are subdivided into 1×n pixels or n
It is regarded as a set of areas of ×1 pixel. In this case, the area R
3' is divided into subdivision areas R31', R32', and R33', and area U3' is divided into subdivision areas U31', U32', and U3.
3', and area L3' is subdivided area L31'HL3.
2', L33', and area D3' is subdivided area D3.
1', D32', and D33'.

(2) In each subdivision area, (i) the number of black dot clusters (
(number of line segments) LSEG, (ii) number of black dot clusters where the number of black dots (corresponding to line width) is less than or equal to threshold LTH (number of black dot clusters that can be considered as line width) AR
Count each i.

Note that the threshold value LTH here is a threshold value of the line width determined based on the resolution of the writing instrument, the input device, and the like.

(3) Number of black dot clusters LSEG for each subdivision area,
The ambiguity flag FA and continuous arm CA are set based on the number ARi of which the length of the sunspot condensation is less than or equal to the threshold LTH.
Generate the next 2-bit information indicating M.

LSEG=1, ARi=1→FA=0, CAM=1LS
EG=0 →FA=0, CAM=0Other →FA=1
, CAM=1 (4) Take the logical sum of the information obtained in (3) above for each region R3', U3', L3', D3', and divide this into the four regions R3', U3', Each L3' and D3' is 2-bit information.

(5) The first extracted label code LB3'' shown in FIG. generate. Here, when the last 4 bits D', L', U', and R' of FIG. 39(B) are "1", it indicates that the line segment runs in that direction, and FR'-FD' means that, for example, when FR' is "1", the line segment running to the right is ambiguous;
In other words, it indicates that it is a part of a line segment of a line figure with noise added to it, or that it is a part of two characters.

When FU' is "1", it means that the line segment running upward is ambiguous, that is, the same thing as explained above for FR' exists in the upward direction, and when FL' is "1", Sometimes, the line segment running to the left is ambiguous, and when FD' is "1", the line segment running downward is ambiguous, respectively, as explained above for FR'. It also indicates that it exists. When FF' is "1", it indicates that any one of the above-mentioned FR' to FD' is "1".

Therefore, when creating the first extracted label code LB3'' based on the process of (1) to (5) above using the first extraction window SW' for the figure shown in FIG.
=000001010" is obtained. In this case, there is no ambiguity in the figure of FIG. 40, which shows that line segments run up and down.

Then, the first extracted label code L for the figure in Figure 41
If you create B3'', "LB3''=00000111
1”. In this case, there is no ambiguity, indicating that the line segments run vertically and horizontally.

Also, for the figure in Figure 42, the first extracted label code LB
If you create 3'', “LB3''=000000111
”, which shows that there is no ambiguity and that the line runs upwards and from side to side.

However, if the first extracted label code LB3'' is created for the figure in Figure 43, then "LB3''=100111
111". This means that the line segment is this first extraction window SW'
This shows that, although there are both vertical and horizontal directions, there is ambiguity in the upward and rightward directions.

Generally, it is sufficient to perform the local shape extraction process using the first extraction window SW', but if an undesired break G exists in the line segment as shown in FIG. 44(A), for example, the first extraction - In code LB3'', bit U' shown in FIG. 39(B) indicates logic "0". In order to improve this point, a second extraction window SW' having a shape shown in FIG. 44 is used. The second extraction window section SW' is the 38th extraction window section SW'.
It includes the first extraction window SW' shown in FIG.
As shown in Figure 4 (B), the areas R3゜U3', L3', D
It has 3'. Then, in the same way as the above-mentioned first extraction label code LB3' is extracted, the above-mentioned regions R3' and U
3', L3', and D3' are used to extract the second extracted label code LB3''.

FIG. 45(A)(b) shows areas R3', U3', and L3 for the image data (hatched area in the figure) shown in FIG. 44(A).
', D3' is used to extract the first extracted label code LB3'. Also, Figure 45 (C) (d)
44(A) shows a state in which a second extracted label code LB3' is extracted using regions R3', U3', L3', and D3' for the same image data shown in FIG. 44(A).

When the first extracted label code LB3' and the second extracted label code LB3' are extracted, the local shape extracted label code LB3 is determined using these two codes. When displaying each code as follows, local shape extraction label code L
B3 is determined by the following logic.

That is, first, LB3' is assigned to LB3.

Then, the following process is executed to correct LB3 obtained by substitution, and to generate information on the gap flag GF and gap direction codes GD, GL, GU, and GR shown in FIG.

By the above processing, the breakage of the line pattern as shown in FIG. 44(A) can be sufficiently absorbed. Figure 46 is similar to Figure 45 (
B) Local shape extraction label code LB3' obtained based on the code LB3' shown in the figure and the code LB3' shown in FIG.
GD, GL, GU, and GR are shown.

Note that in the extraction process in the gap direction, after the input image is normalized on the lattice axis by the second verification process described above, a projection process is executed to extract the second verification label code.
The gap direction is extracted by determining whether or not the projection results in each direction are continuous based on the projection results. Processing examples are shown in FIGS. 47 and 48.

(VII) Determination processing of collective lattice point label code (LOGLBL) in label code generation processing unit (2) (a).

According to (III) to (VI) above, initial grid point label code LBL; first verification deviation information SX1, SY1,
First verification label code LB1; second verification deviation information SX2
, SY2, the second verification label code LB2, and the local shape extraction label code LB3 can be extracted. Then, a 32-bit aggregate lattice point label code LOGLBL is determined as follows by putting together these extracted information in the form shown in FIG.

(1) When the initial lattice point label code LBL is all 0, the lattice point label code LOGLBL sets all 32 bits to "0", but when LBL is not all "0", the local shape extraction label code LB3 If all are "0", only the #16th bit of the ambiguity flag is set to "1" in LOGLBL, and the remaining 31 bits are set to "0".

(2) If the first verification deviation information SX1, SY1 and the second verification deviation information SX2, SY2 are both not "999", calculate SX and SY by the following formula.

SX=SX1+5X2 SY=SY1+SY2 However, "SX1=1000" or "SX2=1000"
When "SX=0", "SY=1000" or "S
When "Y2=1000", "SY=0" is set.

(3) Using this result, first clear LOGLBL, take the AND of the lower 4 bits of LBL, LB1, LB2, and LB3, and calculate the lower bits of LOGLBL, that is, #28 to #31 in FIG. Set to bit.

(4) Next, the absolute values of the above SX and SY |SX|, |SY|
A deviation threshold value ATH is set for , and the following processing is performed. This threshold value ATH is set to, for example, half of n, which is the maximum movement distance of the window portion, ie, n/2.

(4-1) When |SX|>ATH, set the shift flag, which is the #23 bit of LOGLBL shown in FIG. 5, to "1".

And when "SX>0", it is shifted to the right, so
Set the #22 bit of LOGLBL to "1", and when "SX<0", it is shifted to the left, so LOGL
The #20 bit of BL is set to "1".

In addition, in order to prevent problems caused by moving the rectangular area too much, a threshold value OTH that is slightly smaller than the above ATH is set and the primary processing is performed.

In the case of |SX|>OTH, if "SX>0", if the R bit of LBL is "1", it indicates that the right side of the lattice axis has been shifted too much, and the initial state is Trust the LOGLBL #31 bit to “1”
shall be.

If “SX<0”, if the L bit of LBL is “1”, then LOGL
Set #29 bit of BL to “1”.

(4-2) When |SY|>ATH, similarly to (4-1) above, set the shift flag, which is bit #23 of LOGLBL, to "1".

And when "SY>0", it is shifted downward, so
Set the #19 bit of LOGLBL to “1” and set “SY<0
”, the shift is upward, so set #21 bit to “1”
Make it.

Also, in the case of |SY|>OTH, if "SY>0", if the U bit of LBL is "1", then # of LOGLBL
Set 30 bits to “1”.

If “SY<0”, if bit D of LBL is “1”, # of LOGLBL
Set 28 bits to “1”.

(5) Then, processing in the ambiguous direction is performed.

(5-1) If the #31 bit of LOGLBL is "1" and the bit of FR of LB3 is "1", set each bit of #27 bit and #16 bit of LOGLBL to "1".

(5-2) If the #30 bit of LOGLBL is "1" and the bit of FU of LB3 is "1", set each bit of #26 bit and #16 bit of LOGLBL to "1".

(5-3) If the #29 bit of LOGLBL is "1" and the FL bit of LB3 is "1", set each bit of #25 bit and #16 bit of LOGLBL to "1".

(5-4) If the #28 bit of LOGLBL is "1" and the bit of FD of LB3 is "1", set each bit of #24 bit and #16 bit of LOGLBL to "1".

(6) First verification deviation information SX1, SY1 and second verification deviation information SX2. If both SY2 are "999", the following processing is performed.

(6-1) Clear LOGLBL, LBL, LB1
, LB2, LB3 are logically ANDed, and the LO
The lower four bits of GLBL, ie, bits #28 to #31, are set to the above-mentioned AND.

(6-2) Set #16 bit of LOGLBL to “1”,
Indicates that the line segment is ambiguous and may be a character.

(7) First verification deviation information SX1 and second verification deviation information SX
2 are both "999" and the first verification deviation information "SY1=1000", the same process as in (6) above is performed.

(8) If the first verification deviation information SX1 is "1000" and the first verification deviation information SY1 and the second verification deviation information SY2 are "999", the same process as in (6) above is performed.

(9) The first verification deviation information SX1 is “999” and the first verification deviation information SY1 and the second verification deviation information SX2
, "999" indicates that SY2 was verified.
If it is smaller, SX=SX2 SY=SY1+SY2 and the above processes (3) to (5) are performed.

(10) The first verification deviation information SX1, SY1 and the second verification deviation information SX2, SY2 are “SXl<999” and “S
Y1=999” and “SX2<999” and “SY2
<999'', SX=SXl+SX2 SY=SY2 and the processes (3) to (5) above are performed.

(11) In cases other than (1) to (10) above, the following processing is performed.

SX1≧999→SX1=0 SX2≧999→SX2=0 SY1≧999→SY1=0 SY2≧999→SY2=0 SX=SX1+SX2 SY=SY1+SY2 and set #16 bit of LOGLBL to “1”,
Processes (4) and (5) above are performed.

The expression of the aggregate lattice point label code LOGLBL generated by the processes (1) to (11) above can be summarized as follows.

(a) Whether or not a line segment exists near the lattice point. This is LO
This can be determined by the 4-way code of #28 to #31 bits of GLBL.

(b) If a line segment exists near a grid point, which direction of the four directions (left, right, top, and bottom) does that line segment belong to? Or is it part of a line figure or a character? represents the possibility that it is part of the

This is #16 bit of LOGLBL and #24 to #2
This can be determined by 7 bits, that is, an ambiguous flag and an ambiguous direction code.

(c) If a line segment exists near a lattice point, in what direction is the line segment displaced from the lattice axis? This is #19 to #23 of LOGLBL indicating the deviation flag and deviation direction code.
This can be determined by the bit.

The aggregate lattice point label code LOGLBL determined as described above is shown in FIGS. 49 to 52.

In the case of the figure shown in FIG. 49(A), its LBL, L
B1 to LB3, SX1, SY1, SX2, and SY2 are as shown in (A) to (C), and based on these,
A LOGLBL as shown in FIG. 3(D) is obtained.

For the figure in FIG. 50(A), the LOGLBL shown in FIG. 50(D) is obtained in the same way, and the same is true for FIGS. 51 and 52.

In this manner, according to the present invention, input image information can be compressed into grid point label codes, which are code information on grid points, by graphical representation of the vicinity of the grid points.

(VIII) Recognition processing for line connectors in label code generation processing unit (2) (a).

The label code generation processing unit (2) (a) checks whether the #18 bit (line connector display flag) in the illustrated code LOGLBL in FIG. 5 is set. As described above, the line connector can be thought of as a minute black circle that indicates whether or not the intersections of connection lines on the logic circuit diagram are electrically connected. In detecting the presence or absence of the black circle, it goes without saying that the existence of the connecting line is correctly discovered, and then the pattern of the image data is examined at the position corresponding to the intersection. below,
The processing mode will be described below.

A partial image of the image data stored in the image memory is
It is cut out based on the grid coordinates.

That is, as shown in FIG. 53(A), a partial image is cut out based on the grid coordinates (X0, Y0) defined by the vertical grid axis X0 and the horizontal grid axis Y0. In this state, the partial image shown in FIG. 53(B). As shown in (C), the horizontal direction (
Two types of horizontal windows HW1 and HW2 (each of which has a size of 1×m pixels) (left and right) and vertical windows VW1
, VW2 (top and bottom) (each with a size of m x 1 pixel), and move the horizontal window from top to bottom within the preset sliding range WH as shown in Figure 53. , and slide the vertical window from left to right in the slide range WV.

In the sliding process of these windows, each unit distance, for example, 1 pixel movement, there is a "1" (black dot) in the window.
, and check whether the total number exceeds a preset threshold. If it is exceeded, that position is regarded as a line part, and the detection is continued until the end of the slide range to detect the presence or absence of a line in each of the up, down, left and right directions, and its position.

The line detected in this way is a line that exists in the middle of the sliding range of the window, that is, a line that is sandwiched by non-line parts. FIG. 54 shows an example of line detection by the upper window VW1. Note that DTL indicates the detected line position.

As described above, by setting the threshold value, it is possible to detect lines that are broken, and also to relatively accurately detect the position of distorted lines.

Note that the threshold value is set to a value slightly smaller than m.

Based on the presence or absence of a line detected in this manner and its position, line position correction processing is performed.

The correction process is performed according to the logic shown in Table 1.

In other words, if there is no upward (or leftward) line and no downward (or rightward) line as in case (1), the vertical (or horizontal) line is Assume that it does not exist.

Also, as in case (2), if there is no upward (or leftward) line but there is a downward (or rightward) line, the downward (or rightward) line Assume that there is an upward (or leftward) line at the same position where . Furthermore, the case (4
), the vertical direction (
It is assumed that there is a line in the left-right direction). The reason for performing this kind of correction is to temporarily correct for lines in all four directions not being detected in cases such as T-shaped intersections or poor input image quality. .

In case (1) of Table 1 in this correction process, there is no line in the vertical or horizontal direction, so there is no need to cut out the area near the intersection, perform matching calculations, and make a determination, which will be described later. It is possible to determine that the connector does not exist. Therefore, each process described later is omitted.

In cases (2), (3), and (4) in the table above, lines in each direction (up, down, left, and right) exist or are assumed, so
Based on the output value of this correction process, a region near the intersection, which is a shape feature of the line connector, is cut out from the partial image. As shown in FIG. 55, the cutout areas are four rectangular areas C1 to C4 of size n×n, which are sandwiched by lines in four directions set based on the output value of the correction process. This cutting process is performed by cutting out a 4n2 bit pattern for the area near the intersection.

In FIG. 55, LU is an upward line, LL is a leftward line, LD is a downward line, and LR is a rightward line.

The region bit pattern thus cut out is subjected to the following matching operation with, for example, a dictionary bit pattern read from the dictionary memory.

However, in the above formula, C1 is the i-th bit of the extracted region bit pattern, Dij is the i-th bit of the j-th dictionary bit pattern, K is the number of patterns registered in the dictionary memory, and 4n2 is the above-mentioned represents the size of each pattern.

If the above matching calculation result T is less than or equal to the threshold value, it is determined that no line connector exists at that intersection, and if it is greater than or equal to the threshold value, it is determined that a line connector exists at that intersection.

[IX] Small circle pattern extraction process in circle/triangle extraction processing unit (2) (b).

The small circular pattern in the logic circuit diagram is shown in Figure 56 (A).
, (B) which means inversion, and bottle Fig. 56 (
There are also those that mean a combination such as C). Figure 56 (A
), if there is no circle pattern figure M, an AND gate,
If so, it is a NAND gate, so it is important to check that the figure M is a circle and to check the surrounding figures N to which it is connected. Surrounding figure N of circular figure M, that is, Fig. 56 (A)
In other words, the AND symbol is recognized by other means, so let's recognize whether the figure M is a circle and what kind of line segments there are in its vicinity, and learn the meaning of the circular pattern figure M. It is said that

The position of the small circular pattern drawn on the drawing is more likely to be misaligned than other line figures. To deal with this, it is necessary to flexibly respond to positional shifts so that the presence of the object is recognized no matter where it is drawn. A circular pattern of 2 mmφ that often appears in logic circuit diagrams will be described below as an example. When the resolution is 8 lines per 1 mmφ and a rectangular area of 25 x 25 pixels is used as the field of view, the diameter is 2 mmφ.
Since there is a margin of 4 pixels on each side for the circular pattern, a positional deviation of up to 0.5 mm will fall within the rectangular area of the visual field. FIG. 57 shows the relative relationship between the rectangular area 4 and the circular pattern 5 in this visual field. FIG. 57 shows a case where the circular pattern 5 is located in the center of the area 4.

Next, features are extracted to determine whether or not a circular pattern 5 exists in this area 4, but the manner of extracting features of this circular pattern is well known and will not be described here.

FIG. 58 shows the scanning mode of the area 4 for one image data and the candidate points 5' of the circular pattern 5. In FIG. 58, G5 indicates each grid point, and the grid points exist at a distance of 2 mm, and a rectangular area 4 of 25×25 pixels is scanned along these grid points.

Since the allowable displacement of the circular pattern 5 within one region 4 is 0.5 mm, the region 4 is scanned at a pitch of 1 mm. By doing so, extraction is possible no matter where the circular pattern 5 is drawn. Further, candidate points 5' for the existing position of the circular pattern 5 are 6a, 6b, 6c in FIG. 58, depending on the position where the circular pattern is extracted.
6d, and set the #17 bit of the aggregate grid point label code LOGLBL, which is the grid point position, to "1".

Due to its nature, the 2mmφ circular pattern has meaning attached to other symbols. Therefore, the position of the circular pattern is determined by determining the position where the circular pattern should be based on the recognition results of other symbols, and if the position is a candidate point, it is determined as a circular pattern.

(X) Processing of outward facing arm removal unit (3) (a).

The aggregated grid point label code LOGLBL extracted as described above generally contains undesired noise. In this process.

For example, as shown in FIG. 59, if an arm 7 (line segments such as LU, LL, LD, LR, etc. described above) exists toward the outside of the frame of the logic circuit diagram 1, this arm 7 is It is considered to be a desired noise and is canceled.

Then, any ambiguous direction code or gap direction code that may exist related to that arm is deleted.

The process for this involves comparing the aggregate grid point label code LOGLBL for each grid point with the coordinates of the grid point.

(1) If j=NY (left side), set #28 hit (L), #24 bit (FD), and #12 bit (GD) to "0".

(2) If i=1 (left side), set #29 bit (L), #25 bit (FL), and #13 bit (GL) to "0".

(3) If j=1 (upper side), set #30 bit (U), #26 bit (FU), and #14 bit (GU) to "0".

(4) If i=NX (right side), set #31 bit (R), #27 bit (FR), and #15 bit (GR) to "0".

However, NX and NY are the numbers of lattice axes in the X-axis and Y-axis directions, respectively, in FIG.

(XI) Processing of pair of processing units (3) (b).

In this process, for example, FIG. 60 (A) (b) (c
) As shown in (D), the existence of arms 7 is checked for two opposing grid points, and unpaired arms 7 are removed.

In this processing, as in the first order, unpaired arms are removed and then predetermined supplementary processing is performed.

That is, (1) Removal of unpaired arms a) LOGLBL(i,j) and LOGLBL(i+1.
When paying attention to j), #31 bit (R) of LOGLBL (i, j) is “1”.
” and the #29 bit of LOGLBL (f+1.j) (
If L) is “0” → #31 of LOGLBL(i,j)
bit (R), #27 bit (FR), #15 bit (
GR) to "0".

・The #31 bit (R) of LOGLBL (i, j) is “0”
” and the #29 bit of LOGLBL (i+1, j) (
If L) is “1” → # of LOGLBL(i+1,j)
Set the 29th bit (L), #25 bit (FL), and #13 bit (GL) to "0".

b) LOGLBL(i,j) and LOGLBL(i,j+
When paying attention to 1): #28 bit (D) of LOGLBL (i, j) is “1”
” and the #30 bit of LOGLBL (i, j+1) (
If U) is “0” → #28 of LOGLBL(i,j)
bit (D), #24 bit (FD), #12 bit (
GD) to "0".

・#28 bit (D) of LOGLBL (i, j) is “0”
” and the #30 bit of LOGLBL (i, j+1) (
If U) is “1” → # of LOGLBL(i, j+1)
Set bit 30 (U), bit #26 (Fu), and bit #14 (GU) to "0".

(2) After removing the arm, for each LOGLVBL (i, j), a) If all #28 to #31 pits (D, L, U, R) of LOGLVBL (i, j) are "0" ,→L
#11 to #15 bits (G
D, GD, GL, GU, GR), #19 to #27 bits (ZD, ZL, ZU, ZR, ZF, FD, FL, F
U, FR) to "0".

b) If all #12 to #15 bits (GD, GL, GU, GR) of LOGLBL (i, j) are "0", → set #11 pit (GD) of LOGLBL (i, j) to "0". ”.

Note that the process (2) corresponds to the process of erasing ambiguous codes and the like in response to the removal of the arms.

(XII) Processing of line breakage correction unit (3) (a).

In this process, for example, as shown in FIGS. 61(A) and 61(B), the existence of arm 7 is checked for four corresponding grid points, and the arm that should have been added is added as a missing arm to correct line breakage. . In FIG. 61, 8 represents a don't care arm in which arm 7 may or may not exist, and 9 represents an arm added by the process. That is, (1) LOGLBL(i-1,j) and LOGLBL(i
, j) and LOGLBL(j+1,j) and LOGLBL(
When paying attention to i+2, j); and.

That is, arm 9 is attached.

(2) LOGLBL(i, j-1) and LOGLBL(i
, j) and LOGLBL(i, j+1) and LOGLBL(
i, j+2); and.

That is, attach arm 9.

(XIII) Processing of deviation correction I unit (3) (d).

In this process, in general, if a shift occurs in a line segment corresponding to a certain grid point (i, j), there is a possibility that a corresponding shift will also appear at the grid point (i0+j0) in the direction of the shift. Focusing on a certain point, if there is no deviation in the lattice point label code LOGLBL in the direction of deviation, the deviation flag existing at the certain lattice point (i, j) is dropped. The process is as follows.

(1) Detect LOGLBL(i,j) whose deviation flag ZF (#23 bit) is "1".

(2) When the LOGLBL(i,j) is detected, check the deviation direction code of the LOGLBL(i,j).

And a) If #22 bit “ZR=l” then LOGLBL(i
+1, j) b) If #21 bit “ZU=1”, LOGLBL(i
, j-1) c) If #20 bit “ZL=1”, LOGLBL(j
-4, j) d) If #19 bit “ZD=1”, LOGLBL(i
, j+1).

(3) LOGLBL(i0, j0)75 of the target of interest
(all under the following conditions e) #28 to #31 bits are all “0”, f) #
A case where any of bits 28 to #31 is "1", fuzzy flag FF (#16 bit) is "0", and deviation flag ZF (#23 bit) is "0". Search for.

(4) If the case is satisfied, the above LO
#19 bit to #2 for GLBL(i,j)
Set 3 bits to “0”. That is, the deviation direction code and deviation flag are dropped.

(XIV) Processing of ambiguity correction I unit (3) (e).

In this process, a certain code LOGLBL(i, j
), the code LO of one adjacent grid point in four directions
GLBL(i+1,j), LOGLBL(i,j-1)
,LOGLBL(i-1,j),LOGLBL(i,j
+1) and correct ambiguous information. That is, (1)
L where the ambiguity flag FF (#16 bit) is “1”
Detect OGLBL(i,j).

(2) Initial settings; CNT=0, (ARM(i0)=0,
i01, 4) (3) LOGLBL (i, j) four-way code (D/L
・LOGLBL(i0, j0) in the direction corresponding to U・R)
) i.e. a) If "R=1" then LOGLBL(i+1,j
) b) If “U=1” then LOGLBL(i,j-1)c
) If “L=1” then LOGLBL(i-1,j)d) “
If D=1, check LOGLBL(i, j+1).

Let CFLG be the number of grid points to be investigated.

For example, "R=1, U=1, L=1, D=1" → "CFLG=4"
” “R=1, U=0, L=0, D=0” → “CFLG=
1'' (4) Arm in the corresponding direction of the target grid point label; e) For LOGLBL (i + 1.j), L (#2
9 bits) as ARM(1), and f) LOGLBL(i, j-1) as D(#28
bit) as ARM(2), and g) LOGLBL(i-1,j) as R(#31
bit) is ARM(3), and h) LOGLBL(i, j+1) is U(#30
bit) is ARM(4), and these ARM(1) to ARM(4) are logic "1", deviation flag #23 bit "ZF=0", and fuzzy flag #16 bit "FF=0". If there is, add "plus 1" to the above CNT and set ARM (i0) to "1".

(5) Judgment; i) No processing when CFLG≦1.

j) When CFLG=CNT (however, CFLG≧2), #16 bit (FF), #24 to #27 bit (FF) of LOGLBL (i, j)
D, FL, Fu, FR) #11 bit (GF), #12 to #15 pit (G
D, GL, GU, GR) to "0".

K) CFLG≠CNT, and (i) LOBLBL(i-1,j) and LOGLBL(i
+1, j) satisfies the condition (4) above, LOG
#16 bit (FF) of LBL (i, j) #24 to #27 bit (FD
+FL+FU+FR) Set #15 bit (GR) and #13 bit (GL) to “O”
Make it.

Also, if ARM (2) = 1, #14 bit (GU) ARM (
4) If =1, set #12 bit (GD) to "0".

Furthermore, if the 12th to 15th bits (GD, GL, GU, GR) are all "0", the #11 bit (GF) is set to "0".

(ii) LOGLBL(i,j-1) and LOGLB
When L(i, j+1) satisfies the condition (4) above,
#16 bit (FF), #24 to #27 bit (FF)
D, FL, FU, FR) #14 bit (GU), #12 bit (GD) are set to “0”
Make it.

Also.

If ARM (1) = 1, #15 bit (GR) ARM (
3) If =1, set #13 bit (GL) to "0".

Furthermore, if #12 to #15 bits (GD, GL, GU, GR) are all "0", #11 bit (GF) is set to "0".

(XV) Processing of symbol classification processing unit (4).

Lattice point label code LOG generated as above
Symbol group extraction processing is performed based on the four-way code (D, L, U, R) in the LBL.

In the recognition of logic circuit diagrams, Figures 62 (A) to (
It is necessary to identify similar symbols as shown in C). Although there are slight differences between these symbols, the input drawing that is the target of this invention is a handwritten drawing with a mixture of characters, so if we take into account the variations due to handwriting and the influence of characters, these differences at the time of current processing. It is dangerous to determine individual symbols based on slight differences.

For this reason, in this process, individual symbols are not directly extracted, but a major classification corresponding to a two-step process of major classification and minor classification is extracted. Regarding the symbols to be extracted, similar symbols as shown in FIGS. 62(A) to 62(C) are grouped in advance, and extraction is performed for each symbol group. For processing corresponding to small classification, a single gate symbol recognition processing unit (9
) will be explained in detail.

63(A) to 63(E) are graphic representations of how the four-way code (DLUR) appears at each grid point when the symbol group shown in FIG. 62(A) is drawn by hand, For example, "■" means "1011" and "." means "0000". Also, MX and MY indicate the size of the area that is thought to be affected by the shape of the symbol. Fig. 63 The reason why there are several different patterns like (A) to (E) is because the symbol contains a curved line, and due to slight variations due to handwriting etc. This is because the direction codes appear differently. This also applies to symbols containing diagonal lines as shown in Figure 62 (B). To deal with such deformed patterns, basically All of the modified patterns may be stored as dictionary patterns in, for example, a dictionary memory, but this would result in a huge number of dictionary patterns.

Therefore, in the present invention, a dictionary pattern based on the method described below is used. First, if we pay attention to one coordinate [I, B] in each of the deformed patterns in Figs. There are no line segments in the upward direction. Line segments exist in at least one direction below and to the left of the lattice points for one pattern.

Also, the coordinates of each deformation pattern in the same figure [II, B
), there are no line segments in the downward and left directions, and line segments exist and do not exist in the upward and right directions.

Therefore, in the present invention, by utilizing these conditions, FIG. 62 (
For extraction of symbol groups in A), a dictionary pattern as shown graphically in FIG. 64 is used. In the figure, small circles represent grid points, and thick lines indicate that a pattern should exist in the up, down, left, and right directions at each grid point, and no lines indicate that a pattern should not exist. A double line indicates that the existence of a pattern is not a concern (don't care), and a thin line indicates that two or more directions are necessarily specified, and it is sufficient that the pattern exists in at least one of these directions. Furthermore, MX and MY indicate the size of the dictionary pattern. By using dictionary patterns in this format, even for several types of deformed patterns shown in FIGS. 63(A) to (E), only one type of dictionary pattern shown in FIG. A) symbol group can be extracted.

In addition, the coordinates of the dictionary pattern shown in Figure 64 [III, C
) and (V, C) have double lines on the right side because of the reverse logic symbol (
This is to absorb the negative effects of small circular patterns).

FIG. 65(A) shows a four-way code part that is the target of dictionary pattern matching from the intensive grid point label code LOGLBL shown in FIG. 15 (DLU
R] corresponds to (T1T2T3T4). Also the 6th
FIG. 5(B) shows the code format per lattice point of the dictionary pattern used in the present invention.

#0 to #3 of the 9-bit division of this dictionary code DC
The bit is a pattern code (Pk), and when the symbol is handwritten, it is
Whether there is a line segment in four directions (DLUR) from the grid point is expressed as (P1P2P3P4), #4 to #7 bits are the mode code (Mk), and the above 4
This defines the mode for matching the direction code and the above pattern code, and (M1M2M3M4) is (
P1P2P3P4). This mode code is
(1) When “Mk=0”, whether Pk and Tk match or not (2) When “Mk=1” and “Pk=0”, Tk is “0”
” or “1” (don’t care) (3) “Mk=1
” and “Pk=1”, two or more directions are always specified, but it has the meaning of whether or not at least one of the directions is “Tk=1”. In addition, the symbol area flag (S) indicating whether or not the grid point itself is a matching target is set to #
It is set at the 9th bit.

FIG. 66 shows, as an example, a dictionary code corresponding to the graphic dictionary pattern of FIG. 64.

Conversion between this graphical dictionary pattern and dictionary code will be facilitated by Table 2.

Dictionary patterns using the above method are created for all symbol groups to be extracted and stored in the dictionary memory in descending order of dictionary patterns. Then, symbols are extracted from the input drawing by matching with the four-way code of each grid point obtained from the input image data. That is, in FIG. 67, the dictionary pattern of each symbol group stored in the dictionary memory and the four-way code of grids equal to the number of grids of this dictionary pattern are sequentially read out, and the dictionary code group constituting these dictionary patterns is read out. Matching is performed between the DCC and the 4-way field group TCC in correspondence with the grid points. The matching operation for this matching is performed according to the following equation. That is, now the overall evaluation value of a certain symbol group is E
If it is g.

Here, the evaluation value Wxy per I grid point takes a value from "0" to "4". In other words, if the dictionary code and the four-way code match perfectly, the minimum value is "0", and if they do not match at all, the maximum value is "4". The overall evaluation value Eg is expressed as the sum of the evaluation values of all grid points within the dictionary pattern area (represented by MX, MY). If this overall evaluation value E is "0", it means that the dictionary code and the 4-way code perfectly match at all grid points in the dictionary pattern, and the 4-way code group TCC is the dictionary code. It is determined that the symbol belongs to the symbol group of group DCC.

However, as shown in the left direction of the coordinates (Vl, A) in Figure 68 (B) and the upper direction of the coordinates (VI, A) in Figure 68 (B), deformation due to handwriting etc. on the straight part is allowed. In order to do so, an optimal threshold Tg is set for each dictionary pattern for the overall evaluation value Eg according to the size (MX, MY) of the dictionary pattern and the degree of deformation caused by handwriting, etc., and Eg≦Tg. -(8) If the relationship holds true, it is determined that it is a symbol.

In this way, matching is performed with all dictionary patterns in the dictionary memory at a certain grid point of the input drawing, and one actual symbol is determined from among those determined to be symbols. This employs the smallest Eg that satisfies equation (8). Furthermore, if there are multiple minimum Eg's, the one with the largest dictionary pattern is adopted.

As a result of symbol extraction above, the coordinates of the dictionary pattern [
Symbol recognition uses the coordinates of the input drawing corresponding to I, A), the name of the predetermined symbol group, and information on whether it completely matches the dictionary pattern, that is, whether "Eg = 0". Store in a table.

The above matching process is performed while shifting the grid point positions of the input drawing one grid at a time.

(XVI) Composite gate symbol extraction processing in the composite gate symbol recognition processing unit (5).

As mentioned above, in the logic circuit diagram to be processed by the present invention, there are symbols as shown in FIG. 62 as well as composite gate symbols CG as shown in FIG. 6. In order to process these symbols correctly, the following table is prepared. That is, a single gate as shown in FIG.
In response to extracting the symbol, a single gate symbol recognition table SPTAB as shown in FIG. 69(A) is created.
Make sure to prepare LE. The table SPTABLE
has the following columns: That is, (1) i, j... Enter the coordinate values of representative grid points for a single gate symbol. The coordinate values (i, j) of the grid points as shown in FIG. 69(B) are entered.

(2) NO, . . . the name of the extracted single gate symbol is given by number. For example, the number "27" is given to the OR circuit, the number "7" is given to the NAND circuit, and so on.

(3) SDRCT......Gives the output direction of the extracted single gate symbol. For example, for the symbols shown in FIG.
"give.

(4) SNO... When it is finally extracted as one composite gate symbol, the number that should be the single gate symbol that makes up the composite gate symbol is Given. For example, the above N
O. was extracted as an AND circuit, but if the single gate symbol constituting one composite gate symbol was originally an OR circuit, then SNO.
is set to a number corresponding to the OR circuit, and this is input into the data processing bag device. However, the SNO. is given by the extraction of the composite gate symbol, and is initially set to the value "0".

(5) CNO. ......It is given when the single gate symbol is selected as the nucleus of a composite gate symbol (such as the NAND circuit K1 shown in FIG. 70(A), which will be described later). The name of the symbol is given in the form of a number.

Initially, the value is set to "0".

(6) STFLG: Logic "1" is set when one composite gate symbol is extracted and treated as a processing target, and is initially set to the value "0".

In addition, the single gate symbol recognition table SPTABL
The role of E will be described later with reference to FIG. The table SPTABLE is prepared as described above, and a composite gate symbol dictionary memory M as shown in FIG.
PDIC is prepared.

The contents of FIG. 70(A) show the contents of the dictionary memory corresponding to one composite gate symbol CG shown in FIG. 70(B). It also has the following columns:

(7) i, j......When the coordinate values of the core single gate symbol (K1 shown in Figure 70 (B)) are (0, 0), the single Gate·
Symbols Kl, K2. K3... is given as a coordinate value or relative value. For example, for a single gate symbol K2 it is given by (-7, -11).

(8) SDRCT...... each single gate symbol K1,
The same information as in FIG. 69(A) for K2, . . . is given.

(9) NO. . . . The name for each single gate symbol K1, K2, . . . making up the composite gate symbol is given by number. Same as in FIG. 69(A).

(10) SNO. ... Each single gate symbol Kl, K2 . . . constitutes the composite gate symbol. The original number for ... is given. This role will be described later with reference to FIGS. 74 and 75.

(11) SCNT...The number of single gate symbols Kl, K2, . . . that constitute the composite gate symbol is given.

(12) CNO. ...The name of the composite gate symbol is given by number. Regarding the composite gate symbol shown in FIG. 70(B), "CNO.=121" is set.

As mentioned above, the single gate symbol recognition table SPT
ABLE and composite gate/symbol dictionary memory MPDIC
The manner in which one composite gate symbol is extracted in a state in which the gate symbols are prepared will be explained with reference to FIG. 71.

Now, there is a single gate symbol recognition table SPTABLE as shown in FIG. 71(A), and the contents of the dictionary memory MPDIC corresponding to one composite gate symbol are as shown in FIG. 71(B). Suppose it was.

It is assumed that the extracted single gate symbols are stored in the single gate symbol recognition table SPTABLE, for example, in the order of their coordinate values. Also complex gate
In the symbol dictionary memory MPDIC, a group of information (as shown in FIG. 71(B)) corresponding to each composite gate symbol is sorted in descending order of the number of the core unit gate symbol, and the same number If so, the above CNO. They are sorted in descending order of size. Further, let SPNT be the point that indicates the beginning of the single gate symbol recognition table SPTABLE, and let FPNT be the point that indicates the first piece of information in the composite gate symbol dictionary memory.

The processing is performed as follows. That is, (13) NO. for the single gate symbol described at the beginning of the table SPTABLE (assuming that the pattern is unprocessed). and SDRCT are extracted, and the NO. about the first single gate symbol (which is the core) in the first batch of information (as shown in FIG. 71) of the dictionary memory MPDIC is extracted. and SDRCT.

(14) If there is a mismatch, the next batch of information (information at the position of FFNT+1) in the dictionary memory MPDIC is compared in the same way. The same applies below.

(15) If the dictionary memory MPDIC is searched and there is no match, the next single gate symbol in the table SPTABLE (the single gate symbol at position SPNT+1) is compared in the same way.

(16) Suppose that the number of single gate symbol #12 shown in FIG. and SDRCT are shown in FIG. 71(B).
NO. of the first single gate symbol shown. and SDRC
Suppose that T matches. In this case, a single gate symbol located within a predetermined coordinate range from the coordinates (i12, j12) of the single gate symbol #12 is examined, and S
Set TFLG to logic "1". For things that are out of range,
Set STFLG to logic “0”.

(17) Then, compare this number CNT of "STFLG=1" with the SCNT shown in FIG. 71(B).

At this time, if "CNT<SCNT", it is assumed that the single gate symbol #12 is not the core of the composite gate symbol corresponding to the illustration in FIG. 71(B), and the search proceeds to the next step.

(18) If “CNT≧SCNT”, the buffer BU shown in FIG. 71(E)
Clear the dictionary buffer M shown in FIG. 71(C).
i=i12, j= in the coordinate column of #1 line of PDIC, BUF
j12, set i=i12-7, j=j12-2 in the coordinate column of line #2, and set i=i12-14, j=j12-4 in the coordinate column of line #3. In addition, the buffer BU shown in FIG. 71(E)
F is associated with "#12" in the table SPTABLE and stored.

(19) Next, # of the dictionary buffer MPDIC/BUF
It is checked whether a desired single gate symbol exists at the position corresponding to the coordinate values (i12-7, j12-2) shown in the second row. If a corresponding one, such as #10, is found among the ones whose STFLG is logical "1" on the table SPTABLE, then FIG. 71(D)
As shown in the figure, in the dictionary buffer MPDIC-BUF, the coordinate values (i12-7, j12-2) are (i10, f10)
"#10" is written into the buffer BUF shown in FIG. 71(E). In this case, the coordinate value (i12-7) and i10, and the coordinate value (j12-2)
Even if j10 and j10 do not completely match, if the difference is, for example, "2" or less in absolute value, it is determined that the difference is "2" or less in order to allow for a slight deviation. Therefore, there may be cases where more than one item is applicable.

(20) Similarly, it is assumed that the #14 single gate symbol in the table SPTABLE is extracted and "#14" is written in the buffer BUF shown in FIG. 71(E).

(21) In this state, if the number written to the buffer BUF matches the above-mentioned SCNT, it is assumed that one composite gate symbol corresponding to the information shown in FIG. 71(B) has been extracted. , FIG. 71(A) Illustrated table and SP
SNO and CNO are written in TABLE as shown by circles in the figure. Then, proceed to the next search.

The operation during this time is shown in more detail in the form of a flowchart as shown in FIGS. 72 and 73. Incidentally, the flowchart shown in FIG. 73 shows one embodiment of the processing mode for the block for extracting kernel candidates of the composite gate symbol shown in FIG. 72.

As described above, the composite gate symbol is extracted and then input to the data processing device. That is, the seventh
In the example of Figure 1, the i and j SDRs shown in Figure 71 (D)
The columns CT and SNO, SCNT and CNO, and the contents of the buffer BUF shown in FIG. 71(E) are output as information input to the data processing device.

Utilizing this fact, it becomes possible to correct erroneous extraction during single gate symbol extraction and input it to the data processing device. That is, when extracting a composite gate symbol, in the process of extracting a single gate symbol described above, for some reason, the arrow L shown in FIG.
As shown in Figure 2, it is assumed that what should originally be an OR circuit is relatively frequently extracted as an AND circuit.

In such a case, assuming that the location indicated by the arrow L cannot become an AND circuit, a dictionary as shown in FIG. 74(B) is prepared as a composite gate/symbol dictionary memory. And a single gate at arrow L.
The symbol is an AND circuit, and CNO=102 is given as the overall pattern. In this way, the CN with the pattern shown in FIG. 74(A)
It is recognized as a composite gate symbol with O=102, and when inputting to the data processing device, the single gate symbol at the position of arrow L is connected to an OR circuit (SNO
=27) and report it.

Figure 75 shows the 7th gate symbol, which is originally a composite gate symbol.
FIG. 5(A) shows a mode for dealing with the case where a single gate symbol at the position of arrow M is easily extracted as a multi-input AND circuit like a single gate symbol.

(XVII) Composite gate/symbol recognition processing unit (5)
Start point setting process.

When extracting gate symbols in general, not just compound gate symbols related to the process, the start point (terminal position) of the gate symbol should be set correctly and used for the connection line extraction process described later. be made to do. For this purpose, the start point setting process is performed as follows.

That is, when, for example, one composite gate symbol is extracted as described above, the position of the start point (connection point with the connecting line) in the symbol can be determined from the contents of the matching dictionary memory. It is known in the form of relative coordinates from the coordinates (i, j). In the present invention, based on this point, the absolute coordinates where the start point should be located are calculated, and the #0 bit on the grid point label hood LOGLBL is set to logic "1" for the grid point corresponding to the absolute coordinates.
'' is set, and logic ``1'' is set in any of bits #2 to #5, corresponding to which direction the line segment extends from the start point. Further, when an inverted logic symbol is to be added to the grid point, the #1 bit is set to logic "1".

(XVIII) Processing in the symbol area setting processing unit (6).

As described above, when symbols belonging to each group of single gate symbols or composite gate symbols are extracted at the major classification level, symbol area flags are set for grid points on the boundaries of the area occupied by each symbol. stand up. That is, the #8 bit (symbol area flag S) in the code shown in FIG. 5 is set to logic "1". In setting the symbol area flag S, the symbol area flag S is set by looking at the relative coordinates of the grid point where the symbol area flag S is logical "1" as shown in FIG. 66 from the contents of the dictionary memory that are matched with the symbol. Calculate the absolute coordinates and apply the grid point label code LOGLBL to the grid point with the absolute coordinates.
The upper #8 bit may be set to logic "1".

In this way, when attempting to set the #8 bit on the lattice point label code LOGLBL to logic "1" corresponding to the extracted symbol, logic "1" may already be set. In such a case, as described with reference to FIG. 7, there is a possibility that symbols are extracted twice, and a flag indicating this is set to SP as shown in FIG. 69(A).
Place it in the STFLG column of TABLE. FIG. 76(B) corresponds to the logic circuit diagram shown in FIG. 76(A), and shows in thick lines the manner in which the above-mentioned symbol area flag S (#8 bit) is set.

(XIX) Line segment confirmation processing in the line segment confirmation processing unit (7).

As shown in FIG.
7) Processing according to (b).

When processing handwritten drawings, it is necessary to fully consider the positional deviation of line segments. Due to this positional shift, what is originally a single line segment may be extracted twice as a lattice point label code on two parallel lattice axes.

The processing by the deviation correction unit (7) (a) estimates the state of the positional deviation of such line segments from the grid point label code, and creates a reliable grid point label code only on the grid axis that is considered to be the designer's intention. is generated. Here, the reliable grid point label code is the gap direction code (
#12 to #15 pit), deviation direction code (#19
to #22 bit) and ambiguous direction code (#2
4 to #27 bits) are all "0", and an ambiguous grid point label code is one where any bit of the gap direction code, shift direction code, or ambiguous direction code is "1". point to

Figure 77 is an example of this processing, where a pair of adjacent lattice point labels/codes with "shift directions" in opposite directions are captured and this is the result of the shift of a single line segment, as shown in Figure 77 (B). Considering this, the correction is made as shown in FIG. 77(C).

That is, the code shown in FIG. 77(B) is sequentially searched based on the four-way code to detect the axis on which the lattice to which the reliable lattice point label code is attached is present. Finally, raise that axis to a reliable grid point label code, and remove the other grid point label code. In the figure, 7-1
is an arm corresponding to a certain label code, 7-2 is an arm with a deviation flag, 10 is a deviation direction, and 11 is a line segment.

Next, the processing by the ambiguity correction II unit (7) (b) captures the ambiguity of the lattice point label code from a more global perspective and improves it to a reliable lattice point label code, which is unique to hand-drawn drawings. Remove ambiguities caused by line breaks or characters drawn close to line segments.

An ambiguous lattice point label code having a gap direction code or an ambiguous direction code of "1" is assigned to a lattice point having an incomplete form as a line segment. Naturally, an ambiguous lattice point label code is also assigned to a lattice point where a single character exists, but here, it is difficult to determine whether the ambiguity of this code information is due to local fluctuations in the line segment.
Or, give an interpretation as to whether it is caused by the characters themselves, and make corrections based on that interpretation.

FIG. 78 shows an example of this process. Specifically, first, the seventh
As shown in FIG. 8(B), an ambiguous lattice point label code is detected, and adjacent lattice point label codes located in directions along the four-way code are successively searched. In the process of this search, if a reliable lattice point label code sandwiching an ambiguous lattice point label code appears as shown in Figure 78(C), it is assumed that the ambiguity is due to local variations in line segments. Interpret and convert into reliable grid point label code.

In the figure, white circles 12 are reliable grid point label codes, black circles 13 are ambiguous grid point label codes, and 14 are ambiguous grid point label codes.
15 represents an arm having an ambiguous flag, and 15 represents an arm in which arm 7-2 having the above-mentioned deviation flag and arm 14 having the above-mentioned ambiguous flag overlap. Further, 16 represents a character, and 17 represents a line segment.

(XX) Gap/ambiguous arm processing Processing in part I (8).

Since the connection line is substantially determined up to the above processing, at that point, the four-way code (D, L , U, R).

The following processing is performed for the grid point label code LOGLBL (i, j) whose #8 bit (S) is "0".

(1) #11 bit (GF) of LOGLBL (i, j)
is "1".

(1-1) #15 bit (G
If R) is "1", #15 of LOGLBL(i,j)
Bit (GR) #31 Set bit (R) to “0”.

(1-2) #14 bit (G
If U) is “1”, #14 of LOGLBL(i,j)
Set pit (GU) #30 bit (U) to “0”.

(1-3) LOGLBL, #13 bit of (i, j) (
If GL) is "1", #1 of LOGLBL(i,j)
Set the 3rd pit (GL) and #29 pit (L) to "0".

(1-4) #12 bit (G
If D) is "1", #12 of LOGLBL(i,j)
Set bit (GD) and #28 bit (D) to “0”.

(1-5) Then, #11 bit (GF) of LOGLBL (t, j) is set to "0".

(2) #16 bit (FF) of LOGLBL (i, j)
is “1”, and (2-1) #27 bit (F
If R) is “1”, then #27 of +LOGLBL(i,j)
Bit (FR), s31 Bit K is set to "0".

(2-2) #26 bit (F
If U) is “1”, #26 of LOGLBL(i,j)
Set bit (FU) and #30 bit (U) to “0”.

(2-3) #25 bit (F
If L) is "1", #25 of LOGLBL(i,j)
Set bit (FD) and #29 bit [I] to “0”.

(2-4) #24 bit (F
If D) is "1", #24 of LOGLBL(i,j)
Set the pit (FD), #28 bit (D) to "0".

(3) For those processed in the above processes (1) and (2), a pair of processes such as those performed in the above pair of processing units (3) and (b) are executed.

(XXI) Symbol recognition processing in the single gate symbol recognition processing unit (9).

In this process, the above-mentioned symbol classification processing unit (4)
Based on the results of the major classification, the same group is further classified into smaller groups.

For the symbols extracted as described above, FIG. 69 (
A table SPTABLE as shown in A) is obtained. Under this state, the following processing is performed.

(1) Search table SPTABLE.

For example, the table shown in FIG. 69(A) is searched for a single gate symbol 18 as shown in the 79th section, and the grid point coordinates (i, j) and classification number NO. Direction SDRCT
Take out. Here, "(i8, j8), NO=13, S
DRCT=0'' is extracted.

(2) Search candidate symbol table.

As shown in FIG. 79(B), the N shown in FIG. 69(A)
A candidate symbol table 19 is provided that describes candidate symbol numbers and candidate number information corresponding to each O. For example, in the case of a single gate symbol 18 having a starting point of 3 inputs and 2 outputs as shown in the figure, the classification number is set to 13” and the direction “SDRCT=0” Candidate symbol table 1
9, three candidate symbol numbers "13", "14", "1"
5" is taken out.

(3) Symbol recognition dictionary and conversion.

Figure 79 (C), (D), and (E) are candidate symbol numbers "13", "14", and "15" extracted from Figure 79 (B).
Symbol recognition dictionaries 20-1, 20-2, 20 corresponding to
- Indicates the contents of 3. The shape of the grid point label code (i, j) corresponding to each starting point position of each left gate is shown. Also, the * mark on the outside of the margin is information indicating that the state should not exist at the starting point. The left side of the bottom column shows the size of the dictionary, and the right side shows the reverse logic symbol (2m
mφ).

These recognition dictionaries are converted by directional SDRCT.

(4) Matching between symbol recognition dictionary and grid point label code.

As shown in FIG. 79(F), symbol recognition dictionary 20-1
, 20-2, 20-3 and the small circular display flag (#17 bit) of the grid point label code and the 4-way code (#28
to bit #31), and the result is stored in the recognition buffer 21 shown in FIG. Column A of the recognition buffer 21 shows the degree of matching of four-way codes, column B shows the degree of matching of reverse logic symbols, and column C shows the reverse logic symbols seen from the position of the reverse logic symbols described in the dictionary. Indicates the degree of matching of existing positions.

(5) Judgment.

(5-1) If A+B is the maximum value, that is, the value of A+B is twice the dog size (the number on the vertical side in the diagram) of the symbol recognition dictionary, the candidate symbol is the maximum matching and is the answer of the recognition result. . This corresponds to the first candidate symbol number in the recognition buffer in FIG.

Then, the symbol number 13 is entered in the SNO column in the table SPTABLE shown in FIG. 69(A).

(5-2) If there is no item for which A+B is the maximum value, then the C column is for the maximum value, that is, among the items that match the number of reverse logic symbols described in the symbol recognition dictionary and for which A+B is greater than a certain threshold. The one with the maximum frequency is taken as the answer of the recognition result. Then, enter the symbol number in the SNO column in the table SPTABLE.

(5-3) If there is nothing that corresponds to either (5-1) or (5-2) above, set a threshold value for A+B+C and use the largest one that is greater than or equal to that value as the answer of the recognition result. do. Similarly, enter the symbol number in the SNO column.

(5-4) If there is nothing corresponding to (5-1) to (5-3) above, it is determined that it is not a symbol, and "1" is set in the STFLG column of table SPTABLE.

As described above, it is possible to give subclassifications to symbols.

(XXII) Processing of the start point setting processing section (10) This processing is substantially the same as the above processing (XVII).

(XXIII) Reverse logic symbol processing unit (11)
processing.

As described in connection with FIG. 10, this process is a process for temporarily shelving reverse logic symbols that may have an adverse effect on the process described later.

In this case, since the processing is for the grid point corresponding to the start point, the grid point label code LO where the #0 bit (Sr) is "1" and the #1 bit (S2) is "1"
The following processing is executed only for GLBL(i,j).

(1) If #5 bit (SR) of LOGLBL (i, j) is “1”, then a) #31 bit (R) of LOGLBL (i, j−i)
, #16 bit (FF) b) #29 bit of LOGLBL (i+1, j-1) (
L) #28 bit (D), #16 bit (FF) c) L
#30 bit (U) of OGLBL (i+1, j), #2
8 pinto (D) d) #30 bit of LOGLBL (i+1, j+1) (
U).

#29 bit (L), #16 bit (FF) e) LOG
Set #31 pinto (R) and #16 bit (FF) of LBL (i, j+1) to “0”.

(2) If #4 bit (SU) of LOGLBL (i, j) is “1”, then a) #30 bit (U) of LOGLBL (i-1, j)
, #16 bit (FF) b) #31 bit (FF) of LOGLBL (ii, ji)
R), #28 bit (D), #16 bit (FF) c)
#31 bit (R) of LOGLBL (i+1, j-1)
, #29 bit (L) d) #29 bit (L) of LOGLBL (i+1, j-1)
L), #28 bit (D), #16 bit (FF)e)
#30 bit (U) of LOGLBL (i+1, j), #
Set the 16 bit (FF) to “0”.

(3) If #3 bit (SL) of LOGLBL (i, j) is “1”, then a) #29 bit (R) of LOGLBL (i, j-1)
, #16 bit (FF) b) #31 bit of LOGLBL (i-1, j-1) (
R), #28 bit (D), #16 bit (FF) c)
#30 bit (U) of LOGLBL (i-1, j), #
28 bits (D) d) #31 bit of LOGLBL (i-1, j+1) (
R), #30 bit (D), #16 bit (FF) e)
#29 bit (L) of LOGLBL (i, j+1), #
Set the 16 bit (FF) to “0”.

(4) If #2 bit (SD) of LOGLBL (i, j) is “1”, then a) #28 bit of LOGLBL (i-1, j) - (D
), #16 bit (FF) b) LOGLBL, #31 bit (R) of (i-1, j+1), #30 bit (D), #16 bit (FF) c
) #31 bit (R) of LOGLBL (i, j+1),
#29 bit (L) d) #30 bit of LOGLBL (i+1, j+1) (
U), #29 bit (L), #16 bit (FF) e)
#28 bit (D) of LOGLBLB (i+1, j),
Set #16 bit (FF) to “0”.

(XXIV) Line breakage correction processing unit near the start point (12
) processing.

As described above, line breakage is likely to occur on the lattice point label code LOGLBL in the vicinity of the starting point position of the symbol. This process corrects the existence of this undesired line break.

FIG. 80(A) shows a case where the start direction is left, and therefore bits #2 to #5 of the grid point label code are "0100". Column 5 in the figure schematically shows bits #2 to #5 of the lattice point label code of the start point of the recognized logical symbol in detail, and column 4 shows the starting direction (lattice point) one lattice axis to the left. In this example, when the interval is 2 mm, bits #28 to #31 of the label code of the lattice point (2 mm to the left) are schematically shown. Case 1 indicates that the four-way code is "0100", that is, the line segment extends from the left and stops at the grid point.

In case 2, the 4-way code is "1000", that is, the line segment descends from the top and stops at the relevant grid point, and in case 3, the 4-way code is "1000", that is, the line segment goes up from the bottom and stops at the relevant grid point. It shows that However, since there is a logic symbol terminal in this part as shown in the 5th column, this broken trace is a line break caused by inaccurate drawing, and the line should originally have extended one grid interval to the right. The line segment is added as shown in the 6th and 7th columns. Specifically, the 4-way code L (#
29 bit) is set to "1", and R (#31 bit) of the 4-way code of the grid point to the left of it is set to "1".

FIG. 80(B) shows the case where the starting direction is upward, and the 5th line illustrates this, and the 4th line illustrates the 4-direction code of the grid point adjacent above it. In cases 1, 2.3, the 4-way code is “
0010'', ``0100'', and ``0001'', it is determined that the connection from the grid point to the start point is missing, and the 4-way code of the upper adjacent grid point is determined as shown in lines 6 and 7. Set D (#28 bit) to "1", and set U (#30 bit) of the 4-way code at the start point to "1". FIG. 80(C) shows the case where the starting direction is to the right, and FIG. 80(D) shows the case when the starting direction is downward. In both cases, the correction as shown in the drawings is performed in accordance with the above. Through this processing, it is possible to correct line breaks near the terminal positions of logic symbols that are likely to occur due to handwriting, and to avoid line breaks.

(XXV) Gap/ambiguous arm processing II unit (
13) Processing of (a).

This process is to perform the same process as the above process (XX) at this point in time. That is, (1) # of lattice point label code LOGLBL (i, j)
The following processing is executed for those whose 8 bits (S) are "1".

a) #16 bit (FF) of LOGLBLD (i, j)
, #11 bit (GF) is set to "0".

(2) # of grid point label code LOGLBL (i, j)
The following processing is executed for those whose 8 bits (S) are "0".

(2-1) #11 bit (G
F) is "1", then a) When the #15 bit (GR) of LOGLBL (i, j) is "1", the #15 bit (GR) of LOGLBL (i, j) is
GR) #31 bit (R) is set to “0”.

b) When #14 bit (GU) of LOGLBL (i, j) is “1”, #14 bit (GU) of LOGLBL (i, j)
GU), #30 bit (U) is set to “0”.

c) When #13 bit (GL) of LOGLBL (i, j) is “1”, #13 bit (GL) of LOGLBL (i, j)
GL), #29 bit (L) is set to “0”.

d) When #12 bit (GD) of LOGLBL (i, j) is “1”, #12 bit (GD) of LOGLBL (i, j)
GD), #28 bit (D) is set to “0”.

e) and #12 bit (G
D) is set to "0".

(2-2) #16 bit (F
If F) is "1", then a) #24 to #31 bits (FD, FL, FU, FR, D, L, U, R) of LOGLBL (i, j) are set to "0".
”.

(3) Then, perform pairwise processing on the results.

(XXVI) Line connector processing unit (13) (b
) processing.

At this point, the line connector indication bit (#1
8 bit) is set, correct this. That is, (1) If symbol area "S=1";#18 bit is set to "0".

(2) If “S=O” which is not a symbol area; (2-1
) Examine the four-way code (D, L, U, R), count the number of bits that are 1, and perform the following processing depending on the number of 2 bits.

{a) If the number≦2, set #18 bit to “0”.

b) If it is a number, set #18 bit to "1".

c) If it is a number, leave it as is (no processing)} (XXVII)
Line segment erasure processing unit (13
) Processing of (c).

Since the connection lines within the region of the composite gate symbol are a previously known pattern and do not need to be extracted, processing is performed to erase them. That is, (1) symbols that are constituent elements of the composite gate symbol are extracted from the symbol recognition table SPTABLE. That is, STFLG=0. And CN
The coordinates (i, j) and symbol number SNO of a symbol with O>100 (indicating a compound) are extracted.

(2) Take out the terminal dictionary (start point dictionary 20) according to the symbol number SNO.

(3) Compare the contents of the start point dictionary 20 and the grid point label code to detect terminal positions and connection directions where the start point information (#0 bit) is not "1". That is, the terminal position and direction of the line segment within the composite gate symbol area are detected.

(4) Trace the four-way code to the symbol area (#8 bit = 1), the start point (#0 bit = 1), or the end point (no tracking direction), and execute the following process.

(4-1) Lattice point label LOGLB reached by tracking
For L(i,j), a) When tracking to the left, #29 pit (L
) to "0".

b) When tracking upward, #28 bit (D
) to "0".

c) When tracking to the right, #31 bit (R
) to "0".

d) When tracking downward, #30 pit (U
) to "0".

e) and then the #16 bit (ambiguity flag)
Set to "0".

(XXVIII) Processing in the connection line extraction processing unit (14).

In this process, for the connection line, (i) between starting points (ii) between branching points (iii) between bending points (iv) between starting points and branching points (v) between branching points - Between bending points (vi) Tracking is performed to extract a vector between the bending point and the start point. This converts the intensive grid point label code described above to 4
This can be achieved by tracing based on the direction code, and detailed explanation of the process will be omitted.

(XXIX) Processing in the character area extraction processing unit (15).

Extracting symbols and connection lines from a drawing.

The rest are letters. In this process, those in which the ambiguity flag #16 bit (FF) is set in the grid point label code LOGLBL are extracted, and character areas are extracted. The processing is performed as follows. That is, (1) Grouping of character flags (2) Extraction of character strings (2-1) Extraction of image data (2-2) Extraction of connectivity of image data (2-3) Removal of graphic patterns and extraction of adjacent areas It consists of each stage.

The details of each of the above processes will be explained below.

(1) Grouping of character flags For example, as shown in FIG. 81(A), items that are unnecessary for the time being in the lattice point label code are temporarily deleted, and 1 bit is created as a character string flag MF, which is used as lattice point data.

Prior to processing, the character string flags MF of all grid point label codes are cleared. Also, the ambiguous flag FF can be called a character flag.

In this process, the character flag FF of the grid point label code is searched, and a processing example is shown in FIG. # Set the 7-bit string flag MF to “1”
shall be.

(2) Extracting character strings (2-1) Extracting image data n×n (
(n is the distance between grid axes) pixels are cut out into a rectangular area. This process will be explained below with reference to FIGS. 82 and 83.

FIGS. 82(A) and 82(B) show examples processed by the above-described processing. In other words, the character 24 in the hole in the figure. Line segment 25
The black circle mark 26 in the same figure (B) indicates the grid point where the character flag FF is "1", and the arm corresponding to the white circle is the logic "1"
1 schematically shows a four-way code (DLUR) with Grouping processing using character flags is shown in Figure 83 (A
), the image data in the vicinity of the lattice points is divided into groups by the character string flags 27 marked with ■. Therefore, when the image data in the vicinity of the lattice points marked with ■ is cut out by the rectangular area 28, image data 29 shown in FIG. 83(B) is extracted.

However, if the image data near the grid points is simply extracted using the grouped character flags, as shown in the figure, a complete character string may not be complete due to deletion of some characters or inclusion of other graphic images. Sometimes it is difficult to extract.

For this purpose, the following process will be introduced.

(2-2) Connectivity extraction of image data Regarding the image data cut out in the rectangular area 28 near the lattice point where the character string flag MF is "1", as shown in FIG. It is checked whether it touches the outside line 30 of the rectangular area.

(a) If all n×1 (or 1×n) areas are “0”, it is indicated as “AM(k)=1” and is non-connected.

(b) If there is "1" in the nX1 (or 1×n) area, it is indicated by "AM(k)=1" and there is a possibility of connection to the adjacent area. However, it is assumed that "k=1, 2, 3, 4".

FIG. 85 shows an example of this connectivity extraction. Among the four directions of the image data of the rectangular area 28, "AM(3)=0"
"AM(1)=1" in the other three directions, "
"AM(4)=1" is changed to "AM(2)" by the character data 31.
)=1'' indicates that image data exists due to the adjacent grid axis line 32.

(2-3) Removal of graphic pattern and cutting out adjacent area a) As a result of the connectivity extraction process of the graphic pattern removed image data in the rectangular area, “AM(k)=1
”, then “AM” in the upper direction of the image data shown in FIG.
(2) = 1'', when the lines of adjacent grating axes are shifted, there is a possibility that part of that line has entered. Therefore, if "AM(k)=1", as shown in FIG. 86, the adjacent grid point label code corresponding to that direction is checked and the next process is performed. That is, (i) If the character flag "FF=1", then "AM(k)=
0".

(ii) If {character flag “FF=0” and any of the four direction codes (DLUR) is “1”}, line pattern removal processing is performed.

(iii) If other than the above, leave as is.

The line pattern removal process within the rectangular area 28 is performed under the above conditions (ii
), but as an example, ``i=
1'' will be explained with reference to FIGS. 87 and 88.

In an area of m pixels from the outer edge of the cut out rectangular area 28, all "0" in the vertical direction (horizontal direction when "K=2, 4")
” and performs the following processing.

(iv) If there is a column in which all values are "0", black points located outside of that column are cleared and "AM(k)=0" is set.

(v) If there is no column that is all "0", leave it as is.

FIG. 87 is a schematic diagram of this process, and FIG. 88 shows the result of applying this process to the image data within the rectangular area of FIG. 85. After applying this process, "AM(k)=1" indicates that character data is continuous in that direction. In addition, in Fig. 88, the reason why "AM(1) = 0" is set even though the character data is continuous in the right direction is because the character flag FF of the grid point label code on the right side is "1". In this case, even if character continuity is not specified, the area near the grid point will be extracted in later processing.

b) Cutting out adjacent rectangular area If "AM(K)=1" for the above-mentioned rectangular area, cut out the image data near the adjacent grid point in that direction by n×n pixels, and perform the following graphic pattern removal process. Execute.

As an example, the case of "K=1" will be explained.

For the image data within the cut out rectangular area 33, as shown in FIG. to (n-th)
The number of sunspots BCNT in each row up to row w+1) is sequentially counted, and if BCNT≧TH or BCNT=0, all the blackspots from that column to the w-th column including that column are cleared. Furthermore, all black pixels from the (w+1)th column to the nth column are unconditionally cleared. Note that TH is a predetermined threshold value.

Figure 90 (5) shows the image data cut out near the adjacent lattice points in the downward direction "AM (4) = 1" of the rectangular area shown in Figure A188, and Figure 90 (B) shows the above a
) shows the results of the graphic pattern removal process shown in FIG.

By applying the above processing to all character string flags MF of "1", image data of one character string can be extracted. Figures 91 (A) and (B) are
Complete characters are extracted by removing unnecessary graphic patterns and complementing the partial patterns of the deleted characters.

(XXX) Character separation processing in the character separation/recognition processing unit (16).

The characters of the character string extracted in the above process (XXIX) are separated character by character in the two-line process to facilitate recognition processing. The process is shown below.

Here, we will show the processing procedure when it is difficult to separate the character string as it is, such as "V2B" shown in FIG. 92.

FIG. 92 shows an image in which the character strings 311 to 313 are cut out by a rectangular frame 34 that is larger in each direction by one pixel than the circumscribed rectangle. The window 35 shown in the same figure for this image
That is, a window part perpendicular to the character string direction, the length of which is equal to the vertical width of the rectangular frame 34, and one pixel wide is scanned from one end of the area within the rectangular frame, and the black dot 36 first appears in the window part 35. Detect location.

FIG. 93 shows the position where the black dot 36 is detected by the window 35 in the character strings 331 to 333 of FIG. 92.

Next, the both end positions “S” and “E” of the window portion 35 at this position are
To find the shortest path between the white pixels of ", the search area is limited to the scanning direction of the character string from the position of the window 35, that is, to the right in the figure. The character end position indicated by the "+" mark in FIG. 37 is a label indicating the limitation of the search area.In other words, the area to the right of the "+" mark is the search area.Various algorithms have been proposed for extracting the shortest path, but here we will use the This will be explained using the algorithm of (Lee).

First select one of the two points "S" and "E" determined by the above process, for example "S" as the starting point. First, select the white point directly adjacent to "S" (four-way connection). Give the label “1” to Next, a label "2" is given to the white point adjacent to the pixel given the label "1". Label "3" is given to the white point adjacent to label "2". Further, a label "1" is given to the white point adjacent to the label "3".

Repeat this below.

This procedure continues until the end point "E" is reached. Figure 94 shows the results of this labeling procedure.

Next, this label is traced in the reverse order of labeling from the end point "E" in the order of "3" → "2" → "1" → "3" in the reverse order of labeling, and reaches the start point "S". Find a path.

Although this route is the shortest route, it is not necessarily determined uniquely. In order to uniquely determine this, as shown in FIG. 95, priorities are set in the direction of reverse tracking, and tracking is performed in accordance with these priorities.

Figure 96 shows the shortest path detected by reverse tracking,
A label "+" is given to the pixel 38 on the path during reverse tracking.

Through the above processing, an area where one character in the character string exists is identified as an area surrounded by "+".

Therefore, by cutting out the black dots within this area, the image of one character is separated and extracted.

FIG. 97 shows an image of character strings 332 and 333 within the rectangular frame 34 after one character has been separated and extracted.

By repeating the above process until no black points are detected within the rectangular area, after converting pixels labeled with labels other than white points and black points to white points every time one character is separated and extracted,
Each character in a string can be separated and extracted one by one.

That is, as shown in FIG. 98, a window is set for the next character 332, a label 39 representing the limitation of the search area for the next character is determined, and the steps of FIGS. 93 to 97 are repeated.

(XXXI) Character recognition processing in the character separation/recognition processing unit (16).

In the above processing (XXX), recognition processing is performed on each character separated, but the manner of this processing is arbitrary and is conventionally known, so a description thereof will be omitted.

The process is performed as described above, and FIG. 99 shows an example hardware block diagram for performing the above process.

101 in the figure is an image input device, 102 is an image memory, 103 is a verification circuit, 104 is a reference point detection circuit, 105
is a grid point table, 106 is a grid conversion circuit (horizontal), 1
07 is a grid point label code generation circuit (horizontal), 108 is a grid conversion circuit (vertical), 109 is a grid point label code generation circuit (vertical), 110 is an address control section, 111 is a control section, 112 is a verification window setting circuit , 113 is an LBL table that sets the code LBL, and 114 is an LBL table.
B1 table, 115 is LB2 table, 116 is SX
1. SY1 table, 117 is SX2, SY2 table, 118 is an address conversion circuit, 119 is an LB3 generation circuit that generates local shape label information, 120 is an LB3 table in which local shape label information is set, 121 is a grid point label/code determination circuit, 1
22 is a label code table, and 123 is a pair processing circuit.

124 is a line pattern breakage correction circuit, 126 is a deviation correction circuit, 127 is an ambiguity correction circuit [I], 128 is a symbol dictionary, 129 is a symbol extraction circuit, 130 is a symbol recognition table, 131 is a composite gate/symbol recognition dictionary, 132 is a Composite gate symbol terminal position dictionary, 133
is a composite gate symbol recognition circuit, 134 is a single gate symbol candidate dictionary, 135 is a single gate symbol terminal position dictionary, and 136? 137 is a symbol area setting circuit, 138 is a deviation correction circuit [II), 139 is an ambiguity correction circuit [II), 14
0 is a gap/ambiguity processing circuit, 141 is a page connector recognition processing circuit, 142 is an inverse logic/symbol processing circuit, 143 is a terminal position determination circuit, 144 is a terminal vicinity line break correction circuit, 145 is a line segment extraction circuit, 146 147 is a line segment extraction preprocessing circuit, 147 is a character area extraction circuit, 148 is a line connector processing circuit, and 149 is a recognition result output device.

(E) Effects of the Invention As explained above, according to the present invention, it is possible to automatically read a handwritten logic circuit diagram and input information regarding the logic circuit diagram into a data processing device.

[Brief explanation of drawings]

FIG. 1 is an example of a logic circuit diagram processed by the present invention.
FIG. 2 is a diagram illustrating the processing range for obtaining lattice point label codes, FIG. 3 is a diagram illustrating an embodiment of the process for obtaining lattice point label codes, and FIG. 4 is an example of an implementation of the apparatus of the present invention. FIG. 5 is an example format of the lattice point label code used in the present invention, FIGS. 6 to 10 are diagrams each explaining the processing mode according to the present invention, and FIG. 12 and 13 are explanatory diagrams of an embodiment of the distortion correction process in the processing section (2) (a) shown in FIG. Figures 14 to 52 show the processing section shown in Figure 4 (
2) A diagram explaining the processing mode for obtaining the intensive grid point label code in (a), FIGS. 53 to 55 are diagrams explaining the processing mode for extracting line connectors, and FIGS. 56 to 58 59 is a diagram explaining the processing of the processing unit (3) (a) shown in FIG. 4, and FIG. 60 is the processing unit shown in FIG. 4. (3) A diagram explaining the processing of (b), FIG. 61 is a diagram explaining the processing of the processing units (3) and (6) shown in FIG. Figures 69 to 7 explaining the processing of the processing unit (4)
FIG. 6 is a diagram explaining the processing of the processing unit (5) shown in FIG.
77 and 78 are diagrams explaining the processing of the processing section (7) shown in FIG. 4, and FIG. 79 is the processing section (9) shown in FIG. 4.
FIG. 80 is a diagram explaining the processing of FIG.
12). FIGS. 81 to 91 are diagrams explaining the processing of the processing unit (15) shown in FIG. 4.
2 to 98 are diagrams for explaining the processing of the processing section (16) shown in FIG. 4, and FIG. 99 is a hardware block diagram of an embodiment that executes the configuration shown in FIG. 4. In the figure, 1 is the drawing to be processed, 2 is the processing result information, LOGL
BL represents a grid point label code, and G5 represents a grid point. Patent applicant Fujitsu Limited Patent attorney Hiroshi Mori (1 other person) Wa ``Ning:Page discontinuityg+-xsu24Fig. Figure R+-x t311
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Claims (1)

[Claims] A logic circuit diagram processing device that recognizes and extracts line figures and graphic figures from image data obtained by reading handwritten drawings that include line figures drawn along predetermined lattice axes and figures including characters. , a lattice point label code generating means for generating a lattice point label code indicating the possibility of the existence of image data near the lattice point, and a positional shift of the image data with respect to the lattice point based on the lattice point label code. A verification means for verifying, a positional deviation information holding means for holding positional deviation information obtained from the verification means, and a local shape of the image data to determine the possibility of the existence of a line figure or a drawing figure. a local shape extracting means; a local shape label holding means for retaining the local shape label information outputted from the local shape extracting means; A label code generation unit is provided that determines an intensive grid point label code that aggregates image data in the vicinity of the grid point, and separates the line figure and the drawing figure based on the intensive grid point label code. A logic circuit diagram processing device characterized in that it recognizes and extracts a logical circuit diagram.