JPS59214360A - Detecting circuit of signal input break - Google Patents

Abstract

PURPOSE:To detect the state of an input break correctly even when a clock signal extracting circuit states self-oscillation by usilizing a flip-flop circuit which inputs a receive input unipolar pulse signal and extracted from the receive signal. CONSTITUTION:When the signal input is normal, the unipolar signal 7 of the receive input is applied to an input terminal D of the flip-flop circuit 1 and the clock signal 9 extracted by the clock extracting circuit 2 is applied to an input terminal CLK, so that the input signal 7 is outputted as an output signal 10 from a terminal Q between one rise of the clock signal 9 applied to the terminal CLK to the ther rise. Some of it is branched to drive a time constant circuit 3. When, however, the signal input 7 is cut off, no signal input appears at the terminal D, so the outpt 10 from a terminal Q of the flip-flop circuit stops even if the clock signal extracting circuit 2 starts self-oscillation to generate the same signal as the clock signal at the terminal CLK. Therefore, the time constant circuit 3 does not operate and sends a signal input break detection signal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to, for example, a circuit for monitoring a PCM signal transmission device and detecting a signal input disconnection state of a receiving section.

(b) Prior Art and Problems Conventionally, a circuit having a configuration as shown in the block diagram of FIG. 1 has been used as a signal input disconnection detection circuit of a receiving section of a PCM transmission device. If the PCM input signal 6 is a unipolar pulse, it is branched as is and added to the clock signal extraction circuit 2, but if it is a bipolar pulse, it is converted to a unipolar signal 7 by the bipolar/unipolar conversion circuit 4 and then branched from the main signal path. The clock signal 9 is applied to the clock signal extraction circuit 2 and the clock signal 9 is extracted. This extracted clock signal 9 drives a monostable multi-bi break circuit 3 (hereinafter referred to as a time constant circuit) having a time constant circuit,
The time constant circuit 3 displays the state of the signal input Masatomi. If the signal input is cut off and the extraction clock 9 stops for a certain period of time, the time constant circuit 3 does not operate. In this state, the time constant circuit 3 sends out a clock signal disconnection detection signal 8. Conventionally, this clock signal disconnection detection signal 8 has been used as the PCM signal input disconnection detection signal. However, with this circuit configuration, if the Q of the tuning circuit of the clock signal extraction circuit 2 is too high or if there is a lot of reception noise, the clock signal extraction circuit 2 will self-oscillate and continue to output, so the PCM signal input will be interrupted. However, it has the disadvantage that it is not detected as a signal input disconnection.

(C) Object of the Invention An object of the present invention is to provide a circuit that can correctly detect a PCM signal input disconnection state even if the clock signal extraction circuit causes self-oscillation.

(d) Structure of the Invention In the present invention, a flip-flop circuit which inputs a received input unipolar pulse signal and a clock signal extracted from the received signal is used, and a monostable multiplier driven by the output of the flip-flop circuit is used. The circuit is configured to detect a state in which the received signal input is cut off based on the output of the high break.

(e) Embodiment of the Invention An embodiment of the invention will be described with reference to FIG. In the figure, 1 is a flip-flop circuit. When the signal input is normal, in the flip-flop circuit 1, the receiving input unipolar signal 7 is applied to the input terminal, and the input terminal CLK is applied to the flip-flop circuit 1.
The clock signal 9 extracted by the clock signal extraction circuit 2 is added to the clock signal 9 . In the flip-flop circuit 1, an input signal 7 applied to the terminal Q is output as an output signal 1° from the terminal Q from the rising edge of the clock signal 9 applied to the terminal CLK to the rising edge of the next clock. The output signal 10 of the flip-flop circuit 1 is transmitted to the subsequent circuit of the receiving section as a compact main signal pulse delayed by only a short time from the input signal 7, but a part of it is branched and drives the time constant circuit 3. . The time constant circuit 3 indicates that the signal input is in a normal state. The above is the normal operation, but if the signal type cuff is disconnected, there will be no signal input to the terminal of the flip-flop circuit 1, so even if the clock signal extraction circuit 2 self-oscillates and a clock signal is sent to the terminal CLK. Even if the same signal exists, the output 10 from the terminal Q of the flip-flop circuit stops. Therefore, time constant circuit 3
does not operate, and the time constant circuit 3 sends out a signal input interruption detection signal 8.

FIG. 3 shows another embodiment of the invention. The difference from FIG. 2 is that the bipolar/unipolar conversion circuit outputs two unipolar signals 7 and 8 corresponding to the positive and negative polarity parts of the bipolar input signal 6, and that unipolar signals 7 and 8 are input. It has two flip-flop circuits 1 and 1'. In this embodiment, the output signal 11 of the flip-flop circuit 1' is input to the time constant circuit 3. Therefore, even if the received input PCM signals are all 1'', the input signal 11 to the time constant circuit 3
becomes an alternating signal of '1.0' and will not be mistakenly detected as a signal input disconnection.

Fig. 4 is an explanatory diagram of a time constant circuit. As shown in Fig. is the data input terminal, and terminal 1 is the output terminal. The operation of this circuit is as shown in figure (b). When a pulse signal is input to input terminal A, an output rises to output terminal 1, and even if the input cabling signal disappears, this output signal remains constant for a certain period of time τ (time constant CR). lasts for a certain amount of time (determined).

As in normal conditions, if the next pulse signal comes within a certain time τ, the output from the output terminal 1 will continue. If the signal input is cut off, the pulse at input terminal A will no longer come, so the multi-by-break will not operate and will not change. In this state, a signal input disconnection is detected and a signal input disconnection detection signal 9 is sent out.

Although the above description has been made by taking the PCM signal as an example, it is also possible to detect input disconnection of other pulse signals according to the present invention.

(f) Effects of the Invention As detailed in the embodiments, according to the present invention, the drawbacks of the conventional circuit are improved, and even if the clock signal extraction circuit causes self-oscillation, it can correctly detect the state of signal input disconnection. The effect is significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional circuit, FIGS. 2 and 3 are block diagrams of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the operation of a time constant circuit. In the figure, 1 and 1' are flip-flop circuits, 2
is a clock signal extraction circuit, 3 is a time constant circuit, 4 is a bipolar/unipolar conversion circuit, 6 is a PCM input signal, 7 and 7 are unipolar signals, 8 is a signal input disconnection detection signal,
9 is a clock signal, and 10 and 11 are flip-flop output signals.

Claims (1)

[Claims] The signal input disconnection detection circuit of the receiving section of the pulse signal transmission device includes a flip-flop circuit that receives as input the received human-powered unipolar pulse signal and a clock signal extracted from the received signal, and is driven by the output of the flip-flop circuit. PCM signal input disconnection detection circuit characterized by monitoring by the output of a monostable multi-pie break