JPS6251852A - Transmission line switching device - Google Patents

Transmission line switching device

Info

Publication number
JPS6251852A
JPS6251852A JP19258785A JP19258785A JPS6251852A JP S6251852 A JPS6251852 A JP S6251852A JP 19258785 A JP19258785 A JP 19258785A JP 19258785 A JP19258785 A JP 19258785A JP S6251852 A JPS6251852 A JP S6251852A
Authority
JP
Japan
Prior art keywords
transmission line
data
terminal
counter
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19258785A
Other languages
Japanese (ja)
Inventor
Toshihiko Sasai
敏彦 笹井
Kenichi Inui
乾 健一
Fumio Kamiya
神谷 文夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Electric Equipment Corp
Original Assignee
Toshiba Electric Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Electric Equipment Corp filed Critical Toshiba Electric Equipment Corp
Priority to JP19258785A priority Critical patent/JPS6251852A/en
Publication of JPS6251852A publication Critical patent/JPS6251852A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To avoid unnecessary switching and restoring operations of transmission lines for interrupted data break on transmission lines by giving a hysteresis to data reception to restore transmission lines only for continuity of several frames. CONSTITUTION:Data of a digital signal is transmitted to an internal device 14 through a main transmission line 1 and a gate 10. As long as data is received continuously from the main transmission line 1 by a receiver 3, the overflow output of a counter 6 is not outputted from a terminal Qn. Meanwhile, a frame signal is continuously inputted to the CLK terminal of an address counter 61, and the overflow output is outputted from a terminal Qm to a set terminal S of an FF 8, and the gate 10 is held in the conductive state. If data reception from the main transmission line 1 is broken, the counter 6 is overflowed to reset the address counter 61. AS the result, a gate 11 is made conductive to receive data from an auxiliary transmission line 2. When the main transmission line is restored thereafter and is broken again after reception of m-number of frames, the gate 10 is not opened because the overflow output of the counter 61 is not outputted.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、主と副となる2つの糸路をもつ伝送路の一方
を適宜に切替えて使う伝送路切替装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transmission line switching device that appropriately switches and uses one of a transmission line having two thread lines, a main line and a sub line.

(発明の技術的背景とその問題点) 従来、この種装置の一例として第3図に表わす手段があ
る。
(Technical background of the invention and its problems) Conventionally, there is a means shown in FIG. 3 as an example of this type of device.

伝送線の1lli線等に備え、主伝送路1と副伝送路2
を設け、平常時はつねに主伝送路1を使ってデータを受
信するようにしである。
In preparation for 1lli line etc. of transmission line, main transmission line 1 and sub transmission line 2
, and data is always received using main transmission path 1 during normal times.

すなわち、3は主伝送路1の受信装置で、ここで主伝送
路1を伝送してデジタル信号のデータは、ゲート10を
経由して内部機器14へ伝送される。
That is, numeral 3 is a receiving device for the main transmission path 1, where the data of the digital signal transmitted through the main transmission path 1 is transmitted to the internal device 14 via the gate 10.

5はクロックでカウンタ6.7のCLK端子へ常時一定
聞隔でパルスを送り込んでいる。また、受信装置3が受
は入れたデータ受信信号はカウンタ6のCL K E子
とフリップフロップ8のセット端子Sへ加えられる。そ
こで、主伝送路1におけるデータ受信信号が正常である
限り、クロック5によりカウンタ6に計数された計数値
はつねにデータ受信信号によりリセットされ、カウンタ
6はオーバーフロー出力(切替信号)がQ。端子から7
リツプフロツプ8のリセット端子Rへ加えられることは
なく、フリップフロップ8はQ端子から出力し、ゲート
10を導通状態にさせている。なお、データ受信信号が
受信装置3から後方へ送出されているので、フリップフ
ロップ8はセット状態を継続する。
5 is a clock which always sends pulses at constant intervals to the CLK terminal of the counter 6.7. Further, the data reception signal accepted by the receiving device 3 is applied to the CLKE terminal of the counter 6 and the set terminal S of the flip-flop 8. Therefore, as long as the data reception signal on the main transmission line 1 is normal, the count value counted by the counter 6 by the clock 5 is always reset by the data reception signal, and the counter 6 outputs an overflow (switching signal) as Q. 7 from terminal
It is not applied to the reset terminal R of the flip-flop 8, and the flip-flop 8 outputs from the Q terminal, making the gate 10 conductive. Note that since the data reception signal is sent backward from the receiving device 3, the flip-flop 8 continues to be set.

ところで、主伝送路1が断線障碍が発生したとする。By the way, suppose that a disconnection failure occurs in the main transmission line 1.

受信装置3はデータ受信信号を後方へ送出できないので
、カウンタ6はクロック5でたちまちオーバーフローし
端子Q。から切替信号をフリップフロップ8のリセット
端子Rへ出力し、そのQ出力を停止させ、ゲート10を
不導通にさせる。
Since the receiving device 3 cannot send the data reception signal backward, the counter 6 immediately overflows at the clock 5 and the signal is sent to the terminal Q. outputs a switching signal to the reset terminal R of the flip-flop 8, stops its Q output, and makes the gate 10 non-conductive.

そのとき、副伝送路2から受信装置4に受は入れられた
データ受信信号は後方へ送られカウンタ7のCLK端子
へ入り、カウンタ7のCLK端子へのクロック5の計数
をリセットし、オーバーフローしたときの切替信号をフ
リップフロップ9のR端子へ出さないので、フリップフ
ロップ9は受信装置4からのデータ受信信号のS端子へ
の入力により出力Qを出す。
At that time, the data reception signal received by the receiving device 4 from the sub-transmission line 2 is sent backwards and enters the CLK terminal of the counter 7, which resets the count of the clock 5 to the CLK terminal of the counter 7, causing an overflow. Since the switching signal at the time is not outputted to the R terminal of the flip-flop 9, the flip-flop 9 outputs an output Q by inputting the data reception signal from the receiving device 4 to the S terminal.

ところで、フリップ7Oツブ8はQ端子からの出力を出
していないから、インバータ12には入力がなく出力が
あり、さきのフリップフロップ9からのQの出力とあわ
せてアンドゲート(論]!I!W4>13が出力し、ゲ
ート11を導通させ、副伝送路2から受は入れられるデ
ータ受信信号は後方のゲート11を介して内部機器14
へ送られる。
By the way, since the flip-flop 7O tube 8 does not output an output from the Q terminal, the inverter 12 has no input but has an output, and together with the Q output from the flip-flop 9, an AND gate (theory)!I! W4>13 outputs, gate 11 becomes conductive, and the data reception signal received from sub-transmission line 2 is sent to internal device 14 via rear gate 11.
sent to.

そして、主伝送路1の断線が回復すると、ゲート10が
ゲート11が不導通となり、平常状態に復帰する。
Then, when the disconnection of the main transmission line 1 is recovered, the gates 10 and 11 become non-conductive, and the normal state is restored.

つまり、この従来例は、伝送線断線等に備え、主伝送路
1と副伝送路2を設け、受信V;を置3.4に有効なデ
ータを受は取ったことを示すデータ受信信号によって、
カウンタ6.7をリセットする構成とし、有効なデータ
がこない時間で計測し、一定時間以上有効なデータを受
信しない場合、故障と判断して切替信号を発生し、伝送
路の切替を行う。また、送信側の不良の、場合、送信側
不良箇所をとり除いた場合、回復するようにする。
In other words, in this conventional example, a main transmission line 1 and a sub-transmission line 2 are provided in preparation for transmission line breakage, etc., and a reception V; ,
The counter 6.7 is configured to be reset, and the time is measured by the time when valid data does not arrive. If valid data is not received for a certain period of time or more, it is determined that there is a failure, a switching signal is generated, and the transmission path is switched. In addition, in the case of a defect on the transmitting side, if the defective part on the transmitting side is removed, recovery is possible.

しかしながら、この構成では、伝送線の接触不良時のよ
うな、データ断が断続的に発生する場合、切替、復帰を
くり返し、誤データとなるおそれがある。
However, with this configuration, when data interruption occurs intermittently, such as when a transmission line has a poor contact, there is a risk that switching and recovery may be repeated, resulting in erroneous data.

〔発明の目的〕[Purpose of the invention]

ここにおいて本発明は、従来例の難点を克服し、伝送路
における断続的なデータ断では切替、復帰の応動をしな
い伝送路切替装置を提供することを、その目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the conventional example and to provide a transmission line switching device that does not switch or restore in response to intermittent data interruptions in the transmission line.

〔発明の概要〕[Summary of the invention]

本発明は、上記目的を達成するために、従来手段では切
替、回復がひんばんに起る可能性があるので、その回復
条件を厳しくすることによって、 切替、回復にヒステリシスを持たせる ようにした伝送路切替装置である。
In order to achieve the above object, the present invention provides hysteresis in switching and recovery by tightening the recovery conditions, since switching and recovery may occur frequently with conventional means. This is a transmission line switching device.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例における回路構成を表わすブロック図
を第1図に示す。
FIG. 1 shows a block diagram showing a circuit configuration in an embodiment of the present invention.

すべての図面において同一符号は同一もしくは相当部分
を表わず。
The same reference numerals do not represent the same or corresponding parts in all drawings.

本発明に適用される伝送データの態様を第2図に示す。FIG. 2 shows an aspect of transmission data applied to the present invention.

nチャンネル(以下、このチャンネルをchと記す)分
のデータを送る場合に、送信側ではOchから順次1c
h、2ch・・・・・・、nChと送信し、Ochから
nchまでを1フレームとする。
When sending data for n channels (hereinafter referred to as ch), the sending side sends 1c sequentially from Och.
h, 2ch..., nCh, and one frame is from Och to nch.

アドレスは送らないため、各フレーム間にリセット信号
を送る。
Since no address is sent, a reset signal is sent between each frame.

しかして、本発明はカウンタ6.7の外に、おのおのカ
ウンタ61,71を受信613.4とフリップフロップ
8,9のセット端子Sの間に配設し、受信装置3,4に
おいて受信したフレーム信号(つまり、1フレーム毎に
設けられたリセット時間の空白を表わすリセット信号)
をカウンタ61.71のCLK端子に受は入れ、それら
カウンタ61.71のCLK端子にはカウンタ6.7の
オーバーフロー出力を導入し、かつこれらカウンタ61
.71の出力端子Qmからオーバーフロー出力が7リツ
プフロツブ8.9のセット端子Sへ与えるようにしであ
る。
Therefore, in the present invention, in addition to the counter 6.7, counters 61 and 71 are arranged between the reception device 613.4 and the set terminal S of the flip-flops 8 and 9, and the frames received by the reception devices 3 and 4 are signal (that is, a reset signal that represents a blank reset time provided for each frame)
is received at the CLK terminal of counter 61.71, the overflow output of counter 6.7 is introduced into the CLK terminal of these counters 61.71, and
.. The overflow output from the output terminal Qm of 71 is applied to the set terminal S of 7 lip flop 8.9.

カウンタ6.7の動作については、従来どうりである。The operations of counters 6 and 7 are conventional.

したがって、主伝送路1から連続して受信装置3へ受は
入れられている限り、カウンタ6のオーバーフロー出力
がQ。端子から出ることがない。
Therefore, as long as reception is continuously received from the main transmission line 1 to the receiving device 3, the overflow output of the counter 6 is Q. It never comes out from the terminal.

一方、アドレスカウンタ61はフレーム信号が継続して
そのCLK端子へ入力され、かつCLK端子へのリセッ
ト信号は入らないから、オーバーフロー出力はQIl[
子からフリップフロップ8のセット端子Sへ出力され、
ゲート10は導通状態を続ける。
On the other hand, since the frame signal is continuously input to the CLK terminal of the address counter 61 and no reset signal is input to the CLK terminal, the overflow output is QIl[
output from the child to the set terminal S of the flip-flop 8,
Gate 10 continues to be conductive.

そして、主伝送路1からのデータの受信が断つと、カウ
ンタ6はオーバーフロー出力を端子Q。
Then, when the reception of data from the main transmission line 1 is interrupted, the counter 6 sends an overflow output to the terminal Q.

から送出し、アドレスカウンタ61をリセットしてその
オーバーフロー出力は端子Q、から出ず、フリップフロ
ップ8はQ端子からの出力を送出せず、ゲート10は不
導通となり、ゲート11が導通し副伝送路2からのデー
タが内部機器14へ受は入れる。
The address counter 61 is reset and the overflow output does not come out from the terminal Q, the flip-flop 8 does not send out the output from the Q terminal, the gate 10 becomes non-conductive, and the gate 11 becomes conductive for sub-transmission. Data from path 2 is received by internal device 14.

ところで、主伝送路1が僅かの時間、たとえばデータの
フレーム数m個受は入れたとぎに、再度データの受けい
れが断たれたさいは、アドレスカウンタ61のオーバー
フロー出力はQ、端子から出ることはなく、ゲート10
は不導通、ゲート11は導通を続けるようにしである。
By the way, if the main transmission line 1 accepts m frames of data for a short period of time, and then stops accepting data again, the overflow output of the address counter 61 will be Q, and the overflow output from the terminal will not be output from the terminal. No, gate 10
is non-conductive, and gate 11 continues to be conductive.

つまりアドレスカウンタ61のオーバーフローはmより
多いnを設定している。
In other words, the overflow of the address counter 61 is set to n, which is greater than m.

すなわち、受信側では、データ数をアドレスカウンタ6
1.71でカウントすることによってアドレスを発生さ
せ、リセット信号でアドレスカウンタ61.71をリセ
ットしている。このため、アドレスカウンタ61.71
のCLK計数から、n番目データが受は取られたことを
知ることができ、送られた状態の数をカウントし、あら
かじめ定めた数のフレームが完全に送られた状態を検出
し回復を行なう。
That is, on the receiving side, the number of data is counted by the address counter 6.
An address is generated by counting 1.71, and the address counter 61.71 is reset by a reset signal. Therefore, the address counter 61.71
From the CLK count, it can be known that the nth data has been received, the number of sent states is counted, and the state in which a predetermined number of frames have been completely sent is detected and recovery is performed. .

このように、従来は1フレーム中の1つのchが連続し
て受は入れられれば回復させていたのが、本発明ではデ
ータの受は入れにヒステリシスを持たせ、数(n)フレ
ーム引き続くことにより、初めて復帰を行なうようにし
た手段をそなえる。
In this way, in the past, if one channel in one frame received data consecutively, it would recover, but in the present invention, the data data is received with hysteresis, and data is received consecutively for several (n) frames. This provides a means for making the return for the first time.

なお、副伝送路2の受信側についても全く同様な動作を
行なうことは明白である。
Note that it is clear that the receiving side of the sub-transmission line 2 performs exactly the same operation.

〔発明の効果〕〔Effect of the invention〕

かくして本発明によれば、データを受は入れる伝送路の
回復条件を厳しくすることから発生する。
Thus, according to the present invention, data reception occurs by tightening the recovery conditions of the transmission path.

不必要な伝送路の切苔、回復動作を避けることができ、
伝送データの信頼性を著しく高め、当該分野に寄与する
ところ大きい。
Unnecessary transmission line cutting and recovery operations can be avoided,
It significantly improves the reliability of transmitted data and greatly contributes to this field.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における回路構成を表わすブ
ロック図、第2図は受信する伝送データの態様図、第3
図は従来例の説明図である。 1・・・主伝送路、2・・・副伝送路、3.4・・・受
信装置、5・・・クロック、6.7.61.71・・・
カウンタ、8.9・・・フリップフロップ、10.11
・・・ゲ−l−112・・・インバータ(否定回路)、
13・・・アンドゲート(論理積回路)、14・・・内
部機器。
FIG. 1 is a block diagram showing the circuit configuration in an embodiment of the present invention, FIG. 2 is a diagram showing the mode of received transmission data, and FIG.
The figure is an explanatory diagram of a conventional example. 1... Main transmission path, 2... Sub transmission path, 3.4... Receiving device, 5... Clock, 6.7.61.71...
Counter, 8.9...Flip-flop, 10.11
...Ge-l-112...Inverter (Negation circuit),
13...AND gate (logical product circuit), 14...internal equipment.

Claims (1)

【特許請求の範囲】 1、伝送路は主、副の2系路をもち、 主伝送路において、 一定時間有効なデータを受信しない場合に故障と判断す
る手段と、 副伝送路にデータの流れを切り替える手段とを設けた故
障検出機能と、 データの一連の各チャンネルからなるフレームのフレー
ム数をカウントする手段と、 あらかじめ定めた数のフレームが伝送された場合に、故
障回復として主伝送路にデータの流れを回復させる手段
と をそなえた復帰機能と、 を具備することを特徴とする伝送路切替装置。
[Claims] 1. The transmission line has two lines, a main transmission line and a sub line, and means for determining a failure in the main transmission line when no valid data is received for a certain period of time, and a means for determining a failure in the main transmission line, and a flow of data to the sub transmission line. a means for counting the number of frames consisting of each channel in a series of data; and a means for counting the number of frames consisting of each channel of data; A transmission line switching device comprising: a recovery function having a means for restoring data flow; and a transmission line switching device.
JP19258785A 1985-08-31 1985-08-31 Transmission line switching device Pending JPS6251852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19258785A JPS6251852A (en) 1985-08-31 1985-08-31 Transmission line switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19258785A JPS6251852A (en) 1985-08-31 1985-08-31 Transmission line switching device

Publications (1)

Publication Number Publication Date
JPS6251852A true JPS6251852A (en) 1987-03-06

Family

ID=16293758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19258785A Pending JPS6251852A (en) 1985-08-31 1985-08-31 Transmission line switching device

Country Status (1)

Country Link
JP (1) JPS6251852A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344951U (en) * 1989-09-07 1991-04-25
JPH03112235A (en) * 1989-09-26 1991-05-13 Nec Corp Looping back system for optical loop type transmission line
JPH05504665A (en) * 1990-01-04 1993-07-15 コーデックス・コーポレイション Automatic data recovery for modems

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344951U (en) * 1989-09-07 1991-04-25
JPH03112235A (en) * 1989-09-26 1991-05-13 Nec Corp Looping back system for optical loop type transmission line
JPH05504665A (en) * 1990-01-04 1993-07-15 コーデックス・コーポレイション Automatic data recovery for modems

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