JPS59213119A - Manufacture of chip coil - Google Patents

Manufacture of chip coil

Info

Publication number
JPS59213119A
JPS59213119A JP8804683A JP8804683A JPS59213119A JP S59213119 A JPS59213119 A JP S59213119A JP 8804683 A JP8804683 A JP 8804683A JP 8804683 A JP8804683 A JP 8804683A JP S59213119 A JPS59213119 A JP S59213119A
Authority
JP
Japan
Prior art keywords
laminate
void layer
laminated body
forming part
layer forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8804683A
Other languages
Japanese (ja)
Inventor
Harufumi Bandai
治文 万代
Mitsuhiro Murata
充弘 村田
Kunisaburo Tomono
伴野 国三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP8804683A priority Critical patent/JPS59213119A/en
Publication of JPS59213119A publication Critical patent/JPS59213119A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • H01F41/043Printed circuit coils by thick film techniques

Abstract

PURPOSE:To obtain the chip coil of high quality factor at low cost by a method wherein a continued grooved layer forming part is laminated successively on the edge part of a laminated body, then a continued grooves are formed by performing a sintering, and a conductive part which is continued in coillike shape is formed by pressure-filling a fused low melting point metal into the grooves. CONSTITUTION:After the first groove forming part 5 has been formed on the first laminated body 1, and the second laminated body 2 which is smaller than the first laminated body 1 is stacked on the first laminated body 1 in such a manner that the edge part of the first groove forming part 5 will appear. Then, the second groove forming part 6 is formed using paste on the second laminated body 2 continuously from the edge part of the first groove forming part 5. Subsequently, the third laminated body 3 is stacked on the second laminated body 2 in such a manner that the edge part of the second groove forming part 6 will appear, and the third groove forming part 7 is formed on the third laminated body 3 in such a manner that the part 7 will be continued from the edge part of the second groove forming part 6. When the laminated bodies 1-4 stacked as above are placed in a sintering furnace and sintered at the prescribed high temperature, a coillike groove is formed on the laminated bodies 1-4. A fused low melting point metal is filled in the groove from the exposed parts 8 and 9.

Description

【発明の詳細な説明】 本発明は、チップコイルの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a chip coil.

近年、半導体素子の発展に伴って、電子機器、電子回路
の小型化、高集積化の要求力)らコイルのチップ化が進
められている。このチップコイルは、巻線型と積層型に
大別される。巻線型のチップコイルでは、Qを特徴とす
る特性は良好である力よ、巻線が露出しているために取
扱い上難点力;ある。
2. Description of the Related Art In recent years, along with the development of semiconductor devices, there has been an increase in the use of coils as chips due to the demand for smaller size and higher integration of electronic devices and electronic circuits. This chip coil is roughly divided into wire-wound type and laminated type. Wire-wound chip coils have good Q characteristics, but are difficult to handle because the windings are exposed.

この欠点を解決するために全体を樹脂モールドシたもの
が市販されているが大幅にコスト高となっている。一方
、積層型のチップコイル 料から成るペーストとAg. Pdなど75ら成る電極
ペーストを交互.に印刷した後に焼結されて製造される
が、電極材の比抵抗が高いためにQ75;悪く、また貴
金属を使用するためにコスト高となっている。
In order to solve this problem, there are products on the market that are entirely molded with resin, but the cost is significantly higher. On the other hand, a paste consisting of a laminated chip coil material and an Ag. Electrode paste consisting of 75 Pd etc. was alternately applied. Q75 is produced by printing and sintering the electrode material, but the electrode material has a high specific resistance, resulting in poor Q75 quality, and the use of precious metals increases costs.

本発明の目的は、上述の技術的課題を解決し、Q 75
E 高< 低コストのチップコイルの製造方法を提供す
ることである。
The purpose of the present invention is to solve the above-mentioned technical problems and
E. It is an object of the present invention to provide a method for manufacturing a chip coil with high cost and low cost.

以下、図面によって本発明の実施例について詳細に説明
する。第1図(a)〜(g)は本発明の一実施例の製造
工程を説明するだめの平面図であシ、第2図は完成した
チップコイルの断面図である。本発明では、先ず絶縁性
の磁性体生シートの積層体1〜4が準備される。第1の
積層体1には、焼成の際に分解または追出されるカーボ
ンなどの可燃材料若しくは可燃材料と磁性体粉末から成
るペーストによって、第1の空隙層形成部5が第1図(
b)に示されるようにスクリーン印刷などによって形成
される。この第1の空隙層形成部5は、第1の積層体1
の下部の縁に露出し、上部に至る。この下部の縁に露出
した部分8が、後述のように一方の端子となる。第1の
積層体1に第1の空隙層形成部5を形成した後、第1図
(C)に示されるように、第1の積層体1上に第1積層
体1よりも小さな第2の積層体2を、第1の空隙層形成
部5の端部が現われるように載置して積層する。次に第
1図(d)に示されるように、第1の空隙層形成部5の
端部から連続して前述のペーストによって、第2の積層
体2に第2の空隙層形成部6を形成する。その後、第1
図(θ)に示されるように第2の積層体2上に第3の積
層体3を、第2の空隙層形成部6の端部が現われるよう
に載置積層し、第1図(f)に示されるように第2の空
隙層形成部6の端部から連続するように、第3の積層体
3に第3の空隙層形成部7を形成する。この第3の空隙
層形成部7ば、第3の積層体3の上部の縁に露出し、こ
の露出した部分9が、後述のように他方の端子となる。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIGS. 1(a) to 1(g) are plan views for explaining the manufacturing process of an embodiment of the present invention, and FIG. 2 is a sectional view of a completed chip coil. In the present invention, first, laminates 1 to 4 of insulating magnetic raw sheets are prepared. In the first laminate 1, a first gap layer forming portion 5 is formed by a combustible material such as carbon, which is decomposed or expelled during firing, or a paste consisting of a combustible material and magnetic powder (see FIG. 1).
As shown in b), it is formed by screen printing or the like. This first void layer forming portion 5 is formed in the first laminate 1
exposed at the bottom edge of and extending to the top. The portion 8 exposed at the lower edge becomes one terminal as described later. After forming the first void layer forming part 5 on the first laminate 1, as shown in FIG. The laminates 2 are placed and stacked so that the end of the first void layer forming portion 5 is exposed. Next, as shown in FIG. 1(d), a second void layer forming section 6 is formed on the second laminate 2 by using the above-mentioned paste continuously from the end of the first void layer forming section 5. Form. Then the first
As shown in FIG. 1(θ), the third laminate 3 is placed and laminated on the second laminate 2 so that the end of the second void layer forming part 6 appears, and ), the third void layer forming portion 7 is formed in the third laminate 3 so as to be continuous from the end of the second void layer forming portion 6. This third void layer forming portion 7 is exposed at the upper edge of the third laminate 3, and this exposed portion 9 becomes the other terminal as described later.

その後、積層体4が、載置積層される。このようにして
載置積層された積層体1〜4ば、第1の空隙層形成部5
の露出した部分8から順次コイル状に連続して第3の空
隙層形成部7の露出した部分9に至る。第1図では、積
層体1〜4が、1枚ずつ準備された例を示したけれども
、他の実施例として、積層体1〜4は多数枚それぞれ印
刷されたものをカットして準備してもよい。また積層体
1〜4および空隙層形成部5〜7を順次印刷方式で形成
してもよい。
Thereafter, the laminate 4 is placed and laminated. The laminates 1 to 4 placed and stacked in this manner are placed in the first void layer forming portion 5.
The exposed portion 8 continues in a coiled manner to reach the exposed portion 9 of the third void layer forming portion 7 . Although FIG. 1 shows an example in which the laminates 1 to 4 are prepared one by one, in other embodiments, the laminates 1 to 4 may be prepared by cutting a large number of printed sheets. Good too. Alternatively, the laminates 1 to 4 and the void layer forming portions 5 to 7 may be sequentially formed by a printing method.

次に、載置積層された積層体1〜4を焼成炉に入れて所
定の高温度で焼成して一体的な焼結体とする。第1〜第
3の空隙層形成部5〜70ペーストは、前述のように焼
成の際に分解または追出されるので、焼成によって、第
1〜第3の空隙層形成部5〜7は、空隙層となり、積層
体1〜4には、連続したコイル状の空隙層が形成される
こ゛とになる。
Next, the laminated bodies 1 to 4 placed and stacked are placed in a firing furnace and fired at a predetermined high temperature to form an integral sintered body. The first to third void layer forming parts 5 to 70 paste are decomposed or expelled during firing as described above, so by firing, the first to third void layer forming parts 5 to 7 have no voids. Thus, a continuous coil-shaped void layer is formed in the laminates 1 to 4.

次いで、この焼結体をPb、 Snあるいはこれらの合
金寿どの低融点金属の溶融槽に浸漬し、カロ圧すること
によって、前記空隙層に前記溶融した低融点金属を第1
の積層体1の露出した部分8あるいは第3の積層体3の
露出した部分9から充填する。
Next, this sintered body is immersed in a melting tank of a low melting point metal such as Pb, Sn, or an alloy thereof, and is subjected to Calorie pressure, so that the molten low melting point metal is first introduced into the void layer.
The exposed portion 8 of the third laminate 1 or the exposed portion 9 of the third laminate 3 is filled.

その後、溶融槽から出して自然放冷することによってコ
イル状に連続した導電部が第2図に示されるように形成
される。このように本発明に従うチップコイルの製造方
法では、低融点金属によってコイル状に連続した導電部
を形成するので、コストが低く、シかもQの高いチップ
コイルを得ることができる。この連続した導電部の一方
の端子は、第1の積層体1の露出した部分8であり、他
方の端子は第3の積層体の露出した部分9である。
Thereafter, it is taken out of the melting tank and allowed to cool naturally, thereby forming a continuous conductive part in a coil shape as shown in FIG. As described above, in the method for manufacturing a chip coil according to the present invention, since a continuous conductive portion is formed in a coil shape using a low melting point metal, a chip coil with a high Q can be obtained at low cost. One terminal of this continuous conductive portion is the exposed portion 8 of the first laminate 1, and the other terminal is the exposed portion 9 of the third laminate.

このようにしてコイル状の連続した導電部か形成された
後、第2図に示されるように外部端子10.11として
たとえばAgまたはAgとPctの合金を、焼結体の両
端部に焼付けてチップコイルが製造される。本発明の他
の実施例として、外部端子10゜11は、低融点金属の
溶融槽に浸漬する前に焼付けて形成されてもよく、また
この外部端子10゜11はポーラス状であってもよい。
After a coil-shaped continuous conductive part is formed in this way, as shown in FIG. A chip coil is manufactured. As another embodiment of the present invention, the external terminals 10° 11 may be formed by baking before being immersed in a melting bath of a low melting point metal, and the external terminals 10° 11 may be porous. .

前述の実施例では、積層体は、4枚積層されたけれども
、本発明の積層枚数は所望のコイル状の導電部を形成す
るのに必要な所定の枚数であればよい。
In the above-mentioned embodiment, four laminates were laminated, but in the present invention, the number of laminates may be a predetermined number necessary to form a desired coil-shaped conductive part.

また、第3図に示すように、第1の積層体1の上に形成
した第1の空隙層形成部5の端部と第2の積層体2の第
2の空隙層形成部6の端部は第1の積層体1の上辺中間
で連結してもよい。なお図−示しないがその他の空隙層
形成部同上の連絡も同様に行ってもよい。
Further, as shown in FIG. 3, the end of the first void layer forming part 5 formed on the first laminate 1 and the end of the second void layer forming part 6 of the second laminate 2 The portions may be connected at the middle of the upper side of the first laminate 1. Although not shown in the drawings, other void layer forming portions may be connected in the same manner.

以上のように本発明によれば、積層体に順次その端部で
連続した空隙層形成部を形成して積層し、その後焼成に
よって連続した空隙層と成し、前記空隙層に溶融状態の
低融点金属を圧入、充填してコイル状に連続した導電部
を形成するので、低コストでしかもQの高いチップコイ
ルを得ることが可能となる。
As described above, according to the present invention, continuous void layer forming portions are sequentially formed in the end portions of the laminate, and then the continuous void layer is formed by firing, and the void layer has a low melting state. Since a continuous conductive portion is formed in a coil shape by press-fitting and filling the melting point metal, it is possible to obtain a chip coil with a high Q value at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(g)は本発明の一実施例の製造工程を
説明するだめの平面図、第2図は完成したチップコイル
の断面図、第3図は本発明の他の実施例の平面図である
。 1〜4・・積層体、5〜7・・空隙層形成部、10゜1
1・・外部端子。 出 願 人  株式会社村田製作所 代 理 人 弁理士岡田和秀
FIGS. 1(a) to (g) are plan views for explaining the manufacturing process of one embodiment of the present invention, FIG. 2 is a sectional view of a completed chip coil, and FIG. 3 is another embodiment of the present invention. FIG. 3 is a plan view of an example. 1-4...Laminated body, 5-7...Void layer forming part, 10°1
1...External terminal. Applicant: Murata Manufacturing Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁性の複数枚の積層体を準備し、第1の積層体
には焼成によって空隙層となる第1の空隙層形成部を形
成し、前記第1の積層体上に第2の積層体を、前記第1
の空隙層形成部の端部が現われるように載置積層し、前
記端部から連続するように第2の空隙層形成部を第2の
積層体に形成し、前記第2の積層体上に第3の積層体を
、前記第2の空隙層形成部の端部が現われるように載置
積層し、前記第2の空隙層形成部の端部から連続するよ
うに第3の空隙層形成部を第3の積層体に形成し、以下
、順次このようにして空隙形成部がその端部でコイル状
に連続するように所定枚数の積層体を積層し、前記積層
された積層体を焼成して前記、第1.第2.第3・・の
空隙層形成部を空隙層と成し、前記空隙層に溶融状態の
低融点金属を充填してコイル状の連続した導電部を形成
することを特徴とするチップコイルの製造方法。
(1) Prepare a plurality of insulating laminates, form a first void layer forming portion that becomes a void layer by firing in the first laminate, and form a second void layer on the first laminate. The laminate is placed in the first
The second laminate is placed and laminated so that the end of the void layer forming part of the second laminate is exposed, a second void layer forming part is formed in the second laminate so as to be continuous from the end, and the second laminate is placed on the second laminate. The third laminate is placed and stacked so that the end of the second void layer forming section is exposed, and a third void layer forming section is placed so as to be continuous from the end of the second void layer forming section. A predetermined number of laminates are sequentially stacked in this manner so that the void forming portion continues in a coil shape at the end thereof, and the stacked laminate is fired. See above, No. 1. Second. A method for producing a chip coil, characterized in that the third void layer forming portion is formed as a void layer, and the void layer is filled with a molten low melting point metal to form a continuous conductive portion in a coil shape. .
JP8804683A 1983-05-18 1983-05-18 Manufacture of chip coil Pending JPS59213119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8804683A JPS59213119A (en) 1983-05-18 1983-05-18 Manufacture of chip coil

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8804683A JPS59213119A (en) 1983-05-18 1983-05-18 Manufacture of chip coil

Publications (1)

Publication Number Publication Date
JPS59213119A true JPS59213119A (en) 1984-12-03

Family

ID=13931886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8804683A Pending JPS59213119A (en) 1983-05-18 1983-05-18 Manufacture of chip coil

Country Status (1)

Country Link
JP (1) JPS59213119A (en)

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