JPS59211325A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS59211325A
JPS59211325A JP58086851A JP8685183A JPS59211325A JP S59211325 A JPS59211325 A JP S59211325A JP 58086851 A JP58086851 A JP 58086851A JP 8685183 A JP8685183 A JP 8685183A JP S59211325 A JPS59211325 A JP S59211325A
Authority
JP
Japan
Prior art keywords
transistor
voltage
emitter
load
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58086851A
Other languages
Japanese (ja)
Inventor
Seiichiro Kikuyama
菊山　誠一郎
Hiroto Motoyoshi
元吉　啓登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58086851A priority Critical patent/JPS59211325A/en
Priority to AT0161084A priority patent/ATA161084A/en
Priority to DE19843418191 priority patent/DE3418191A1/en
Publication of JPS59211325A publication Critical patent/JPS59211325A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/66—Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/03—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
    • H02P7/04—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors by means of a H-bridge circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To minimize the occupied area of an integrated circuit and to switch a current of a DC load by controlling an emitter voltage of two transistors (TRs) of an output control circuit of a current switching circuit so as to change a load voltage. CONSTITUTION:An operational amplifier 19 is constituted as a voltage follower and controls an emitter voltage of TRs 6, 7 by a voltage from a control input terminal 20. In bringing input terminals 8, 9 as an L level and input terminals 10, 11 as an H level, TRs 6, 1, 4 are turned on and TRs 7, 2, 3 are turned off. A voltage VA of a terminal A becomes VA=V19-VEC6-VBE1(Vcc>VA), where VEC6 is an emitter-collector voltage of the TR6, VBE1 is a base-emitter voltage of the TR1 and V19 is an emitter voltage of the TRs 6, 7. In taking an input voltage of an input terminal 20 as V20, the relation of VA=V19-VEC6- VBE1 is attained, and since V20=V19, the relation of VA=V20-VEC6-VBE1 is obtained and a voltage applied to a DC load 5 is controlled by the voltage V20.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は直流負荷の電流の方向を切換えるようにした半
導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device that switches the direction of current in a DC load.

〔従来技術〕[Prior art]

第１図はこのような従来装置の回路図である。 FIG. 1 is a circuit diagram of such a conventional device.

図において、（１）　、　（２）　、　（３）　、　（
４）は各々第１．第２゜第３．第４のトランジスタとし
てのＮＰＮ　）ランジスタ、（５）はＮＰＮ　）ランジ
スタ（２）のコレクタのＡ端子とＮＰＮ　）ランジスタ
（４）のコレクタのＢ端子間に接続された直流負荷、（
６）及び（７）は第５及び第６のトランジスタとしての
ＰＮＰ　）ランジスタ、（８）　、　（９）。In the figure, (1), (2), (3), (
4) are respectively 1st. 2nd゜3rd. NPN) transistor as the fourth transistor, (5) is an NPN) DC load connected between the A terminal of the collector of NPN) transistor (2) and the B terminal of the collector of NPN) transistor (4),
6) and (7) are PNP transistors as the fifth and sixth transistors, (8) and (9).

（１０）、０υは直流負荷（５）に流れる電流の方向を
切換えるための入力端子、圓は第１の電源端子、Ｑ３１
は接地端子である。０勺はＰＮＰ　）ラゾジスタ、０５
１はＮＰＮトランジスタ、ａＱは直流負荷（５）の端子
電圧を制御するための制御入力端子、ａηは第２の電源
端子であって、これらで出力電圧制御回路を構成してお
り、この回路は他の回路と別の半導体装置として設けら
れている。(10), 0υ is the input terminal for switching the direction of the current flowing to the DC load (5), circle is the first power supply terminal, Q31
is the ground terminal. 0 is PNP) La Zodista, 05
1 is an NPN transistor, aQ is a control input terminal for controlling the terminal voltage of the DC load (5), aη is a second power supply terminal, and these constitute an output voltage control circuit. It is provided as a semiconductor device separate from other circuits.

上記構成において、先ず入力端子（８）　、　（９）を
ｒＬＪレベルに、入力端子Ｑｌ、（ｌυをｒＨＪレベル
にすると、ＰＮＰ　）ランジスタ（６）　、　ＮＰＮ　
）ランジスタ（１）　、　（４）がオンとな、ｉＥ、Ｐ
ＮＰ）ランジスタ（力、　ＮＰＮ　トランジスタ（２）
、（３）がオフとなる。したがって直流負荷（５）には
Ａ端子からＢ端子方向の電流が流れる。このときの制御
入力端子Ｑ６）の電圧をＶ１６　、　ＮＰＮ　）ランジ
スタロ９０ベース・エミッタ間電圧Ｖｓｒｔｌｓ　、　
ＮＰＮトランジスタ（１）のコレクタ・エミッタ間電圧
を■ＣＩＥＩ　＋第１の電源端子ａりの電圧をｖｃｃｔ
ｚとすると、Ａ端子の電圧（ＶＡ）は、 ＶＡ　＝Ｖ１６−ＶＢＫＩ５−Ｖｃｙｔ、ｘ　（ただし
ＶＯＣｌ２　〉Ｖｌｅ　）とな’）　、ＶＢＫＩ５　＋
　ｖＯＥＩの負荷電流による変化を無視すれば、ｖＡは
Ｖ１６で制御できることになシ、Ｂ端子の電圧（Ｖ　Ｂ
）の負荷電流による変化を無視すれば、直流負荷（５）
にかかる電圧（ＶＡＢ　）　Ｉｄ　Ｖ１６で制御できる
ことになる。In the above configuration, first input terminals (8) and (9) are set to rLJ level, and input terminals Ql and (PNP when lυ are set to rHJ level) transistors (6) and NPN
) When transistors (1) and (4) are on, iE, P
NP) transistor (power, NPN transistor (2)
, (3) are turned off. Therefore, a current flows from the A terminal to the B terminal in the DC load (5). At this time, the voltage of the control input terminal Q6) is V16, NPN) the voltage between the base and emitter of Ranjistaro 90 Vsrtls,
The collector-emitter voltage of the NPN transistor (1) is CIEI + the voltage at the first power supply terminal a is vcct
z, the voltage (VA) at the A terminal is VA = V16 - VBKI5 - Vcyt, x (where VOCl2 > Vle ), VBKI5 +
If we ignore the change in vOEI due to the load current, vA can be controlled by V16, and the voltage at the B terminal (V B
), if changes due to load current are ignored, DC load (5)
This means that the voltage applied to (VAB) Id can be controlled by V16.

又、入力端子（８）　、　（９）をｒＨＪレベルに、入
力端子００）、（ｌυをｒＬＪレベルにした場合、ＶＡ
Ｂが逆極性となるが、前述と同じようにＶ１６で制御で
きることは明らかである。Also, if input terminals (8) and (9) are set to rHJ level and input terminals 00) and (lυ are set to rLJ level, VA
Although B has the opposite polarity, it is clear that it can be controlled by V16 in the same way as described above.

しかしながら従来のこのような装置では、直流負荷（５
）に大きな電流を流す場合、ＰＮＰ）ランジスタａ優に
も大きい電流容量が必要となり、集積回路上の専有面積
が増大するため、とのような出力電圧制御回路の集積回
路化は不可能となる。　−〔発明の概要〕 本発明はこのような従来装置の問題点に鑑みてなされた
もので、集積回路の専有面積の増大を最小限におさえて
、出力電圧を制御できるようにするため、第５トランジ
スタと、第６のトランジスタのエミッタ電圧を制御する
ようにしたものである。However, in conventional devices like this, the DC load (5
), a much larger current capacity is required than the PNP transistor a, which increases the area occupied on the integrated circuit, making it impossible to integrate the output voltage control circuit such as . - [Summary of the Invention] The present invention has been made in view of the problems of the conventional device. The emitter voltages of the fifth transistor and the sixth transistor are controlled.

〔発明の実施例〕[Embodiments of the invention]

第２図は本発明の一実施例を示す半導体集積回路装置の
回路である。第２図において第１図と同一部分は同一符
号を用いて説明は省略する。FIG. 2 shows a circuit of a semiconductor integrated circuit device showing one embodiment of the present invention. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted.

０１Ｇは電源電圧（Ｖｃｏ　）が印加される電源端子、
ａ９は出力が反転入力端子に接続されると共にＰＮＰ　
）ランジスタ（６）　、　（７）のエミッタに接続され
、非反転入力端子が制御入力端子−に接続された演算増
幅回路である。01G is a power supply terminal to which the power supply voltage (Vco) is applied;
a9 has its output connected to the inverting input terminal and is PNP
) is an operational amplifier circuit connected to the emitters of transistors (6) and (7), and whose non-inverting input terminal is connected to the control input terminal.

なお、ｌ’？ＪＩ？）ランジスタ（６）　、　（７）及
び演算増幅回路ａ！Ｊで出力電圧制御回路を構成してい
る。Furthermore, l'? JI? ) transistors (6), (7) and operational amplifier circuit a! J constitutes an output voltage control circuit.

上記構成において、演算増幅回路ａ譜はボルテージフォ
ロワに構成され、制御入力端子−からの電圧によｆｉ　
ＰＮＰ　）ランジスタ（６）　、　（力のエミッタ電圧
を制御する。先ず、従来例と同様に入力端子（８）。In the above configuration, the operational amplifier circuit a is configured as a voltage follower, and is controlled by the voltage from the control input terminal.
PNP) transistor (6), (controls the emitter voltage of the force. First, the input terminal (8) as in the conventional example.

（９）を「Ｌ」レベルに、入力端子（１１）、（ＩＩ）
を「Ｈ」レベルにすると、ＰＮＰトランジスタ（６）と
ＮＰＮ　）ランジスタ（１）　、　（４）がオンとなり
、ＰＮＰ　）ランジスタ（７）とＮＰＮ）ランジスタ（
２）、（３）がオフとなる。このときのＰＮＰ　）ラン
ジスタ（６）のエミッタ・コレクタ間電圧をＶ　ＫＯ２
とし、ＮＰＮ　）ランジスタ（１）のベース・エミッタ
間電圧をＶＢＫＩとし、ＰＮＰ　）ランジスタ（６）、
（力のエミッタ電圧をＶ１９とし、演算増幅回路ａ９の
制御入力端子−の入力電圧をＶ２Ｏとすると、Ａ端子の
電圧（ＶＡ）は ＶＡ　＝Ｖ１９−Ｖｘｃｅ　−ＶＢｎ　（タタＬＶｃａ
〉ＶＡ）となシ、また演算増幅回路Ｑ！Ｊがボルテージ
フォロワに構成されているので、 Ｖ２Ｏ”Ｖ１９ ・°・■ム＝Ｖ２０　　Ｖｌｅ６−ＶＢＫＩとなり、前
記従来装置と同様に負荷電流による変化を無視すれば、
直流負荷（５）にかかる電圧（ＶＡＢ）はＶ２Ｏで制御
できることになる。(9) to "L" level, input terminals (11), (II)
When set to "H" level, PNP transistor (6) and NPN) transistors (1) and (4) turn on, and PNP) transistor (7) and NPN) transistor (
2) and (3) are turned off. At this time, the emitter-collector voltage of the PNP transistor (6) is VKO2
Let the base-emitter voltage of the NPN ) transistor (1) be VBKI, and the PNP ) transistor (6),
(If the emitter voltage of the power is V19 and the input voltage of the control input terminal of the operational amplifier circuit a9 is V2O, then the voltage (VA) of the A terminal is VA = V19 - Vxce - VBn (Tata LVca
〉VA) and operational amplifier circuit Q! Since J is configured as a voltage follower, V2O"V19 ・°・■mu=V20 Vle6-VBKI, and if we ignore the change due to load current as in the conventional device,
The voltage (VAB) applied to the DC load (5) can be controlled by V2O.

ここでＮＰＮ　）ランジスタ（１）　、　（３）の電流
増幅率をｈＦｘ、ベース電流をＩＢ＋直流負荷（５）を
流れる出力負荷電流をＩＯとすると、演算増幅回路任９
の出力電流１１９は、 １１９　＝　ＩＢ　＝　Ｉｏ／ｈｒｘ となシ、従来装置に比べ出力電圧制御回路の電流は１／
ｈＦＫ　　で済むことになる。Here, if the current amplification factor of NPN) transistors (1) and (3) is hFx, the base current is IB + the output load current flowing through the DC load (5) is IO, then the operational amplifier circuit function is 9.
The output current 119 is 119 = IB = Io/hrx, and compared to the conventional device, the output voltage control circuit current is 1/
hFK will do.

したがって、出力電圧制御回路の集積回路上の専有面積
が小さくできるため、このような回路の集積回路化が可
能となる。Therefore, the area occupied by the output voltage control circuit on the integrated circuit can be reduced, making it possible to integrate such a circuit.

なお、この実施例では第１〜第４のトランジスタをＮＰ
Ｎ　）う／ジスタで構成したが、ＰＮＰ）ランジスタを
用いても同様な効果がある。Note that in this embodiment, the first to fourth transistors are NP.
Although it is constructed using N) transistors, the same effect can be obtained by using PNP) transistors.

さらに、出力電圧制御回路の素子数を増加して使用でき
るようになり、上記のような演算増幅回路ａ９や様々の
出力電圧制御方法が可能となる。Furthermore, it becomes possible to use an increased number of elements in the output voltage control circuit, making it possible to use the operational amplifier circuit a9 as described above and various output voltage control methods.

なお、上記実施例では、出力電圧制御回路として、演算
増幅回路（１９を用いたボルテージ７オロワ回路を使用
しているが、他の回路構成、または従来の出力電圧制御
回路等を使用する場合、また第５、第６のトランジスタ
のエミッタを直接駆動する場合も同様の効果が期待でき
る。In the above embodiment, a voltage 7 lower circuit using an operational amplifier circuit (19) is used as the output voltage control circuit, but if another circuit configuration or a conventional output voltage control circuit is used, Further, similar effects can be expected when the emitters of the fifth and sixth transistors are directly driven.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、出力電圧制御回路
の第５のトランジスタと第６のトランジスタのエミッタ
電圧を制御して負荷電圧を変えるようにしたので、集積
回路の専有面積を最小限におさえることができ、直流負
荷の電流の方向を切換えるようにした半導体集積回路装
置の集積回路化が可能となる効果がある。As explained above, according to the present invention, the load voltage is changed by controlling the emitter voltage of the fifth transistor and the sixth transistor of the output voltage control circuit, so that the area occupied by the integrated circuit can be minimized. This has the effect of making it possible to integrate a semiconductor integrated circuit device in which the direction of the current in a DC load is switched.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来装置の回路図、第２図は本発明の一実施例
による半導体集積回路装置の回路図である。 （１）　、（２）　、（３）　、（４）・・・・ＮＰＮ
　）ランジスタ、（５）・・・・直流負荷、（６）　、
　（７）・・・・ＰＮＰ　）ランジスタ、（８）、（９
１訓、（１１１−−−−入力端子、贈・・・・接地端子
、Ｑ８１・・・・電源端子、■・・・・演算増幅回路、
翰・・・・制御入力端子。 なお、各図中、同一符号は同一または相当部分を示すも
のとする。 代理人　大岩増雄FIG. 1 is a circuit diagram of a conventional device, and FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. (1) , (2) , (3) , (4)...NPN
) transistor, (5)...DC load, (6),
(7)...PNP) transistor, (8), (9
1 lesson, (111---input terminal, gift...ground terminal, Q81...power supply terminal, ■...operational amplifier circuit,
Kan: Control input terminal. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (3)

【特許請求の範囲】[Claims] （１）コレクタが電源に接続された第１のトランジスタ
と、コレクタが第１のトランジスタのエミッタに接続さ
れ、エミッタが接地された第２のトランジスタと、コレ
クタが電源に接続された第３のトランジスタと、コレク
タが第３のトランジスタのエミッタに接続され、エミッ
タが接地された第４のトランジスタと、第２のトランジ
スタのコレクタと第４のトランジスタのコレクタの間に
接続された直流負荷と、コレクタを第１のトランジスタ
のベースに接続した第５のトランジスタと、コレクタが
第３のトランジスタのベースに接続され、エミッタが第
５のトランジスタのエミッタに接続された第６のトラン
ジスタとからなシ、第２のトランジスタ、第４のトラン
ジスタ、第５のトランジスタ、第６のトランジスタのベ
ース電圧を制御して前記直流負荷の電流の方向を切換え
ると共Ｋ。 第５のトランジスタと第６のトランジスタのエミッタ電
圧を制御して前記直流負荷にかかる電圧を制御すること
を特徴とする半導体集積回路装置。(1) A first transistor whose collector is connected to a power supply, a second transistor whose collector is connected to the emitter of the first transistor and whose emitter is grounded, and a third transistor whose collector is connected to a power supply. a fourth transistor whose collector is connected to the emitter of the third transistor and whose emitter is grounded; a DC load connected between the collector of the second transistor and the collector of the fourth transistor; a fifth transistor connected to the base of the first transistor; a sixth transistor whose collector is connected to the base of the third transistor and whose emitter is connected to the emitter of the fifth transistor; The base voltages of the transistor, the fourth transistor, the fifth transistor, and the sixth transistor are controlled to switch the direction of the current of the DC load. A semiconductor integrated circuit device, characterized in that a voltage applied to the DC load is controlled by controlling emitter voltages of a fifth transistor and a sixth transistor. （２）第５のトランジスタと第６の、トランジスタのエ
ミッタを制御する手段として演算増幅回路を用いること
を特徴とする特許請求の範囲第１項記載の半導体集積回
路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein an operational amplifier circuit is used as means for controlling the emitters of the fifth transistor and the sixth transistor. （３）演算増幅回路はボルテージフォロワを構成してい
ることを特徴とする特許請求の範囲第２項記載の半導体
集積回路装置。(3) The semiconductor integrated circuit device according to claim 2, wherein the operational amplifier circuit constitutes a voltage follower.
JP58086851A 1983-05-16 1983-05-16 Semiconductor integrated circuit device Pending JPS59211325A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58086851A JPS59211325A (en) 1983-05-16 1983-05-16 Semiconductor integrated circuit device
AT0161084A ATA161084A (en) 1983-05-16 1984-05-16 CIRCUIT TO SWITCH THE CURRENT DIRECTION TO A DC CONSUMER
DE19843418191 DE3418191A1 (en) 1983-05-16 1984-05-16 Circuit for reversing the current direction to a DC load

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58086851A JPS59211325A (en) 1983-05-16 1983-05-16 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS59211325A true JPS59211325A (en) 1984-11-30

Family

ID=13898311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58086851A Pending JPS59211325A (en) 1983-05-16 1983-05-16 Semiconductor integrated circuit device

Country Status (3)

Country Link
JP (1) JPS59211325A (en)
AT (1) ATA161084A (en)
DE (1) DE3418191A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4031398A1 (en) * 1990-10-04 1992-04-09 Digital Equipment Int METHOD AND CIRCUIT FOR CONTROLLING THE ROTATIONAL SPEED OF A DC MOTOR

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1098996B (en) * 1957-09-30 1961-02-09 Licentia Gmbh Electronic switching arrangement capable of reversing current direction
GB1017459A (en) * 1963-03-22 1966-01-19 Ampex Improvements in or relating to motor drive circuits
US3260912A (en) * 1963-06-19 1966-07-12 Gen Motors Corp Power amplifier employing pulse duration modulation
US3496441A (en) * 1965-10-05 1970-02-17 Licentia Gmbh D.c. motor control circuit
FR2180144A5 (en) * 1972-04-10 1973-11-23 Honeywell Bull

Also Published As

Publication number Publication date
ATA161084A (en) 1987-04-15
DE3418191A1 (en) 1984-11-22
DE3418191C2 (en) 1989-10-05

Similar Documents

Publication Publication Date Title
JPS6369306A (en) Current mirror circuit
JPS59211325A (en) Semiconductor integrated circuit device
JPH01223807A (en) Output circuit
JPH0498683A (en) Differential amplifier circuit
JP2647725B2 (en) Voltage comparator
JP3097593B2 (en) Semiconductor device
JP2597314Y2 (en) Constant current circuit
JPH0749541Y2 (en) Transistor switch circuit
JP3862550B2 (en) Emitter follower circuit
KR970063907A (en) Variable gain amplifier circuit
JPH04157919A (en) Current switch type control circuit
JPS6221310A (en) Current constant multiple circuit
JPS62220010A (en) Switching current generating circuit
JPH04208709A (en) Semiconductor device for voltage comparison
JPH09260971A (en) Differential amplifier
JPS63231514A (en) Semiconductor integrated circuit
JPS6231219A (en) Logic circuit
JPH03237809A (en) Amplifier circuit
JPH04158609A (en) Current mirror circuit
JPH0675017U (en) Reference power supply circuit
JPS60119108A (en) Generating circuit of inflow/outflow current
JPS6323418A (en) Output circuit
JPH0661823A (en) Switch circuit
JPS5814610A (en) Push-pull amplifier
JPH0236792A (en) Induction load driving circuit