JPS59210599A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make the scale of an additional circuit small and facilitate the test of bit error correcting operation for a memory cell by using a data inputting circuit of initial setting and a data control circuit for test in common with a writing control circuit to a memory cell and inspection cell. CONSTITUTION:When a control signal given to a control terminal EC is ''O'', input data from an input terminal DI are transmitted as they are to all of reading buses BMI, BHI, BVI at the time of writing and initial setting is made possible. When the control signal given to a control terminal EC is ''I'', input data from the input terminal DI are transmitted to a writing bus BMI at the time of writing. Updated data are transmitted to writing buses BHI, BVI basing on the result of comparison of input data and memory cell information before writing so that horizontal parity and vertical parity obtain even number parity. That is, self correcting type memory can be realized by performing ordinary random access.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to
Haneno I4 (related to memory) has a built-in error correction circuit that automatically detects and corrects bit errors caused by

As a semiconductor memory device that has a built-in circuit that automatically corrects errors in pin 1 that occur in semiconductor memory, the horizontal and vertical parity check method has been made one-dimensional, and multiple memory cells connected to the same word line are used. By applying this method in units of units, a semiconductor memory device which can correct errors from pin 1 to white was first proposed in Japanese Patent Application No. 11-11 in Japanese Patent Application No. 56-37223.

Fig. 1 is an explanatory diagram of its principle, and shows 16 data bits arranged in 71 to 7 of 4x4 (corresponding horizontal parity bit 1 is indicated by A, and vertical) < 1 note bit 1 is indicated by B.
Not shown. Note that in this example, even parity is used as the value.

Any 1-bit error among the 16 data bits causes the validity of the horizontal group C that yields from 1 to 1, and the validity of the vertical group D to ~ Investigate using information,
By avoiding parity errors, they can be detected and corrected.

Here, the above-mentioned 1G data bits, parity bits l-A, and parity bits l-1-3 are shown in FIG.
If moved as indicated by the dotted line, this two-dimensional matrix can be converted into a one-dimensional matrix as shown in Figure 1B.1 This one-dimensional 71 helix is shown in Figure 1C. , J.
, if you avoid corresponding to the memory cells connected to each word line in the memory, if there is an error in one memory cell information among Hi716 memory cell information, the lower 8 checks lx that store valid information By checking the parity of the horizontal group and vertical group to which each memory cell of C1 belongs using the information in the
J- can do it.

In such a self-correcting memory, it is necessary to initialize the information of all memory cells and all test cells in order to correctly correct errors in pin 1.

In other words, if the configuration uses even parity, as in the example shown in FIG. 111] requires a configurable data input circuit.

Furthermore, in such a self-correcting memory, it is necessary to test the bit error correction operation for all memory cells at the time of shipment.

For this purpose, a data control circuit is required to control the information of the memory cells and test cells so that errors can be generated in a 1-bit 1 manner in all memory cells in a pseudo manner.

The present invention provides that the data input circuit for the initial setting required in the self-correcting memory and the data control circuit for the test I are combined with the m-input control circuit for the memory cells and test cells. Can be used for both purposes, 1. H4 formation is right, and for this reason,
By reducing the size of the additional circuit, it is possible to easily pass Test 1 of the 1-bit error correction operation for the memory cell. Obviously there would be a lot of yelling.

FIG. 2 shows an embodiment of a semiconductor memory according to the present invention,
A write control circuit for memory cells and test cells has a circuit configuration that serves as a data input circuit for initial setting and a data control circuit for tests 1 to 1.

In FIG. 2, φ indicates a correction signal; 1. Also, BMO
and BMI respectively accept the read bus from the memory, the memory cell that has been acknowledged, and the write bus to the memory cell that has been acknowledged.

Furthermore, B l-10 and B l-1r 4゜1 indicate the read bus from the horizontal valid cell (test cell) to which the 't1 addressed memory cell relates, and the read bus thereto, respectively. 0 Furthermore, BVO and BVI are vertical parity cells (test cells) to which the addressed memory cells relate, respectively.
A read bus from and a bus connected to it are shown.

Moreover, EX1, 2, 3, and 4 are JJI logical OR gates.

Roughly speaking, D○ is the output terminal, DI is the input *1): child, EC
indicate the control i11 terminals, respectively.

In addition, SW 1 and SW 2 C control 9 U 1: I
This is a switching circuit controlled by the Ec(7) signal.

A specific example of the switching circuit SW 1 (shown in FIG. 3, in which the control signal directed to the control terminal EC is 21i (
j display]''', the input signal applied to the input terminal J terminal 2 is transmitted to the output terminal 1, and the control signal applied to the control terminal EC is transmitted to the output terminal ``o'' and the output terminal. An input signal applied to input terminal 3 is transmitted to terminal 1.
'i'i'i right.

Further, the switching circuit SW2, like the switching circuit SW1, has control terminals EC1, LJ and I″L.
When the control signal given to the child EC is 1111+, the signal given to the input terminal 2' is transmitted to the output terminal 1', and control 9;1: When the control signal given to the child EC is "o", the signal given to the input terminal 2' The structure through which the signal applied to the input terminal 2' is transmitted is shown below.

In the switch circuits SW1 and SW2, Ql and Q
2 indicates a MISI transistor, and ■ indicates an inverter.

According to the semiconductor memory according to the present invention shown in FIG. 2, the following operation can be obtained.

The operation will be explained below separately when the control signal applied to the control terminal FC is "o" and when it is "1".

If the control signal applied to the control terminal FC is '°O'', then the control signal is used as an initial signal for the purpose of preventing the formation of an even barrier in the memory cell and the test cell, for example, while the correction circuit is activated. Used for settings.

If the control signal given to the control terminal "C" is 'O' (well, at the time of writing, 95', output bus BN (l, B l
-11 and 93° of B V T:: jllshi,
On the lotus, there is an input terminal, and the human data from I is 4,
Therefore, the same data can be written to the addressed memory cell and its horizontal parity cells and vertical parity cells (test cells).

Therefore, for example, when using even parity, if you write PaO"' to all memory cells by initial setting, the same information "o" will be written to all test cells, and even parity will be established. [first time] setting is possible.

If the control input given to the control terminal EC is "1", it is the same as the case of a normal random address that operates the correction circuit, and when writing, the write bus BMI is
Input data from the input terminal DI is transmitted to the write buses BHI and BV, but the input data is input to the write buses BHI and BV so that their horizontal parity and vertical parity are even parity.
Based on the comparison results with the memory cell information before dispatch, the update information is communicated.

This makes it possible to update the horizontal parity cell information and the vertical parity cell information (41) and to correct a 1-bit error during reading.

Therefore, according to the semiconductor memory according to the present invention shown in FIG. 2, first, the control signal applied to the control signal terminal EC is
o" and write "o" to all memory cells to perform initial setting. Next, set the control signal given to the control signal terminal EC to "1" and perform normal random access. , a self-correcting memory can be realized.

By the way, as shown in Fig. 2, the present invention (Koyoru Cliff '9 (4\
If memory is used, it is possible to perform human error correction for all memory cells using a general-purpose method (without testing I can bring it.

FIG. 4 shows the test sequence.

In Figure 4, N is all memory cells, so W○ is II OI
I dispatch operation \V1 is ``'1'' write operation, RO is ``'0''
``Read 111 operation, R1 represents ``''1'' read operation,
Also, horizontal lll1! I stands for event quil, (time).

The read operation R writes '1' to the control terminal EC, and the write operation W gives 'O' information to [C.

The operation of P1 to Error Correction by this test button will be explained using the 4×4 virtual memory array shown in FIG. 5 (corresponding to FIG. 1A).

First, as shown in FIG. 5A, all memory cells (2'1
Write ″.

In this case, since the control signal given to the control ◇v1;
+ is written.

Since writing to the test cell can be performed simultaneously with writing to the memory cell, the pattern length for this is N.

Next, when the upper left memory cell is read, its horizontal parity and vertical parity are both odd parities, and a parity error occurs, so the self-correction circuit causes the upper left memory cell 1j "" information to be falsely read. “’1” to 110
It becomes I+ and compared with the expected value +1011, J:
to self] from “1” to l O+” by the positive circuit.
] Correct operation can be checked.

Next, as shown in FIG. 5B, the upper left memory cell is
When , "o" is written to both the first horizontal validity cell from the top and the first vertical parity cell from the left. Since this write operation can be performed simultaneously, the des1-pattern length for this is 1.

Therefore, next time when the upper left memory cell is read, its horizontal parity and vertical parity both become odd parities, and a barrier error occurs, so the self-correction circuit changes the value from '0' of the upper left memory cell to '0'. j to 1″
l Correct operation can be checked.

Next, as shown in FIG. 5C, if ``1'' is stored in the memory cell on the left -1-, the state returns to △ in FIG. Ai is also 1.

Therefore, as shown in Figure 5, E and [: 1, by changing the memory cell address to be accessed by 1 per hit and performing the same check/7, "o" for all memory cells is set. Both bit error correction operations from ``1'' to 110 I+ can be made to des1.

As mentioned above, as shown in FIG.
It is possible to completely test the bit error correction operation of the self-forming system using a short test pattern of vertical parity.

In the above 1l-3, we explained the case where the horizontal/vertical parity system uses even parity, but if the tongue f'i9 parity 2e is used, J to replace "(')" and "'1",
Therefore, exactly the same des1~ as described above is possible.

As mentioned above, by using the semiconductor memory of the present invention shown in FIG.
The advantage of this is that you can easily check the correct operation of pin 1 to error d1 for all memory cells using a general-purpose memory desk, since it can be shifted in the same way as the R/W input signal of a normal memory. ”ru.

Further, according to the present invention, in a semiconductor memory having a built-in J normal function in pin 1, the control circuit (1) for the memory cell or test cell is a data input circuit for initial 1yJ setting and a test Since the configuration also serves as a data control circuit for the 2D, it has the advantage of being able to reduce the size of the input/output circuit and easily test the bit error correction function.

In addition, a complete test of the correct operation of each memory cell with λ・j pins 1~τ1; Death in a3 to Death 1 [~Advantage that leads to improved reliability of Song and Song Dynasty -〇, (74t I1'?Jru.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of a self-correcting semiconductor memory used to explain the present invention. FIG. 2 is a system diagram showing an example of the yield angle of a semiconductor memory according to the present invention. Figure 3 is a 1° diagram showing the switching circuit. FIG.
It is a dimensional drawing of the Death L-batan secret. FIG. 5 is a diagram for explaining the same. Applicant: Nippon Telegraph and Telephone Public Corporation Broom 11:'A So------j Figure 1 B C'@3 Figure 4 □7

Claims (1)

[Scope of Claims] It includes a plurality of memory cells for storing information and a plurality of test cells for storing test information for testing the information stored in the memory cells, A semiconductor memory having means for correcting bit errors by a horizontal/vertical parity check method, comprising: 7) a write control circuit for controlling writing of information in the memory cell and the test module; , as a circuit means that combines the above three circuits: a data control circuit that initializes the information of the test cell, and a data control circuit that makes it possible to test the P1 error correction operation for each memory cell. A self-correction circuit is installed, and without operating the self-correction circuit, data that satisfies the opposite parity of the parity used in the horizontal perpendicular parity method is written to all memory cells and all test cells. , Next, the self-correction circuit is operated to read the memory cell at a certain address and check the correction operation. Next, the self-correction circuit is operated, and f, the memory cell at the address and its related items are inspected. Write reverse data to the cell, and then make the self-correction circuit perform E)3 to read the memory cell at the address and perform correction operations Ml, n)X. Semiconductor memory characterized by