JPS5920969B2 - Object surface flaw detection device - Google Patents

Object surface flaw detection device

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Publication number
JPS5920969B2
JPS5920969B2 JP557677A JP557677A JPS5920969B2 JP S5920969 B2 JPS5920969 B2 JP S5920969B2 JP 557677 A JP557677 A JP 557677A JP 557677 A JP557677 A JP 557677A JP S5920969 B2 JPS5920969 B2 JP S5920969B2
Authority
JP
Japan
Prior art keywords
output signal
preliminary measurement
signal
measurement
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP557677A
Other languages
Japanese (ja)
Other versions
JPS5390984A (en
Inventor
俊彦 大道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koyo Seiko Co Ltd
Original Assignee
Koyo Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koyo Seiko Co Ltd filed Critical Koyo Seiko Co Ltd
Priority to JP557677A priority Critical patent/JPS5920969B2/en
Publication of JPS5390984A publication Critical patent/JPS5390984A/en
Publication of JPS5920969B2 publication Critical patent/JPS5920969B2/en
Expired legal-status Critical Current

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  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Length Measuring Devices By Optical Means (AREA)

Description

【発明の詳細な説明】 本発明は物体の表面きず検出装置に関する。[Detailed description of the invention] The present invention relates to an apparatus for detecting surface flaws on an object.

従来、機械加工された金属表面のきずを検知する装置と
して、被検査表面に光を当てその反射光を集光する光学
系構成部分と、集光された光を光電変換し予備計測時に
求めた平均的な明るさに比例した量を欠陥検出レベルに
使用して実計測時で良否の判定を行う電気系構成部分と
からなるものがある。上記装置の概略は第1図に示すご
とく、破線括弧内のアナログゲート1、積分回路2、レ
ベル調節器3で予備計測が行われ、該レベル調節器3の
出力信号fを欠陥検出レベルとしてコンパレーター4で
光電子増倍管5からの出力信号aと比較する。この従来
装置は被検査物の表面の研摩程度などに差を有するもの
を混合して検査する場合には第2図にイ,口,ハと区別
して示されるように、被検査物の明るさに応じて種々の
レベルに信号があられれるが、予備計測時に求めた平均
的明るさに比例して欠陥検出レベルfも移動するので、
イ,口等いかなるレベルに信号fがあつても欠陥信号L
を捕える。また、全体が暗いハの信号であつても欠陥信
号Lがなければ良品の信号として判定出来るなどの特徴
を有しているので一応の成果をもたらすことができる。
しかし例えば第3図に示されるような良面Jに薄いサビ
様で比較的広い範囲にでる欠陥Kの場合、第4図の如く
欠陥信号Lは良面信号Mのあいだに長い時間にわたつて
出るがあまり暗い方向に出ない。したがつて予備計測時
の被検査物全面の平均的明るさは、この種の欠陥で暗い
方向に押し上げられ、その結果欠陥信号Lが捕えられに
くい方向へ欠陥検出レベルfが移動する。それゆえ信号
の平均レベルから欠陥信号の小さい欠陥を検出する目的
で欠陥検出レベルfを信号に接近させると、たとえ良品
であつても、その表面の微細構造のために欠陥検出レベ
ルfに達する信号が発生する事があり、誤つて不良品と
判定される不都合が起こる。本発明は上述の欠点を解消
した欠陥検出精度の高い物体の表面きず検出装置を提供
することを目的とするものである。
Traditionally, devices for detecting flaws on machined metal surfaces include an optical system component that shines light on the surface to be inspected and collects the reflected light, and a photoelectric converter of the focused light to obtain the results during preliminary measurements. Some devices include electrical system components that use an amount proportional to average brightness as a defect detection level to determine pass/fail during actual measurement. The outline of the above device is shown in Fig. 1. Preliminary measurements are performed by an analog gate 1, an integrating circuit 2, and a level adjuster 3, which are shown in broken line parentheses, and the output signal f of the level adjuster 3 is used as a defect detection level for a comparator. The output signal a from the photomultiplier tube 5 is compared with the output signal a from the photomultiplier tube 5. When inspecting a mixture of objects with different levels of surface polishing, this conventional device uses a The signal will be at various levels depending on the situation, but the defect detection level f will also move in proportion to the average brightness determined during preliminary measurement.
B, No matter what level the signal f is, the defective signal L
capture. Furthermore, even if the signal is entirely dark C, it can be determined as a good signal if there is no defective signal L, so that it can produce some results.
However, for example, in the case of a thin rust-like defect K appearing on a relatively wide area on a good surface J as shown in FIG. It comes out, but it doesn't come out in a very dark direction. Therefore, the average brightness of the entire surface of the object to be inspected during preliminary measurement is pushed up in the dark direction due to this type of defect, and as a result, the defect detection level f moves in a direction where it is difficult to capture the defect signal L. Therefore, if the defect detection level f approaches the signal for the purpose of detecting a defect with a small defect signal from the average level of the signal, even if it is a good product, the signal will reach the defect detection level f due to the fine structure of its surface. This may occur, resulting in the inconvenience of incorrectly determining that the product is defective. SUMMARY OF THE INVENTION An object of the present invention is to provide a surface flaw detection device for an object that eliminates the above-mentioned drawbacks and has high defect detection accuracy.

実施例について説明すれば、本発明は第5,6図に示す
如く、被検査物Xを位置N1から位置N2へ送るプツシ
ヤ一6と位置N2で被検査物Xを回転させるロール7を
設け、位置N2の被検査物Xが位置N1から移動してき
た被検査物Xに押し出され後述する電気系構成部分から
の指示で良品方向0、不良品方向Pに振り分けられる選
別扉8を有する排出シユート9とからなる附帯部分と、
第7図に示す如く被検査物Xを照明する光源10を被検
査物Xの上部に設置し、該光源10と被検査物xとの間
に集光レンズ11及びハーフミラー12を取付け、該ハ
ーフミラー12に導かれる被検査物Xの表面反射光を結
像する結像レンズ13と、該結像レンズ13による結像
位置に、余分な光を除き細線像Qを形成する第8面の如
き固定スリツト14を設け、さらに該固定スリツト14
を透過した細線像Qと交差しながら該細線像Qを走査す
る第9図の如き軸中心に対し放射状で等間隔な複数のス
リツト15aを有しモータ16で回転する回転スリツト
15と、上記固定スリツト11と該回転スリツト15の
交差点を透過した光を後述する電気系構成部分19の光
電子増倍管20に導く集光レンズ17とを備えた光学系
構成部分18と、第10図の如く上記光学系構成部分1
8の後に設置され、該光学系構成部分18からの光を電
気信号に変換し被検査物Xの表面の良否を判定する本計
測装置と予備計測装置とからなる電気系構成部分19と
から構成される。
To explain an embodiment, as shown in FIGS. 5 and 6, the present invention includes a pusher 16 for transporting the object X from position N1 to position N2, and a roll 7 for rotating the object X at position N2. A discharge chute 9 having a sorting door 8 through which the inspected object X at position N2 is pushed out by the inspected object an accessory part consisting of;
As shown in FIG. 7, a light source 10 illuminating the object X is installed above the object X, a condenser lens 11 and a half mirror 12 are installed between the light source 10 and the object An imaging lens 13 that forms an image of the light reflected from the surface of the object X guided by the half mirror 12, and an eighth surface that removes excess light and forms a thin line image Q at the imaging position by the imaging lens 13. A fixed slit 14 as shown in FIG.
A rotary slit 15 rotated by a motor 16 and having a plurality of slits 15a radially and equally spaced from the axis center as shown in FIG. An optical system component 18 includes a condenser lens 17 that guides the light transmitted through the intersection of the slit 11 and the rotating slit 15 to a photomultiplier tube 20 of an electrical system component 19, which will be described later, and the above-mentioned optical system component 18 as shown in FIG. Optical system component part 1
The electrical system component 19 is installed after the optical system component 8 and consists of a main measuring device and a preliminary measuring device that converts the light from the optical system component 18 into an electrical signal and determines the quality of the surface of the object to be inspected. be done.

前記本計測装置は上記光学系構成部分18からの光を電
気信号に変換する光電子増倍管20と、該光電子増倍管
20からの出力信号Aを増巾する増巾器21と、該増巾
器21の出力信号を予備計測装置からの欠陥検出レベル
Fと比較し良否の判定信号を出すコンパレーター22と
、該コンパレーター22の出力信号Gを実測定時間だけ
通すゲート回路23と、該ゲート回路23の出力信号H
を、測定を終えた被検査物Xがロール7上から前述の排
出シユート9に送られ、次の被検査物Xがロール7上に
移動してくるまでのローデイング及びアンローデイング
時間のあいだ保持しつづけるメモリー回路24と、該メ
モリー回路24の出力信号1でオン−オフ動作し、前述
した選別扉8を動かして良品と不良品とを選別する信号
を送るリレー回路25とから構成される。予備計測装置
は第10図の一点鎖線内で示すように前記増巾器21と
コンパレーター22との間に配置され、予備計測の開始
と共に発振器26で駆動され分割された予備計測信号1
,2,3を送るカウンター27と、該予備計測信号1,
2,3によりサイクリツクに動作可能にされ、且つそれ
ぞれ分割された予備計測時間T,,t2,t3だけ増巾
された出力信号Aを通過さすアナログゲートA,,a2
,a3と、該アナログゲートの出力信号Bl,B2,B
3を積分し、その積分値を前記予備計測時間Tl,t2
,t3に次ぐ予備計測信号2,3,1の間その値を保持
し、次につづく予備計測信号3,1,2によりりセツト
される積分回路Bl,b2,b3と、各予備計測信号2
,3,1で動作可能にされ、且つ積分回路B,,b2,
b3の出力Cl,C2,C3を通過させるアナログゲー
トDl,d2,d3と、予備計測の開始と共に動作可能
にされ計測完了と共にりセツトされるあいだ該アナログ
ゲートDl,d2,d3から送られてきた積分回路出力
Dl,D2,D3の最大値を保持するピークホールド回
路28と、前記最大値を検出したい欠陥の程度に応じて
欠陥検出レベルFをF−AEなる関係に設定するレベル
調節器29とから構成される。
The measuring device includes a photomultiplier tube 20 that converts light from the optical system component 18 into an electrical signal, an amplifier 21 that amplifies the output signal A from the photomultiplier tube 20, and an amplifier 21 that amplifies the output signal A from the photomultiplier tube 20. A comparator 22 that compares the output signal of the width detector 21 with the defect detection level F from the preliminary measurement device and outputs a pass/fail judgment signal, a gate circuit 23 that passes the output signal G of the comparator 22 for the actual measurement time, and Output signal H of gate circuit 23
is held during the loading and unloading time until the inspected object It is composed of a memory circuit 24, and a relay circuit 25 which is turned on and off by the output signal 1 of the memory circuit 24, and sends a signal for moving the aforementioned sorting door 8 and sorting good products from defective products. The preliminary measurement device is disposed between the amplifier 21 and the comparator 22 as shown in the dashed line in FIG.
, 2, 3, and the preliminary measurement signal 1,
analog gates A, , a2 which are enabled to operate cyclically by 2 and 3 and which pass the output signal A amplified by the divided pre-measurement times T, , t2 and t3, respectively;
, a3 and the output signals Bl, B2, B of the analog gate
3, and the integral value is calculated at the preliminary measurement time Tl, t2.
, t3, the integration circuits B1, b2, b3 hold their values during the preliminary measurement signals 2, 3, 1 following the subsequent preliminary measurement signals 3, 1, 2, and are reset by the subsequent preliminary measurement signals 3, 1, 2, and each preliminary measurement signal 2.
,3,1, and the integrating circuit B,,b2,
Analog gates Dl, d2, d3 pass the outputs Cl, C2, C3 of b3, and analog gates Dl, d2, d3 pass through the analog gates Dl, d2, d3, which are made operational at the start of the preliminary measurement and reset at the completion of the measurement. a peak hold circuit 28 that holds the maximum value of the integral circuit outputs Dl, D2, and D3; and a level adjuster 29 that sets the defect detection level F to the relationship F-AE according to the degree of the defect for which the maximum value is to be detected. It consists of

ここでαはレベル調節器29により設定される定数であ
り過去の蓄積データ等より経験的に導き出されたもので
ある。上記電気系構成部分19においては前記レベル調
節器29の出力信号を欠陥検出レベルFとしてコンパレ
ーター22により光電子増倍管20からの出力信号Aと
比較させる構成を採つているが、この他第11図に示す
ように、光電子増倍管20からの出力信号Aを一旦、割
算器30によりピークホールド回路28の出力信号Eで
割算して基準レベルに揃えたあと、コンパレーター22
/により一定値に設定された欠陥検出レベルF′と比較
するようにしたものでも同様の出力信号が得られる。す
なわち、前述の第10図に示した方法では、出力信号A
をf(t)とし、その積分値の最大値Eをf(t)Ma
xとした場合、信号Aと欠陥検出レベルFとの比Rはと
なるが、割算器を使用する方法では、割算器をf(t)
経た信号は:=::となり、この信号にαなる欠Flf
しーーー一)′111【j′L 陥検出レベルを設定すると、その比は となり、前記に等しくなる。
Here, α is a constant set by the level adjuster 29, and is derived empirically from past accumulated data. The electrical system component 19 has a configuration in which the output signal of the level adjuster 29 is set as a defect detection level F and is compared with the output signal A from the photomultiplier tube 20 by a comparator 22. As shown in the figure, the output signal A from the photomultiplier tube 20 is once divided by the output signal E of the peak hold circuit 28 by the divider 30 to equalize it to the reference level, and then the comparator 22
A similar output signal can be obtained by comparing the defect detection level F' set to a constant value by /. That is, in the method shown in FIG. 10 described above, the output signal A
is f(t), and the maximum value E of the integral value is f(t)Ma
x, the ratio R between the signal A and the defect detection level F is, but in the method using a divider, the divider is f(t)
The signal passed through becomes:=::, and this signal has a lack of α, Flf.
(1)'111[j'L When the defect detection level is set, the ratio is as follows, which is equal to the above.

従つてどちらの方法を採用しても欠陥信号の検出に関し
ては同等の効果を持つ。
Therefore, whichever method is adopted has the same effect in detecting defective signals.

ここでRなる量は、欠陥検出レベルの設定度合を示す量
である。ただし、発振器26の発振周波数は一定に保た
れ、したがつて各予備計測信号1,2,3は一定時間に
保たれる。また積分回路の積分定数は積分回路の出力C
l,C2,C3が各々予備計測の対象となつた面の平均
的な明るさにほぼ等しくなる様に調整される。以上の構
成を有する本装置の作用を以下に説明する。
The quantity R here is a quantity indicating the degree of setting of the defect detection level. However, the oscillation frequency of the oscillator 26 is kept constant, and therefore each preliminary measurement signal 1, 2, 3 is kept at a constant time. Also, the integral constant of the integrating circuit is the output C of the integrating circuit.
l, C2, and C3 are adjusted so that they are each approximately equal to the average brightness of the surface that is the subject of the preliminary measurement. The operation of this device having the above configuration will be explained below.

被検査物Xがプツシヤ一6でロール7上に送られて、最
後に排出シユート9へ送り出されるまでの1サイクルは
、第12図に示すように被検査物Xをロール7上に送る
と同時に検査後ロール7下方の排出シユート9に投下す
るローデイング及びアンローデイング時間と、ロール7
上で回転する被検査物Xに光を照射して表面きずの検出
を行なう計測時間とに区分される。
One cycle in which the inspected object Loading and unloading time for dropping the roll 7 into the discharge chute 9 below the roll 7 after inspection, and the roll 7
The measurement time is divided into the measurement time during which surface flaws are detected by irradiating light onto the object X rotating above.

しかして前記計測時間は前段の予備計測時間T1と後段
の実計測時間T2とに区分され、さらに前段の予備計測
時間T1は分割された予備計測時間t1ツT2?T3ラ
t1?T22゜゜゜゛゜゛゜゜゜゜゛゜゛゜゛に細区分
される。
Therefore, the measurement time is divided into a preliminary measurement time T1 in the first stage and an actual measurement time T2 in the second stage, and further, the preliminary measurement time T1 in the first stage is divided into preliminary measurement time t1 t T2? T3 la t1? It is subdivided into T22゜゜゜゛゜゛゜゜゜゜゛゜゛゜゛.

この時、予備計測する面と実計測する面とは同じ面であ
ることが望ましいが、一部分の予備計測で全体を推定し
てもその予備計測部分が充分な範囲をもつものであれば
実用上何等問題はなく、本実施例においても一部分を予
備計測し、それに続く部分を実計測するようにしている
。また予備計測の対象となる面は、ある予備計測時間に
おいては一部の面で、第13図に示すように、その対象
となる面は被検査物Xの全巾がとられる場合もあるが、
特定の被検査物Xでは、その加工方法の特徴によつて、
ある一部の面によく欠陥が発生する場合等がある時は、
その部分を意識的にさける場合、例えば第13図の点線
の内部を予備計測の対象外にすることもある。さて、被
検査物X表面からの反射光は・・−フミラ一12、結像
レンズ13を経て固定スリツト14を透過し、回転スリ
ツト15上に細線像Qが映し出される。
At this time, it is desirable that the surface to be preliminarily measured and the surface to be actually measured are the same surface, but even if the whole is estimated by preliminary measurement of a part, it is practical if the preliminary measurement part has a sufficient range. There is no problem, and in this embodiment as well, one part is preliminarily measured, and the subsequent part is actually measured. In addition, the surface to be subjected to preliminary measurement is only a part of the surface at a certain preliminary measurement time, and as shown in FIG. 13, the entire width of the object to be inspected ,
For a specific inspected object X, depending on the characteristics of its processing method,
If defects often occur on a certain surface,
When intentionally avoiding that part, for example, the area inside the dotted line in FIG. 13 may be excluded from the preliminary measurement. Now, the reflected light from the surface of the object to be inspected X passes through the camera lens 12, the imaging lens 13, and the fixed slit 14, and a thin line image Q is projected onto the rotating slit 15.

細線像Qと回転スリツト15との位置関係は、第14図
に示す如く細線像Qの両端部が相隣るスリツト15aの
両方に同時にかかる状態を生じうるようにする。回転ス
リツト15の回動につれて該細線像Qは走査され、集光
レンズ17により光電子増倍管20に入射される。光電
子増倍管20の出力信号は増巾器21で適当に増巾され
第15図のごとき信号Aを予備計測装置に送る。第15
図においてMは良面の信号、Lは欠陥部による信号で暗
い方向に出ている有様を示す。Rは回転スリツト15の
スリツト15aが第14図の如く同時に像にかかつた時
の信号で明るい方向に出ている。この出力信号Aは、ま
ず予備計測信号1によつて動作可能にされるアナログゲ
ートa1に送られ、アナログゲートa1は予備計測時間
T,だけ出力信号B1を積分回路B,に送る。積分回路
B,は該出力B1を積分し、予備計測信号2の間その値
を保持し、予備計測信号3によりりセツトされる。積分
回路B2,b3についても同様で、この状況は第16図
に示す通りである。アナログゲートD,は予備計測信号
2で動作可能にされ、積分回路b1の出力C1をピーク
ホールド回路28に導く。かくしてピークホールド回路
28は該ピークホールド回路28に送られてくるアナロ
グゲートD,,d2,d3の出力信号Dl,D2,D3
の最大値Eを保持L、すなわち予備計測中の最も明るい
信号、いいかえれば最も良面の部分の出力信号値を保持
する。そして該出力Eはレベル調節器29により増減さ
れてコンパレーター22の欠陥検出レベルFを与える。
第17図は予備計測によつてレベル調節器29の出力F
の推移を示したもので、予備計測1で求められた結果は
、回路構成上予備計測2の時にレベル調節器29の出力
Fとなつてあられれる。しかしこれは過去に求められた
積分値の最大値より大きい場合で、小さい場合は過去の
最大値がそのままレベル調節器29の出力Fとなる。予
備計測2、3についてもまつたく同様である。第17図
右方は予備計測時に求められた積分値の最大値に比例し
た量が欠陥検出レベルFとして使用されている状況を示
し、比較的欠陥信号の小さい欠陥でも検出可能となる。
なお、上記レベル調節器29とコンパレーター22によ
り構成した部分と同様の目的を達成するものを第11図
に示したが、この場合は割算器30により光電子増倍管
20からの出力信号Aを、該出力信号Aに対応するピー
クホールド回路28の出力信号Eで割算操作して、一旦
、出力信号を基準レベルに移し、しかる後、コンパレー
ター22!により一定レベルに設定した欠陥検出レベル
F′と比較するものである。コンパレーター22及び2
2′の出力信号Gは実測定区間に同期して入力信号を通
すゲート回路23を経て、次のメモリー回路24により
前述のアンローデイング区間のあいだ記憶され、メモリ
ー回路24の出力信号1によりリレー回路25が作動す
る。而してリレー回路25に接続した動力が欠陥信号の
有無に対応して選別扉8を作用させる。本発明によれば
、信号の平均レベルから比較的欠陥信号の小さい欠陥の
検出が可能となる。
The positional relationship between the thin line image Q and the rotating slit 15 is such that both ends of the thin line image Q can simultaneously touch both adjacent slits 15a, as shown in FIG. As the rotating slit 15 rotates, the thin line image Q is scanned and is incident on the photomultiplier tube 20 by the condensing lens 17. The output signal of the photomultiplier tube 20 is appropriately amplified by an amplifier 21, and a signal A as shown in FIG. 15 is sent to a preliminary measurement device. 15th
In the figure, M indicates a signal from a good surface, and L indicates a signal from a defective portion, which appears in the dark direction. R is a signal when the slit 15a of the rotating slit 15 is applied to the image at the same time as shown in FIG. 14, and it appears in the bright direction. This output signal A is first sent to an analog gate a1 enabled by a preliminary measurement signal 1, and the analog gate a1 sends an output signal B1 to an integrating circuit B for a preliminary measurement time T. The integrating circuit B integrates the output B1, holds its value during the preliminary measurement signal 2, and is reset by the preliminary measurement signal 3. The same applies to the integrating circuits B2 and b3, and this situation is as shown in FIG. The analog gate D, is enabled with the preliminary measurement signal 2 and leads the output C1 of the integrating circuit b1 to the peak hold circuit 28. Thus, the peak hold circuit 28 receives the output signals Dl, D2, D3 of the analog gates D, d2, d3 sent to the peak hold circuit 28.
The maximum value E is held L, that is, the brightest signal during preliminary measurement, in other words, the output signal value of the best part is held. The output E is increased or decreased by a level adjuster 29 to provide a defect detection level F of the comparator 22.
FIG. 17 shows the output F of the level adjuster 29 based on preliminary measurements.
The result obtained in the preliminary measurement 1 is obtained as the output F of the level adjuster 29 during the preliminary measurement 2 due to the circuit configuration. However, this is the case when the integral value is larger than the maximum value of the integral values found in the past, and when it is smaller, the past maximum value becomes the output F of the level adjuster 29 as it is. The same holds true for preliminary measurements 2 and 3. The right side of FIG. 17 shows a situation where an amount proportional to the maximum value of the integral value obtained during preliminary measurement is used as the defect detection level F, and even defects with relatively small defect signals can be detected.
FIG. 11 shows a part that achieves the same purpose as the level adjuster 29 and comparator 22, but in this case, the output signal A from the photomultiplier tube 20 is divided by the divider 30. is divided by the output signal E of the peak hold circuit 28 corresponding to the output signal A, the output signal is once shifted to the reference level, and then the comparator 22! This is compared with the defect detection level F' which is set to a constant level. Comparators 22 and 2
The output signal G of 2' passes through the gate circuit 23 that passes the input signal in synchronization with the actual measurement period, and is stored in the next memory circuit 24 during the aforementioned unloading period, and the output signal 1 of the memory circuit 24 causes the relay circuit 25 is activated. The power connected to the relay circuit 25 operates the sorting door 8 in response to the presence or absence of a defect signal. According to the present invention, it is possible to detect a defect with a relatively small defect signal based on the average level of the signal.

良品に対しては欠陥検出レベルが波形に近づきすぎる事
がなくあやまつて不良と判定されることがないなどの効
果を奏する。
For non-defective products, the defect detection level does not become too close to the waveform, so that it is not mistakenly determined to be defective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来装置の概略図、第2図は従来装置の一実施
例における検査信号と欠陥検出レベルとの関係を示す図
、第3図は比較的広範囲にでた薄いサビ様の欠陥を示す
斜視図、第4図は薄いサビ様の欠陥部による検査信号を
示す波形図、第5図は附帯部分の実施例を示す概略図、
第6図はロールの側面図、第7図は光学系構成部分の詳
細図、第8図は固定スリツトの平面図、第9図は回転ス
リツトの平面図、第10図は電気系構成部分のプロツク
図、第11図は第10図の一部と置換可能なプロツク図
、第12図は被検査物の投入から排出までの1サイクル
の内容を示す図、第13図は予備計測の対象となる面を
示す図、第14図は細線像と回転スリツトとの位置関係
を示す図、第15図は光電子増倍管の出力信号を示す波
形図、第16図は予備計測信号と積分回路の関係を示す
図、第17図は予備計測時の出力と検査信号との推移並
びに実計測時の検査信号と欠陥検出レベルとの関係を示
す図である。 20・・・・・・光電子増倍管、22,22t・・・・
・コンパレーター、23・・・・・・ゲート回路、26
・・・・・・発振器、27・・・・・・カウンター、2
8・・・・・・ピークホールド回路、29・・・・・・
レベル調節器、30・・・・・・割算器、F,F′・・
・・・・欠陥検出レベル。
Fig. 1 is a schematic diagram of a conventional device, Fig. 2 is a diagram showing the relationship between the inspection signal and defect detection level in an embodiment of the conventional device, and Fig. 3 shows a thin rust-like defect that appears over a relatively wide area. 4 is a waveform diagram showing an inspection signal due to a thin rust-like defect, and FIG. 5 is a schematic diagram showing an example of an incidental part.
Figure 6 is a side view of the roll, Figure 7 is a detailed view of the optical system components, Figure 8 is a plan view of the fixed slit, Figure 9 is a plan view of the rotating slit, and Figure 10 is the electrical system component. Figure 11 is a block diagram that can be replaced with a part of Figure 10, Figure 12 is a diagram showing the contents of one cycle from loading to discharge of the object to be inspected, and Figure 13 is a diagram showing the contents of one cycle from loading to discharge of the object to be inspected. Figure 14 is a diagram showing the positional relationship between the thin line image and the rotating slit, Figure 15 is a waveform diagram showing the output signal of the photomultiplier tube, and Figure 16 is a diagram showing the preliminary measurement signal and the integration circuit. FIG. 17 is a diagram showing the relationship between the output during preliminary measurement and the inspection signal, and the relationship between the inspection signal and the defect detection level during actual measurement. 20...Photomultiplier tube, 22,22t...
・Comparator, 23...Gate circuit, 26
...Oscillator, 27 ...Counter, 2
8...Peak hold circuit, 29...
Level adjuster, 30...Divider, F, F'...
...Defect detection level.

Claims (1)

【特許請求の範囲】 1 被検査物の表面反射光を光電変換し、その出力信号
を欠陥検出レベルと比較することにより物体の表面きず
を検出するものにおいて、光電子増倍管からの出力信号
を発振器により分割された予備計測信号(1)、(2)
、(3)を送るカウンターと、該各分割予備計測信号(
1)、(2)、(3)でサイクリツクに動作可能にされ
、且つ分割された計測時間t_1、t_2、t_3だけ
増巾された出力信号を通過させるアナログゲートa_1
、a_2、a_3とを備え、さらに該アナログゲートa
_1、a_2、a_3の出力信号B_1、B_2、B_
3を積分し、その積分値を予備計測信号(2)、(3)
、(1)の間保持し、予備計測信号(3)、(1)、(
2)でリセットされる積分回路b_1、b_2、b_3
と、予備計測信号(2)、(3)、(1)で動作可能に
され、且つ該積分回路b_1、b_2、b_3の出力C
_1、C_2、C_3を通過させるアナログゲートd_
1、d_2、d_3と、予備計測の開始と共に動作可能
にされ計測完了と共にリセットされる間、過去の積分値
の最大出力を保持するピークホールド回路とを設け、該
ピークホールド回路の最大値をレベル調節器で欠陥検出
レベルに設定して、該欠陥検出レベルと光電子増倍管か
らの出力信号とを比較するコンパレーターと、該コンパ
レーターの出力信号を実計測時間だけ通すゲート回路と
を備えたことを特徴とする物体の表面きず検出装置。 2 被検査物の表面反射光を光電変換し、その出力信号
を欠陥検出レベルと比較することにより物体の表面きず
を検出するものにおいて、光電子増増管からの出力信号
を発振器により分割された予備計測信号(1)、(2)
、(3)を送るカウンターと、該各分割予備計測信号(
1)、(2)、(3)でサイクリツクに動作可能にされ
、且つ分割された計測時間t_1、t_2、t_3だけ
増巾された出力信号を通過させるアナログゲートa_1
、a_2、a_3とを備え、さらに該アナログゲートa
_1、a_2、a_3の出力信号B_1、B_2、B_
3を積分し、その積分値を予備計測信号(2)、(3)
、(1)の間保持し、予備計測信号(3)、(1)、(
2)でリセットされる積分回路b_1、b_2、b_3
と、予備計測信号(2)、(3)、(1)で動作可能に
され、且つ該積分回路b_1、b_2、b_3の出力C
_1、C_2、C_3を通過さすアナログゲートd_1
、d_2、d_3と、予備計測の開始と共に動作可能に
され計測完了と共にリセットされる間、過去の積分値の
最大出力を保持するピークホールド回路とを設けて、前
記光電子増倍管からの出力信号を基準レベルに揃えるた
め割算器により該ピークホールド回路の最大値で割算し
、しかる後、一定レベルに設定した欠陥検出レベルと比
較するコンパレーターと、該コンパレーターの出力信号
を実計測時間だけ通すゲート回路とを備えたことを特徴
とする物体の表面きず検出装置。
[Claims] 1. In a device that detects surface flaws on an object by photoelectrically converting light reflected from the surface of the object to be inspected and comparing the output signal with a defect detection level, the output signal from a photomultiplier tube is Preliminary measurement signals (1), (2) divided by oscillator
, (3) and a counter that sends each divided preliminary measurement signal (
Analog gate a_1 that is enabled to operate cyclically in 1), (2), and (3) and passes the output signal amplified by the divided measurement times t_1, t_2, and t_3.
, a_2, a_3, and the analog gate a
Output signals B_1, B_2, B_ of _1, a_2, a_3
3, and the integral value is used as the preliminary measurement signal (2), (3)
, (1), and the preliminary measurement signals (3), (1), (
Integrating circuits b_1, b_2, b_3 reset in 2)
and the outputs C of the integrating circuits b_1, b_2, b_3 are enabled to operate with the preliminary measurement signals (2), (3), and (1)
Analog gate d_ that passes _1, C_2, and C_3
1, d_2, d_3, and a peak hold circuit that holds the maximum output of the past integral value while being enabled to operate at the start of preliminary measurement and being reset at the completion of measurement, and the maximum value of the peak hold circuit is set to the level. It is equipped with a comparator that sets a defect detection level with a regulator and compares the defect detection level with an output signal from a photomultiplier tube, and a gate circuit that passes the output signal of the comparator for only the actual measurement time. A device for detecting surface flaws on an object, characterized by: 2 In a device that detects surface flaws on an object by photoelectrically converting light reflected from the surface of the object to be inspected and comparing the output signal with the defect detection level, the output signal from the photomultiplier is divided by an oscillator. Measurement signal (1), (2)
, (3) and a counter that sends each divided preliminary measurement signal (
Analog gate a_1 that is enabled to operate cyclically in 1), (2), and (3) and passes the output signal amplified by the divided measurement times t_1, t_2, and t_3.
, a_2, a_3, and the analog gate a
Output signals B_1, B_2, B_ of _1, a_2, a_3
3, and the integral value is used as the preliminary measurement signal (2), (3)
, (1), and the preliminary measurement signals (3), (1), (
Integrating circuits b_1, b_2, b_3 reset in 2)
and the outputs C of the integrating circuits b_1, b_2, b_3 are enabled to operate with the preliminary measurement signals (2), (3), and (1)
Analog gate d_1 that passes through _1, C_2, and C_3
, d_2, d_3, and a peak hold circuit that holds the maximum output of the past integrated value while being enabled to operate at the start of preliminary measurement and being reset at the completion of the measurement, to control the output signal from the photomultiplier tube. A divider divides the value by the maximum value of the peak hold circuit in order to align it with the reference level, and then a comparator compares it with the defect detection level set at a constant level, and the output signal of the comparator is divided by the maximum value of the peak hold circuit. A device for detecting surface flaws on an object, characterized by comprising a gate circuit that only allows passage through the surface of an object.
JP557677A 1977-01-20 1977-01-20 Object surface flaw detection device Expired JPS5920969B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP557677A JPS5920969B2 (en) 1977-01-20 1977-01-20 Object surface flaw detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP557677A JPS5920969B2 (en) 1977-01-20 1977-01-20 Object surface flaw detection device

Publications (2)

Publication Number Publication Date
JPS5390984A JPS5390984A (en) 1978-08-10
JPS5920969B2 true JPS5920969B2 (en) 1984-05-16

Family

ID=11615038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP557677A Expired JPS5920969B2 (en) 1977-01-20 1977-01-20 Object surface flaw detection device

Country Status (1)

Country Link
JP (1) JPS5920969B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789049B2 (en) * 1986-03-31 1995-09-27 株式会社島津製作所 Displacement gauge

Also Published As

Publication number Publication date
JPS5390984A (en) 1978-08-10

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