JPS59208836A - Manufacturing device for semiconductor - Google Patents

Manufacturing device for semiconductor

Info

Publication number
JPS59208836A
JPS59208836A JP8264983A JP8264983A JPS59208836A JP S59208836 A JPS59208836 A JP S59208836A JP 8264983 A JP8264983 A JP 8264983A JP 8264983 A JP8264983 A JP 8264983A JP S59208836 A JPS59208836 A JP S59208836A
Authority
JP
Japan
Prior art keywords
chamber
etching
shutter
baking
cassette
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8264983A
Other languages
Japanese (ja)
Inventor
Kaname Kasama
笠間 要
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8264983A priority Critical patent/JPS59208836A/en
Publication of JPS59208836A publication Critical patent/JPS59208836A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To prevent the corrosion of Al without bringing Al into contact with air by transferring and placing a material to be treated, to which etching is completed, in a baking chamber as it is. CONSTITUTION:When a shutter 20 is opened and a loader 24 is operated, wafers W in a cassette 3 are placed on a forward carrying section 12, and pass through a non-baking section in a baking chamber 11 and are carried. When the shutter 20 is shut and a shutter 21 is opened, the wafers W are moved into an etching chamber 5, and loaded on a lower electrode 7 by a shifter 26. When the shutter 21 is shut and high-frequency power is applied between both electrodes 6, 7, plasma is generated on both electrodes, and Al layers on the surfaces of the wafers W are etched to a predetermined pattern. The etching is completed, a shutter 22 is opened, and the wafers W are placed on a return carrying section 13 by a shifter 26. The wafers W are moved by the returning carrying section 13 in the baking chamber 11 at the same time as the shutter 22 is shut, heated by a baking source 14 on their midways, and baked.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体製造装置に関し、特にAJ膜の加工に際
してA−eの腐蝕を防止することのできる半導体製造装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor manufacturing equipment, and more particularly to a semiconductor manufacturing equipment that can prevent A-e corrosion during processing of an AJ film.

〔背景技術〕[Background technology]

半導体装置の製造工程の一つにA!配線層の形成工程が
あり、半導体ウエーノ・の全面にAffl或いはA1合
金膜を形成した上でこれを所定の配線パターンにエツチ
ング形成している。ところで、この種のエツチングには
c ci、ガスを使用したドライエツチング法が使用さ
れているが、エンチング時に生成されたC−eラジカル
がエツチング終了後もA1膜に残存付着され、空気中の
H,O等と反応してHC4を生成し、これによりパター
ニングされたA−e配線が腐蝕され断線等の障害が生じ
ることがある。
One of the manufacturing processes of semiconductor devices is A! There is a process for forming a wiring layer, in which an Affl or A1 alloy film is formed on the entire surface of the semiconductor wafer and then etched into a predetermined wiring pattern. Incidentally, this type of etching uses a dry etching method using cci gas, but the C-e radicals generated during etching remain attached to the A1 film even after the etching is finished, and the H in the air , O, etc., to generate HC4, which may corrode the patterned A-e wiring and cause problems such as disconnection.

このため本発明者は、ドライエツチングの終了後に真空
状態のエツチング装置内から取り出したウェーハな直ち
にベーク炉内に移載し、ここでベークな行なうことによ
りC!ラジカルを除去し、A!の腐蝕を防止する対策な
試みている。しかしながら、この対策ではエツチング装
置からベーク炉内に移すまでの空気に晒される状態を皆
無にすることはできず、したがって腐蝕の進行を直ちに
停止することが困難であると共に、ウェー/・を短時間
で移載するための迅速な操作が要求される等の問題が生
じることが本発明者によりあきらかとされた。
For this reason, the inventor of the present invention has proposed that after completion of dry etching, the wafer is removed from the vacuum etching apparatus, immediately transferred to a baking oven, and baked there. Remove radicals, A! Attempts are being made to prevent corrosion. However, with this countermeasure, it is not possible to completely eliminate the exposure to air from the etching equipment to the baking oven, and therefore it is difficult to immediately stop the progress of corrosion, and it is difficult to immediately stop the progress of corrosion. The inventors have found that problems arise, such as the need for quick operations for transfer.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、A4のi蝕を確実に防止することがで
きる半導体製造装置を提供することである。さらに被処
理物の取扱いを容易なものにできる半導体製造装置を提
供することにある。
An object of the present invention is to provide a semiconductor manufacturing apparatus that can reliably prevent A4 i corrosion. Furthermore, it is an object of the present invention to provide a semiconductor manufacturing apparatus that can facilitate the handling of objects to be processed.

本発明の前記ならびにそのはカーの目的と新規な特徴は
、本明細書の記述および添付図面からあきらかになるで
あろう。
The above-mentioned objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、エツチング装置のエツチング室に隣接してベ
ータ室を配設し、エツチングの終了した被処理物をその
ままベータ室に移載できるようにすることにより、エツ
チング終了からベータまでの間にA2を空気に触れさす
ことはなく、これによりA!の腐蝕を確実に防止すると
共に、被処理物の移載等の取扱いを容易化するものであ
る。
That is, by arranging a beta chamber adjacent to the etching chamber of the etching apparatus and making it possible to transfer the processed workpiece that has been etched as is to the beta chamber, A2 can be air-filled between the end of etching and the beta. This means A! In addition to reliably preventing corrosion of the material, it also facilitates handling such as transfer of the material to be processed.

〔実施例〕〔Example〕

第1図及び第2図は本発明による一実施例装置の平面図
と展開断面図である。図において、1はロードカセット
室、2はアンロードカセット室であり、ロードカセット
室1には複数枚の被処理物、すなわち半導体ウェーハW
をセットしたカセット3を設置でき、アンロードカセッ
ト室2にはエツチングの完了されたウエーノ・を複数枚
収納できる空のカセット4を設置できる。
1 and 2 are a plan view and a developed sectional view of an embodiment of the device according to the present invention. In the figure, 1 is a load cassette chamber, and 2 is an unload cassette chamber.
A cassette 3 in which etching has been completed can be installed, and an empty cassette 4 capable of storing a plurality of etched wafers can be installed in the unload cassette chamber 2.

5は前記ロードカセット室1に隣設したエツチング室で
あり、平行平板の上部電極6と下部電極7とを対向配置
し、下部電極7上にウェーハWを載置すると共に両電極
6,7間に高周波電源8からの高周波電力を印加できる
。また、前記エツチング室にはcci4ガス等の所要の
エツチングガスな供給するためのガス供給口9を開設す
る一方、室内な所定の真空度とするために図外の真空ポ
ンプに接続した排気口10を開設している。
Reference numeral 5 denotes an etching chamber adjacent to the load cassette chamber 1, in which an upper electrode 6 and a lower electrode 7 of parallel flat plates are arranged facing each other, a wafer W is placed on the lower electrode 7, and an etching chamber is placed between the two electrodes 6 and 7. High frequency power from a high frequency power source 8 can be applied to the high frequency power source 8. The etching chamber is also provided with a gas supply port 9 for supplying necessary etching gas such as CCI4 gas, and an exhaust port 10 connected to a vacuum pump (not shown) to maintain a predetermined degree of vacuum in the chamber. has been established.

11は前記エツチング室5.ロードカセット室1、アン
ロードカセット室2に夫々隣接して設けられたベーク室
であり、内部には2本のべ/l/)コンベア等からなる
往、復の各搬送部12.13’に延設している。即ち、
往搬送部12はロードカセット室1とエツチング室5を
結ぶ間に、復搬送部13はエツチング室5とアンロード
カセット室2な結ぶ間に夫々設げている。また、内部に
は赤外線ランプで代表されるベーク源14を前記復搬送
部13上に配設する一方、図外の真空ポンプに接続して
ベーク室ll内を真空引きする排気口15を開設してい
る。
11 is the etching chamber 5. This is a baking chamber provided adjacent to the load cassette chamber 1 and the unload cassette chamber 2, respectively. It is being extended. That is,
The forward transport section 12 is provided between the load cassette chamber 1 and the etching chamber 5, and the return transport section 13 is provided between the etching chamber 5 and the unload cassette chamber 2. Inside, a bake source 14 represented by an infrared lamp is disposed on the return conveyance section 13, and an exhaust port 15 is provided to connect to a vacuum pump (not shown) to evacuate the inside of the bake chamber 11. ing.

そして、前記ロードカセット室1とベータ室5、ベーク
室11とエツチング室5、ベーク室11とアンロードカ
セット室2との隔壁には前記往、復の搬送部12.13
に臨んで開口16.17と18゜19に形成し、かつこ
れらの開口にはこれを気密に閉成することができるシャ
ッタ20.21と22゜23を夫々設けている。
The reciprocating transport portions 12 and 13 are provided on the partition walls between the load cassette chamber 1 and the beta chamber 5, the bake chamber 11 and the etching chamber 5, and the bake chamber 11 and the unload cassette chamber 2.
Openings 16, 17 and 18.degree. 19 are formed facing the front, and these openings are provided with shutters 20.21 and 22.degree. 23, respectively, which can hermetically close the openings.

なお、図中24はロードカセット室1内でカセット3内
のウェーハWを往搬送部12に移載するローダ、25は
アンロードカセット室2内で復搬送部13上のウェーハ
Wをカセット4に収納するアンローダ、26は往、復の
各搬送部12.13と下部電極7どの間でウェーハWを
移載する移載器である。
In the figure, 24 is a loader that transfers the wafer W in the cassette 3 to the forward transport section 12 in the load cassette chamber 1, and 25 is a loader that transfers the wafer W on the backward transport section 13 to the cassette 4 in the unload cassette chamber 2. The housing unloader 26 is a transfer device that transfers the wafer W between the forward and backward transport sections 12 and 13 and the lower electrode 7.

以上の構成によれば、図外の真空ポンプを作動すれば排
気口10.15から空気が排気され、エツチング室5と
ベーク室11は所要の真空状態とされ空気が殆んどない
状態・となる。そして、ガス供給口9からエツチングガ
スを供給すればエツチング室5内は所要のガス雰囲気と
される。そして、図外のシーケンス制御部の作用により
(以下同じ)シャッタ20な開いてローダ24を作動す
ればカセット3内のウェー・・Wは往搬送部12に乗載
されベーク室11内の非ベーク部位な通って搬送される
。シャッタ20の閉成後に今度はシャッタ21を開けば
ウェー−・Wはエツチング室5内に移動され移載器26
によって下部電極7上に搭載される。
According to the above configuration, when the vacuum pump (not shown) is activated, air is exhausted from the exhaust port 10.15, and the etching chamber 5 and the baking chamber 11 are brought into the required vacuum state, with almost no air present. Become. Then, by supplying etching gas from the gas supply port 9, the inside of the etching chamber 5 is made to have a required gas atmosphere. Then, when the shutter 20 is opened and the loader 24 is operated by the action of a sequence control section (not shown) (the same applies hereafter), the wafer W in the cassette 3 is loaded onto the forward conveyance section 12 and the non-baked wafer in the bake chamber 11 is loaded. It is transported through various parts of the body. When the shutter 21 is opened after the shutter 20 is closed, the wave W is moved into the etching chamber 5 and transferred to the transfer device 26.
is mounted on the lower electrode 7 by.

シャッタ21の間抜に両電極6,7間に高周波電力を印
加すれば、両電極にプラズマが発生し、ウェーハW表面
のA7層は所定のパターンにエツチングされる。
When high frequency power is applied between the electrodes 6 and 7 at the center of the shutter 21, plasma is generated between the electrodes and the A7 layer on the surface of the wafer W is etched into a predetermined pattern.

エツチングの終了後はシャック22な開き、移載器26
によってウェー/・Wを復搬送部13に乗せる。シャッ
タ22閉と共にウェー/・Wはベーク室11内を復搬送
部13によって移動され、その途中でベーク源14によ
り加熱されてベークが行なわれる。通常では80〜10
0℃の温度で5〜10m1n行なわれる。これにより、
A!に付着しているC、I3ラジカルは脱離される。同
時に、C!ラジカルはベーク室11内が真空状態である
ことから空気(外気)との接触が防止され、したがって
HClが生成されることもなく、A4の腐蝕は確実に防
止される。
After etching is completed, the shack 22 is opened and the transfer device 26 is opened.
The way/.W is placed on the return transport section 13. As soon as the shutter 22 is closed, the wafer/.W is moved within the bake chamber 11 by the return transport section 13, and on the way, it is heated by the bake source 14 and baked. Usually 80-10
It is carried out for 5 to 10 ml at a temperature of 0°C. This results in
A! The C, I3 radicals attached to are eliminated. At the same time, C! Since the inside of the baking chamber 11 is in a vacuum state, the radicals are prevented from coming into contact with air (outside air), so that HCl is not generated, and corrosion of A4 is reliably prevented.

ベークの完了後はシャッタ23を開き、ウェー/・Wは
アンローダ25によって復搬送部13かもアンロードカ
セット室2に移され更にカセット4内に収納されて全て
の工程が完了されることになる。
After the baking is completed, the shutter 23 is opened, and the unloader 25 transfers the wafer/W to the unloading cassette chamber 2 as well as the return conveyance section 13, and further houses it in the cassette 4, thereby completing all the steps.

〔効果〕〔effect〕

(1)エンチング室とベーク室を隣設しかつ画室を所要
の真空度に設定しているので、エツチングの終了したウ
ェーハを空気に触れさせることな(ベークすることがで
き、これによりA1の腐蝕を確実に防止することができ
る。
(1) Since the etching chamber and the baking chamber are located next to each other, and the chamber is set to the required degree of vacuum, the etched wafer can be baked without being exposed to air, which prevents corrosion of A1. can be reliably prevented.

(2)エツチング室からそのままベーク室に移載できる
ので、ウェーハの移載をゆっくり行なっても空気と接触
することはなくその影響な防止できるので、ウェーハの
移載等その取扱いを容易なものにできる。
(2) Since the wafer can be directly transferred from the etching chamber to the bake chamber, even if the wafer is transferred slowly, it will not come into contact with air and its effects can be prevented, making wafer transfer and handling easier. can.

(3)  ロードカセット室、エツチング室、ベーク室
(3) Load cassette room, etching room, baking room.

アンロードカセット室間をローダ、往搬送部、移載器、
復搬送部、アンローダ等の移載手段で連絡しているので
、ウェーハのエツチング処理(べ一り処理な含む)を全
自動化することもできる。
The loader, forward transport section, transfer device,
Since communication is provided by transfer means such as a return transport section and an unloader, the wafer etching process (including leveling process) can be fully automated.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、各室の平面
配置は直線的な配置でもよく、また各移載手段は他の具
体的な手段であってもよい。なお、被処理物のエツチン
グ後、真空状態にてベークできる構成とすることに限定
されず、被処理物のエツチング後、アンロードカセット
室に達する前に被処理物なベークするような構成にして
も、被処理物がH,0に触れるのを最小限にすることが
でき有効である。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the planar arrangement of each chamber may be a linear arrangement, and each transfer means may be other specific means. Note that the present invention is not limited to a structure in which the object to be processed can be baked in a vacuum state after etching, but may be configured to allow the object to be baked after etching the object to be processed before reaching the unload cassette chamber. This method is also effective because it can minimize the contact of the object to be processed with H,0.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体製造装置のA
−eエツチング装置に適用した場合ニツイテ説明したが
、それに限定されるものではなく、エツチングガスとベ
ーク工程を連続して行なう必要のある技術に同様に適用
できる。
The above explanation mainly describes the invention made by the present inventor, which is the field of application of semiconductor manufacturing equipment.
Although the present invention has been described above when applied to an etching apparatus, the present invention is not limited thereto, and can similarly be applied to any technique that requires continuous etching gas and baking steps.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明装置の平面構成図、 第2図はその展開断面図である。 1・・・ロードカセット室、2・・アンロードカセット
室、3,4・・・カセット、5 =・エツチング室、6
・・・上部電極、7・・・下部電極、11・・・ベーク
室、12・・・往搬送部、13・・・復搬送部、14・
・・ベーク源噛外線ランプ)、20〜23・シャッタ、
24・・・ローダ、25・・・アンローダ、26・・・
移載器、w川波処理物(ウェーハ)。 代理人 弁理士  高 橋 明 夫 、  ゛・;  
FIG. 1 is a plan configuration diagram of the device of the present invention, and FIG. 2 is a developed sectional view thereof. 1... Load cassette chamber, 2... Unload cassette chamber, 3, 4... Cassette, 5 = Etching chamber, 6
. . . Upper electrode, 7. Lower electrode, 11. Bake chamber, 12. Forward transport section, 13. Return transport section, 14.
・・Bake source external line lamp), 20-23・Shutter,
24...Loader, 25...Unloader, 26...
Transfer device, w Kawanami processed material (wafer). Agent: Patent attorney Akio Takahashi, ゛・;
)

Claims (1)

【特許請求の範囲】 1、被処理物なエツチングするエツチング室と、エツチ
ング終了後の被処理物をベークするベーク室とを隣接す
ると共に両室を所定の真空状態に保持可能な構成とし、
エツチング後の被処理物が空気に触れることな(ベーク
されるよう構成したことを特徴とする半導体製造装置。 2、エツチング室とベーク室との間の隔壁を開口して被
処理物をこの開口を通して移載できるようにし、かつこ
の開口をシャッタにより気密に閉成できるようにしてな
る特許請求の範囲第1項記載の半導体製造装置。 3、ベーク室に隣接してロードカセット室とアンロード
カセット室を設け、被処理物はベーク室を通してエツチ
ング室に出し入れできるように構成してなる特許請求の
範囲第1項記載の半導体製造装置。 3、ベーク室に隣接してロードカセット室とアンロード
カセット室を設け、被処理物はベーク室を通してエツチ
ング室に出し入れできるように構成してなる特許請求の
範囲第1項又は第2項記載の半導体製造装置。
[Claims] 1. An etching chamber for etching the workpiece and a baking chamber for baking the workpiece after etching are adjacent to each other, and both chambers are configured to be maintained in a predetermined vacuum state,
A semiconductor manufacturing apparatus characterized in that the object to be processed after etching is baked without being exposed to air. 2. A partition between the etching chamber and the baking chamber is opened, and the object to be processed is removed from the opening. 3. A semiconductor manufacturing apparatus according to claim 1, wherein the semiconductor manufacturing apparatus is configured to be able to be transferred through the baking chamber, and this opening can be hermetically closed by a shutter. 3. A load cassette chamber and an unload cassette are located adjacent to the bake chamber. 2. A semiconductor manufacturing apparatus according to claim 1, wherein the semiconductor manufacturing apparatus is configured such that a chamber is provided, and the object to be processed can be taken in and out of the etching chamber through the baking chamber. 3. A load cassette chamber and an unload cassette are provided adjacent to the baking chamber. 3. A semiconductor manufacturing apparatus according to claim 1, wherein a chamber is provided, and the object to be processed can be taken in and out of the etching chamber through the baking chamber.
JP8264983A 1983-05-13 1983-05-13 Manufacturing device for semiconductor Pending JPS59208836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8264983A JPS59208836A (en) 1983-05-13 1983-05-13 Manufacturing device for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8264983A JPS59208836A (en) 1983-05-13 1983-05-13 Manufacturing device for semiconductor

Publications (1)

Publication Number Publication Date
JPS59208836A true JPS59208836A (en) 1984-11-27

Family

ID=13780273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8264983A Pending JPS59208836A (en) 1983-05-13 1983-05-13 Manufacturing device for semiconductor

Country Status (1)

Country Link
JP (1) JPS59208836A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131532A (en) * 1984-11-30 1986-06-19 Tokuda Seisakusho Ltd Heat treatment device for sheet-like material
JPS6232619A (en) * 1985-08-06 1987-02-12 Tokuda Seisakusho Ltd Thermal treatment equipment for sheet-like material
JPS6362325A (en) * 1986-09-03 1988-03-18 Nec Corp Dryetching device
JPS6442583A (en) * 1987-08-06 1989-02-14 Nec Corp Dry etching device
JPH01274428A (en) * 1988-04-27 1989-11-02 Hitachi Ltd Dry etching device
JPH01294880A (en) * 1988-05-19 1989-11-28 Mitsubishi Electric Corp Dry etching device
JPH0382121A (en) * 1989-08-25 1991-04-08 Nec Corp Post-processing of dryetching
JPH05343358A (en) * 1992-06-10 1993-12-24 Nec Corp Manufacture of semiconductor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131532A (en) * 1984-11-30 1986-06-19 Tokuda Seisakusho Ltd Heat treatment device for sheet-like material
JPS6232619A (en) * 1985-08-06 1987-02-12 Tokuda Seisakusho Ltd Thermal treatment equipment for sheet-like material
JPS6362325A (en) * 1986-09-03 1988-03-18 Nec Corp Dryetching device
JPS6442583A (en) * 1987-08-06 1989-02-14 Nec Corp Dry etching device
JPH01274428A (en) * 1988-04-27 1989-11-02 Hitachi Ltd Dry etching device
JPH01294880A (en) * 1988-05-19 1989-11-28 Mitsubishi Electric Corp Dry etching device
JPH0382121A (en) * 1989-08-25 1991-04-08 Nec Corp Post-processing of dryetching
JPH05343358A (en) * 1992-06-10 1993-12-24 Nec Corp Manufacture of semiconductor

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