JPS59208649A - Operation processor - Google Patents

Abstract

PURPOSE:To execute processing different from previously fixed processing or having different flow using a fixed pipe line unit by forming a parallel bus connecting respective units in parallel, an input control circuit, etc. CONSTITUTION:When a specific processing request different from the previously fixed processing exists, an input control circuit 7 waits pipe line data during one pipe line cycle. Namely, input to the initial stage unit is stopped and idle state is sent to a pipe line and made flow from a unit 1 to a unit 4. Interruption data are inputted to the idle processing unit through the parallel bus 6 and the fixed processing is executed in the unit. When the interruption data requiring the specific processing are inputted, the input of pipe line data is interrupted, the idle state is formed and the processing can be executed by forming the circuits 6, 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device, and particularly to the configuration of a pipelined arithmetic device.

Normally, an arithmetic unit with a pipeline structure is constructed by serially connecting a plurality of arithmetic processing units arranged in a predetermined order according to the flow of processing with a pipeline bus, and a series of processing is performed as described above. I, arranged like
- There was a tendency for the hardware units to become fixed in line. Therefore, it is extremely difficult to use the units in the pipeline to perform a process different from the series of processes defined by the pipeline or a different process flow. Even if it were possible, it had the drawback of drastically reducing the efficiency of the original pipeline/function.

An object of the present invention is to provide an arithmetic device that uses a fixed pipeline unit to perform processing different from the predetermined processing or processing of a different flow. A parallel bus is provided that connects the plurality of connected arithmetic units in parallel with each other, and a control mechanism that controls input and output of data to the pipeline bus and the parallel bus is connected to the two types of buses,
By including a bus control instruction that determines which bus to use in a group of instructions that pass through the bus, a series of processes specified by the pipeline can be executed without significantly reducing the efficiency of the pipeline arithmetic unit. It is possible to execute different processing or a different flow of processing.

In addition to the pipeline bus, the present invention includes a parallel bus that connects each pipeline operation unit in parallel, and a control mechanism that controls the flow of the pipeline and the input and output from the bus.
In order to include bus control instructions, the following configuration was adopted.

1) One piece of data is set through a parallel bus to any unit connected to the pipeline bus, so that data can be supplied to any selected unit.

2) A means for outputting data from each pipeline unit to a parallel bus is provided so that data is output at a timing different from the timing determined by the pipeline cycle.

3) A means is provided to intentionally generate an empty pipeline cycle in which no valid processing input is given at the input end of the pipeline, so that any unit -\ can be accessed, and interrupts etc. Enabled emergency processing.

4) In 3 above, a control mechanism is provided to control the priority of interrupt processing via the parallel bus in the middle of the pipeline, thereby strengthening the interrupt processing function.

5) A device XLa having means for electrically isolating any section of the bus.

Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the present invention. As an example, four processing units 1 to 4 are provided in the pipeline, each connected by a pipeline 5, and each unit is separately connected to the pipeline. Parallel buses 6 connected in parallel are provided, and two buses 5 and 6 are provided with an input control circuit 7. Data that undergoes a series of processing specified in the pipeline (hereinafter referred to as
The pipeline data (referred to as pipeline data) passes through the pipeline bus 5 via the input control circuit 7, undergoes a series of pipeline processing according to the flow determined by units 1 to 4, and is output from the final stage pipeline bus. be done. On the other hand, data that undergoes processing other than the series of processing specified by the pipeline (hereinafter referred to as interrupt data) passes through the input control circuit 7 and is transferred via the parallel bus 6 to the processing units 1 to 4.
The specified unit will be processed. Figure 2 is the first
FIG. 2 is a state transition diagram of a pipeline having the configuration shown in the figure.

1 to 4 correspond to each processing unit in FIG. 1, and 5 corresponds to a pipeline bus. In this figure, 100H is a flowchart in which pipeline data flows through the pipeline, is processed and transferred, and bigline data is processed during the processing time determined for each unit (hereinafter referred to as pipeline cycle).
The flow is processed in the order of 1 → 2 → 3 → 4 for each time. In this state, data to be processed (hereinafter referred to as valid data) is input to each processing unit at any time.

Next, a case where a special processing request is input to the input control circuit 7 will be explained. The input control circuit 7 makes the pipeline data wait for one pipeline cycle, that is, stops inputting to the first-stage unit, and sends a state without valid data (empty state) into the pipeline. The free state is the same as the state where valid data is required, and the pipeline is set to 1.
→ It flows as 2 → 3 → 4. The person who caused this condition was 1.
01 to 104. In the figure, black circles indicate states with ringing data, and white circles indicate idle states. The interrupt data is input via the parallel bus to a vacant processing unit created by the input control circuit 7, and a predetermined process is performed on that unit. In FIG. 2, processing unit 1 at 101, processing unit 2 at 102, processing unit 3 at 103, and processing unit 4 at 104 have this empty state and are in a state where processing based on interrupt data is possible. ing. Interrupt data is processed according to each instruction when the valley processing unit is idle.

As described above, when interrupt data that requires special processing is input, the input control circuit determines this and selects the barrer according to the processing of the interrupt data and the priority of the processing. Create an empty state by preventing input of line data. Interrupt data is input to the unit from the bus and processed when the unit that performs the processing specified by the instruction is in an idle state. After the processing, the processed interrupt data flows through the pipeline or is output to the parallel bus, depending on the instruction. Interrupt data and pipeline data can be easily distinguished by the input control circuit 7 by providing identification pits. Further, to determine which unit the interrupt data is transferred to, it is sufficient to assign an address to the unit. By transferring the interrupt data along with this address to the parallel bus, and each unit comparing the address on the bus with the address assigned to itself, each unit receives the interrupt data i.
-I (I) can be cut independently from lJ.

Note that the vacant status setting may be made not only for one item but also for a plurality of items in succession. Furthermore, regarding priority determination, for example, a priority focus may be added to the data, or the input control circuit 7 determines the priority order, creates a unit address according to that order, and sends it to the parallel bus. All you have to do is transfer it.

In other words, parallel buses may be selectively separated between units (bus separators). In this way, it is possible to input data from one data 2 bus to the processing unit and output it using another part that has been separated, thereby making it possible to perform processing with high efficiency.

As explained above, the present invention provides a bus structure that connects pipeline units in parallel, and a control mechanism that controls the C or merging of biplin data and bus data,
Furthermore, by controlling this with bus control instructions, the efficiency of the pipeline itself is not reduced.
By using any processing unit in the pipeline, it is possible to perform processing different from the series of processing defined by the pipeline hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system 7 according to one embodiment of the present invention. 1 to 4...Processing units in the pipeline, 5
...Pipeline, 6...Bus, 7.
...Input control circuit. FIG. 82 is a state transition diagram of the nine pipelines shown in FIG. 1 to 4...Processing units in the pipeline, 5
...Pipeline, 100...) Diagram of flow in pipeline of pipeline data, 101~
104... Transition diagram of free state for each pipeline cycle time, ■... State with valid data, ... Free state.

Claims (1)

[Claims] A plurality of arithmetic units, a first bus mechanism that connects them in series, a second bus mechanism that connects them in parallel, and a bus that is connected to the first bus mechanism and the second bus mechanism. 1. An arithmetic processing device comprising: a control device; and data to be processed by the bus control device is selectively transferred to the first and second bus mechanisms.