JPS59207746A - Circuit device for generating stable fixed frequency - Google Patents
Circuit device for generating stable fixed frequencyInfo
- Publication number
- JPS59207746A JPS59207746A JP59083077A JP8307784A JPS59207746A JP S59207746 A JPS59207746 A JP S59207746A JP 59083077 A JP59083077 A JP 59083077A JP 8307784 A JP8307784 A JP 8307784A JP S59207746 A JPS59207746 A JP S59207746A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- oscillator
- value
- stage
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、基準周波数を用いて安定した周波数を発生す
る装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for generating stable frequencies using a reference frequency.
従来技術
公知のように、カラーテレビ受像機で色信号を復調する
ためには、正確かつ安定した固定周波数が必要である。As is known in the art, an accurate and stable fixed frequency is required to demodulate the color signal in a color television receiver.
この場合、発生した固定周波数は乗算器に加えられ、乗
算器の他の入力側には変調された色信号が供給されろ。In this case, the generated fixed frequency is applied to a multiplier, the other input of which is fed with a modulated color signal.
そして乗算器の出力側から、復調された色信号が取出さ
れる。復調の結果、およびその精度ないし品質は、固定
周波数に依存して決１ろ。現在では、このような周波数
は、はとんど、電圧制御発振器（ＶＣＯ） Ｙ用いてフ
ェーズ・ロック・ループ回路（ＰＬＬ ）で発生されろ
。このＰＬＬ回路は、できる限り一定の基準周波数を必
要とし、その際ループの精度はこの基準周波数の精度に
依存する。はとんどの場合、この基準周波数は水晶を用
いて供給されろ。The demodulated color signal is then extracted from the output side of the multiplier. The result of demodulation, and its accuracy or quality, depends on the fixed frequency. Currently, such frequencies are most often generated in phase-locked loop circuits (PLLs) using voltage-controlled oscillators (VCOs). This PLL circuit requires a reference frequency that is as constant as possible, the accuracy of the loop depending on the accuracy of this reference frequency. In most cases, this reference frequency will be provided using a crystal.
発明が解決しようとする問題点
しかしながら水晶は高価なので、」−述した回路に要す
るコストは高くなる。PROBLEM SOLVED BY THE INVENTION However, since crystals are expensive, the cost of the circuit described above is high.
本発明の課題は、高価な水晶を用いなくても高い周波数
安定性が得られるように、冒頭で述べた装着を改良する
ことである。The object of the invention is to improve the mounting mentioned at the beginning in such a way that a high frequency stability is obtained without the use of expensive crystals.
問題点を解決するための手段
本発明によればこの課題は、特許請求の範囲第１項に記
載した装置によって解決される。Means for solving the problem According to the invention, this problem is solved by the device according to claim 1.
（６）
実施例の説明
次に図面を参照しながら実施例について本発明の詳細な
説明する。この実施例では、カラーテレビ受像機の基準
発振器に対する制御電圧を発生する。(6) Description of Embodiments Next, the present invention will be described in detail with regard to embodiments with reference to the drawings. This embodiment generates a control voltage for a reference oscillator of a color television receiver.
第１図は１本発明てよろ装置の実施例のブロック図であ
る。ここで発振器１は、固定の周波数Ｆケ発生するため
に用いられろ。周波数Ｆは乗算段２に加えられろ。乗算
段２の別の入力側には復調すべき色信号ＦＲ，ＦＢが加
えられろ。FIG. 1 is a block diagram of an embodiment of the arming device of the present invention. Here, oscillator 1 is used to generate a fixed frequency F. Add frequency F to multiplication stage 2. The color signals FR, FB to be demodulated are applied to the other inputs of the multiplication stage 2.
乗算段２の出力側からは、復調色信号ＲまたはＢが取出
されろ。復調信号は殴３にも加えられる。段３の他の入
力側には、発振器１に対する制御直流電圧が供給されろ
。この電圧についてハ後で詳しく説明する。デジタル−
アナログ変換器１３から供給されろこの電圧は、次のよ
うにして得られろ。A demodulated color signal R or B is taken out from the output side of the multiplication stage 2. The demodulated signal is also added to Hit 3. The other input of stage 3 is supplied with a control DC voltage for oscillator 1. This voltage will be explained in detail later. Digital-
This voltage supplied from the analog converter 13 can be obtained as follows.
寸ず、走査線周波数に近い周波数Ｆ。が、段４、 ５．
６および７から成ろ分周器列を介して分周される。図示
の例では、周波数Ｆ。＝６２（４）
５００ Ｈ７である。この周波数は、分周器４によって
％に分周され、次続の段によってン。The frequency F is close to the scanning line frequency. However, stage 4, 5.
The frequency is divided through a filter frequency divider array consisting of 6 and 7. In the illustrated example, the frequency F. =62(4) 500 H7. This frequency is divided by a frequency divider 4 to % and then divided by the next stage.
に
１ρ分周される。図示の例では、Ｄ−６２である。分周
比の逆数りは、発振器が発生する周波数の分解能を決定
する。この分周によって、持ｉ時間５１２μＳのゲート
パルスが得られる。The frequency is divided by 1ρ. In the illustrated example, it is D-62. The reciprocal of the frequency division ratio determines the resolution of the frequencies generated by the oscillator. By this frequency division, a gate pulse having a duration i of 512 μS is obtained.
ケゞ−トパルスは、ケゞ−ト回路８に加えられる。The gate pulse is applied to gate circuit 8.
デート回路８は、ケゞ−トパルスの期間だけ開く。The date circuit 8 is open only during the gate pulse.
それによって、発振器１の発生したパルスがゲート８を
通過し、カウンタ９に加えられろ。カウンタ９はパルス
を測定、ないしは加算する。Thereby, the pulses generated by the oscillator 1 pass through the gate 8 and are added to the counter 9. Counter 9 measures or adds up the pulses.
計数結果Ｍは比較段１０の入力測知供給され、比較段は
入力値Ｍと設定値ＰＹ比較する。設定値Ｐは値りとＲの
債から得られろ。ここで値Ｒは、発振器１の発生した設
定周波数と、分周器４から供給される周波数との比であ
る。図示の例では、Ｒ＝Ｆ／ −４４３３／６２．５
＝７０゜０
９２である。従って、値ＰはＤＸＲ，：３２Ｘ７０．９
２ ＝ ２２７０である。The counting result M is supplied to the input measurement of a comparator stage 10, which compares the input value M with a set value PY. The set value P can be obtained from the price and the bond R. Here, the value R is the ratio between the set frequency generated by the oscillator 1 and the frequency supplied from the frequency divider 4. In the illustrated example, R=F/-4433/62.5
=70°092. Therefore, the value P is DXR, :32X70.9
2 = 2270.
比較結果Ｍ−Ｐは、別の加算段１１で、直前に計算され
た値Ｎに加算され、その結果は第１のレジスタ（ラッチ
）１２に送られろ。このレジスタ１２はパルスＰ１によ
って導通制御さね、その出力側にデジタ）ｖ端Ｎが生じ
ろ。デジタル値Ｎはデジクルーアナログ変換器１３て供
給され、アナログ制御電圧■。Ｋ変換される。この制御
電圧■ｏによって発振器１が追従制御され、変化した周
波数Ｆが発生する。デジタル値Ｎは第２のレジスタ（ラ
ッチ）１４にも加えられる。The comparison result M-P is added to the previously calculated value N in another addition stage 11 and the result is sent to the first register (latch) 12. The conduction of this resistor 12 is controlled by the pulse P1, and a digital (V) terminal N is generated on its output side. The digital value N is supplied by the DigiCrew analog converter 13 and the analog control voltage ■. K-transformed. The oscillator 1 is subjected to follow-up control by this control voltage ■o, and a changed frequency F is generated. The digital value N is also applied to a second register (latch) 14.
このレジスタ１４の内容はパルスＰ２の制御によって、
加算段１１の第２の入力側て加えられる。２つの制御信
号ｐ１．ｐ２の発生とその時間関係については、第２図
から明らかである。The contents of this register 14 are controlled by pulse P2.
It is added at the second input of the summing stage 11. Two control signals p1. The occurrence of p2 and its time relationship are clear from FIG.
カウンタ９は、Ｐ２パルスによって再びリセットされ、
ゲート８の開放後に新たな計数過程が開始されろ。発振
器１の新たに検出された周波数Ｆは、計数後に同じく比
較段１０に加えられる。ここで計数結果Ｍは設定値Ｐと
比較され、その結果は加算段１１に供給されろ。この比
較結果はレジスタ１２を介してデジタルーアナログ変換
器１３に加えられ、変化した制御電圧■。Counter 9 is reset again by P2 pulse,
After opening gate 8 a new counting process is started. The newly detected frequency F of the oscillator 1 is also applied to the comparator stage 10 after counting. Here, the counting result M is compared with the set value P, and the result is supplied to the addition stage 11. This comparison result is applied to the digital-to-analog converter 13 via the register 12, and the changed control voltage (2) is applied.
が得られる。比較段１０から値りが取出さ、ｔ″１．た
場合、それはレジスタ１４７１１１１−介して入力され
る以前の［］−げに加算されろ。つ１す、この時点にお
いては、発振器１０発生する周波数を変化させろ必要が
なく、従って制御過程は終了する。is obtained. If a value is taken from the comparator stage 10 and t''1., it is added to the previous value inputted through the register 1471111.At this point, the frequency generated by the oscillator 10 is There is no need to change , so the control process ends.
この装置では、周波数ケ発生する際てデジモル化ケ行な
うので、正確な周波数Ｆが得られた時でも、比較段１０
から到来する比較結果はデジタル値１を有しており、こ
の値て応じて周波数が追従制御されてし１う。従って、
比較結果がデジクル値１の分だけ設定値から偏移し、周
波数が変動することを防止する必要がある。この目的で
、比較器１０の後に検出器１５が接続されている。検出
器１５は、比較結果がデジタル値１の時には、ＮＯＴケ
ゞ−ト１６およびＡＮＤ ｒ”−１−１７を介してＰ１
パルスを阻止する。こうして、レジスタ１２の導通接続
が防止されろ。In this device, when frequency F is generated, it is digitalized, so even when accurate frequency F is obtained, comparison stage 10
The comparison result coming from has a digital value of 1, and the frequency is tracked accordingly. Therefore,
It is necessary to prevent the comparison result from deviating from the set value by the digital value 1 and causing the frequency to fluctuate. For this purpose, a detector 15 is connected after the comparator 10. When the comparison result is a digital value of 1, the detector 15 outputs P1 via the NOT gate 16 and AND r''-1-17.
Block the pulse. In this way, conductive connection of resistor 12 is prevented.
ケゝ−ト１８．Ｍｌは、第２図に示すパルスＰ１＝ Ａ
ＢＣおよびＰ ２ ＝ ＡＢＣを発生するために用い（
７）
られろ。Kate 18. Ml is the pulse P1=A shown in FIG.
used to generate BC and P 2 = ABC (
7) Let it go.
次に、第６図を参照しながら上述の装置の動作について
説明する。この実施例では、計数結果Ｍは関数Ｍ＝ｆ（
Ｎ）に従って得られる。つ１す、計数結果Ｍはデジタル
−アナログ変換器１３へ供給されろデジタル情報Ｎに、
従って制御電圧ｖｏＫ依存し、発振器１０周波数Ｆもこ
の制御電圧■。に依存している。１ず、Ｎ＝５、つ捷り
Ｍ＝２２７０ｖ設定値と考えろ。Next, the operation of the above-mentioned apparatus will be explained with reference to FIG. In this example, the counting result M is a function M=f(
N). First, the counting result M is supplied to the digital-to-analog converter 13, and the digital information N is
Therefore, the oscillator 10 frequency F also depends on the control voltage voK. depends on. 1. Consider that N=5 and the switching value M=2270v.
最初にこの装置が、Ｍ＝２２６３になるよって周波数Ｆ
を調整したとする。所定の固定設定値がＰ＝２２７０な
ので、比較段１０は値−７を発生する。この値は、加算
段１１の中で値Ｎ＝１５に加算され、値８を生じろ。こ
の新しい値Ｎ−８から、少し高い周波数Ｆが発生し、そ
れは計数結果として値Ｍ＝２２６８を供給する。Initially, this device has a frequency F since M=2263.
Suppose that we adjust Since the predetermined fixed set point is P=2270, the comparator stage 10 generates the value -7. This value is added to the value N=15 in addition stage 11, yielding the value 8. From this new value N-8, a slightly higher frequency F is generated, which provides the value M=2268 as the counting result.
この−合の比較結果は−２である。値−２は直前の値Ｎ
＝３と加算されて、新しい値Ｎ＝６＆生じろ。それによ
って、値Ｍ＝２２６９が供給されろ。カウンタ９がリセ
ットさね、もう１度（８）
測定が行なわれた後で、比較段１０は値−１を供給し、
それから新しい値Ｎ＝５が生じろ。発振器１は、この値
の時に設定周波数に調整される。従ってカウンタ９は値
Ｍ＝２２７０’＆供給し、比較段におけろ差はＤとなる
。つまり、装置は完全圧制御さ扛たことになる。The comparison result for this case is -2. The value -2 is the previous value N
=3 to yield a new value N=6&. Thereby the value M=2269 will be provided. After the counter 9 has been reset and one more measurement (8) has been made, the comparator stage 10 supplies the value -1;
Then a new value N=5 arises. Oscillator 1 is tuned to the set frequency at this value. Therefore, the counter 9 supplies the value M=2270'&, and the difference becomes D in the comparison stage. In other words, the device is under complete pressure control.
安定性を保つために、関数Ｍ＝ｆ（Ｎ）の勾配ｄＭ／ｄ
Ｎは負であり、また振動を防上するために勾配の鎖は１
より小さくなっている。To maintain stability, the slope dM/d of the function M=f(N)
N is negative and the gradient chain is 1 to prevent vibrations.
It's smaller.
比較値Ｐの値ゆ発振器１が発生する周波数に依存してい
る。従って、発振器がＰＡＬ信号、ＳＥＣＡＭ信号ない
しＮＴＳＣ信号のうちどれを復調するために周波数を発
生するか、ということに応じて、比較値Ｐの大きさは異
なる。比較値Ｐと分周比の逆数りが固定されていれば２
つの周波数の比ＦＯ／ＦはＤ／ｐ Ｋ比例する。従って
、所与の値から基準周波数Ｆ。を容易に検出することが
できる。The value of the comparison value P depends on the frequency generated by the oscillator 1. Therefore, the magnitude of the comparison value P varies depending on whether the oscillator generates a frequency for demodulating a PAL signal, a SECAM signal, or an NTSC signal. 2 if the comparison value P and the reciprocal of the division ratio are fixed.
The ratio of the two frequencies FO/F is proportional to D/pK. Therefore, from a given value the reference frequency F. can be easily detected.
第１図の例では、データを並列に処理しているが、直列
処理な行なうことも可能である。In the example of FIG. 1, data is processed in parallel, but serial processing is also possible.
発明の効果
本発明（（よれば高価な水晶等を使用せず、周波数の発
生の制御の一部をディジタル的に処理し、その際の誤制
御を回避することと共に、回路て要する費用を低減でき
る効果がある。Effects of the Invention According to the present invention, part of the control of frequency generation is processed digitally without using expensive crystals, avoiding erroneous control at that time, and reducing the cost required for the circuit. There is an effect that can be done.
第１図は本発明による周波数発生装置の実施例のブロッ
ク図、第２図は第１図の装置の説明に供する波形図、第
６図は第１図の装置の動作を説明するための線図である
。
１・・・電圧制御発振器、２・・・乗算段、４・・・分
周器、８・・・ｒ−ト回路、９・・・カウンタ、１０・
・比較段、１１・・・加算段、１２．１４・・・レジス
タ、１３・・・ヂジタ）ｖ／アナログ変換器、１５・・
・検出器、１５−・・ＮＯＴ ｒ −）、１７−＝ Ａ
ＮＤ ｒ −）、１８．１９・・・ｒ−ト。FIG. 1 is a block diagram of an embodiment of the frequency generator according to the present invention, FIG. 2 is a waveform diagram for explaining the device in FIG. 1, and FIG. 6 is a line diagram for explaining the operation of the device in FIG. 1. It is a diagram. DESCRIPTION OF SYMBOLS 1... Voltage controlled oscillator, 2... Multiplication stage, 4... Frequency divider, 8... r-to circuit, 9... Counter, 10...
- Comparison stage, 11... Addition stage, 12.14... Register, 13... Digit) v/analog converter, 15...
・Detector, 15-...NOT r-), 17-=A
ND r-), 18.19...r-t.
Claims (1)
回路装置において、基準周波数（ＦＯ）が、発生しよう
とする周波数（、Ｆ）よりも低い周波数であり、またケ
ゞ−ト回路（８）が設けられ、該ケゝ−ト回路が、低い
基準周波数（Ｆｏ）’Ｙ分周して得られる’７”−）信
号によって開かれ、ケゞ−ト回路（８）の入力側に電圧
制御発振器（１）が接続され、またデート回路（８）が
カウンタ（９）と接続され、該カウンタが、）ｆ−＋−
回路（８）の導通時に発振器（１）から取出されろパル
スを計数し、その計数結果が比較段（１０）に加えられ
、該比較段には所定の固定比較値（Ｐ）も供給され、ま
た比較段（１０）の出力側が加算段（１１）と接続され
、該加算段が、算出さｒＬｌこ値を一時記憶する第１の
レジスタ（１２）と接続され、該第１のレジスタ（１２
）がデジタル−アナログ変換器（１３）と接続され、該
デジタル−アナログ変換器が、発振器（１）を制御する
ために該発振器の制御入力側と接続され、また第１のレ
ジスタ（１２）が第２のレジスタ（１４）と接続され、
該第２のレジスタが加算段（１１）の別の入力側と接続
され、さらに２つのレジスタ（１１，１４）がラッチ・
レジスタとして交互に導通制御されろ、ことを特徴とす
る安定した固定周波数を発生する回路装置。1. In a circuit device that generates a stable fixed frequency using a reference frequency, the reference frequency (FO) is lower than the frequency to be generated (, F), and the gate circuit (8) is A voltage controlled oscillator is connected to the input side of the gate circuit (8). (1) is connected, and the date circuit (8) is connected to the counter (9), and the counter is )f-+-
counting the pulses taken from the oscillator (1) when the circuit (8) is conducting and applying the counting result to a comparison stage (10), which is also supplied with a predetermined fixed comparison value (P); Further, the output side of the comparison stage (10) is connected to an addition stage (11), and the addition stage is connected to a first register (12) for temporarily storing the calculated value.
) is connected to a digital-to-analog converter (13), which is connected to the control input of the oscillator (1) for controlling the oscillator (1), and a first register (12) is connected to the control input of the oscillator (1). connected to the second register (14);
The second register is connected to another input of the adder stage (11), and two further registers (11, 14) are connected to the latching register (11, 14).
A circuit device for generating a stable fixed frequency, characterized in that conduction is controlled alternately as a resistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19833314973 DE3314973C1 (en) | 1983-04-26 | 1983-04-26 | Circuit arrangement for generating a stable fixed frequency |
| DE33149739 | 1983-04-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59207746A true JPS59207746A (en) | 1984-11-24 |
| JPH0754906B2 JPH0754906B2 (en) | 1995-06-07 |
Family
ID=6197329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59083077A Expired - Lifetime JPH0754906B2 (en) | 1983-04-26 | 1984-04-26 | Circuit device that generates stable fixed frequency |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0754906B2 (en) |
| DE (1) | DE3314973C1 (en) |
| FR (1) | FR2545300B1 (en) |
| NL (1) | NL8401283A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6310823A (en) * | 1986-05-30 | 1988-01-18 | アールシーエー トムソン ライセンシング コーポレーシヨン | Phase-locking loop system |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4694327A (en) * | 1986-03-28 | 1987-09-15 | Rca Corporation | Digital phase locked loop stabilization circuitry using a secondary digital phase locked loop |
| EP0278140A1 (en) * | 1987-02-12 | 1988-08-17 | Hewlett-Packard Limited | Clock signal generation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636234A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Ind Co Ltd | Frequency following type voltage control oscillating unit |
| JPS5717235A (en) * | 1980-07-04 | 1982-01-28 | Sansui Electric Co | Frequency controlling oscillator |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3555446A (en) * | 1969-01-17 | 1971-01-12 | Dana Lab Inc | Frequency synthesizer |
| US3582810A (en) * | 1969-05-05 | 1971-06-01 | Dana Lab Inc | Frequency synthesizer system |
| GB1268322A (en) * | 1970-10-19 | 1972-03-29 | Mullard Ltd | Automatic frequency control system |
| US3913028A (en) * | 1974-04-22 | 1975-10-14 | Rca Corp | Phase locked loop including an arithmetic unit |
| FR2294587A1 (en) * | 1974-12-11 | 1976-07-09 | Cit Alcatel | Freq. locking cct. for measuring signal distortion - locks oscillator, output counted during input signal presence to input signal |
| JPS5469018A (en) * | 1977-11-11 | 1979-06-02 | Sony Corp | Color demodulator circuit |
-
1983
- 1983-04-26 DE DE19833314973 patent/DE3314973C1/en not_active Expired
-
1984
- 1984-04-19 NL NL8401283A patent/NL8401283A/en not_active Application Discontinuation
- 1984-04-26 FR FR8406557A patent/FR2545300B1/en not_active Expired
- 1984-04-26 JP JP59083077A patent/JPH0754906B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636234A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Ind Co Ltd | Frequency following type voltage control oscillating unit |
| JPS5717235A (en) * | 1980-07-04 | 1982-01-28 | Sansui Electric Co | Frequency controlling oscillator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6310823A (en) * | 1986-05-30 | 1988-01-18 | アールシーエー トムソン ライセンシング コーポレーシヨン | Phase-locking loop system |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2545300A1 (en) | 1984-11-02 |
| DE3314973C1 (en) | 1984-07-19 |
| NL8401283A (en) | 1984-11-16 |
| FR2545300B1 (en) | 1987-06-19 |
| JPH0754906B2 (en) | 1995-06-07 |
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