JPS59206954A - Data processing device with tracing function - Google Patents

Abstract

PURPOSE:To utilize effectively a memory element, by preparing plural tracer memory groups of a narrow bit width and small capacity and connecting then in parallel or in series depending on the condition. CONSTITUTION:A data processing circuit is composed of tracer memories 1 and 2, a selection indicating circuit 3, an NOT circuit 4, an address register 6, an adder circuit 7, an AND circuit 8, a tracer memory change-over controlling FF circuit 9, OR circuits 5, 10, and 11, a multiple selection circuit 12, etc. The tracer memory change-over control FF circuit 9 is controlled by the overflow signal of the address register 6 and generates the write enable signal of the tracer memories 1 and 2. The tracer memories 1 and 2 are connected in parallel or in series by means of the output of the OR circuits 10 and 11, into which the write enable signal and a signal indicating the tracer bit width are inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a data processing device having a trace function.

[Prior art]

Conventionally, in a data processing device with a trace function, the tracer memory has a fixed bit width and capacity. Furthermore, since the memory capacity is large, the configuration becomes large-scale and expensive.

[Purpose of the invention]

An object of the present invention is to provide a plurality of tracer memories each having a bit width W1 and a bit capacity iD, and to connect the tracer memories in parallel or in cascade using a bit width switching signal, in order to improve such conventional drawbacks. By doing this, it is possible to configure various tracer memories with a bit width nW (n is a natural number), a bit capacity, and a bit width W1 and a bit capacity nDi depending on the situation, making it possible to collect useful information. An object of the present invention is to provide a data processing device having a tracing function.

[Structure of the invention]

According to the present invention, a plurality of tracer memories, a switching circuit for switching data input signals, an address register for supplying addresses to the tracer memories, an adder circuit for adding output signals of the address registers, and a writing circuit for the tracer memories are provided. A tracer memory switching control flip-flop controlled by an overflow signal of the address register to generate a permission signal, and an OR circuit to which an output signal of the flip-flop and a signal specifying a trace bit width are input. A data processing device having a trace function, characterized in that the tracer memories are connected in parallel or in cascade under the control of the OR circuit.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Referring to FIG. 1, this embodiment includes tracer memories 1 and 2, a selection instruction circuit 3, a negative circuit 4, an address register circuit 6,
Addition circuit 7, AND circuit 8, tracer memory switching control flip-flop circuit 9, and OR circuit 5.10.1
1 and a multiple selection circuit 12.

The basic clock input signal 101 is sent to the address register 6,
The trace memory write signal 102 is input to the trace memory switching control flip-flop circuit 9, and the trace memory write signal 102 is input to the trace memory circuit 1 and the L'-1-memory circuit 2. The data input signal 103 is input to the tracer memory circuit l and the OR circuit 5, and the data input signal 104 is input to the logic OR circuit j.
Enter into NJ5.

The trace bit width switching signal 105 is transmitted through the NOT circuit 4, the OR circuit 5, the OR circuit 10, and the 11th logic circuit 11.
Enter.

The output signal 107 of the NOT circuit 4 is input to the OR circuit 5, the OR circuit IO, and the OR circuit 11.

The output signal 108 of the OR circuit 5 is transmitted to the tracer shaving circuit 2.
The output signal 109 of the tracer memory circuit 1 and the output signal 110 of the tracer memory circuit 2 are input to the multiple selection circuit 1.
Enter 2.

The output signal 111 of the address register 6 is input to the tracer memory circuit 1, the tracer memory circuit 2, and the power supply circuit 7, and the output signal 111 of the address register circuit 6 is
is input to the AND circuit 8.

The output signal 113 of the adder circuit 7 is input to the address register 6, the output signal 114 of the AND circuit 8 is input to the trace memory switching control flip-flop circuit 9, and the output signal 115 of the trace memory switching control flip-flop circuit 9 is input to the logic f3! The signal is input to the product circuit 8 and the OR circuit 10, and the output signal 116 is similarly input to the OR circuit 11.

The output signal 117 of the OR circuit 10 is input to the tracer memory circuit 1, and the output signal 118 of the OR circuit 11 is input to the tracer memory circuit 2. The input signal 106 is input to the selection instruction circuit 3, the output signal 119 of the selection instruction circuit 3 is input to the multiple selection circuit 12, and the output signal 120 of the multiple selection circuit 12 is taken into the device.

The operation of the embodiment shown in FIG. 1 will be described below assuming that the bit width of the tracer memory circuit 5 is W bits and the bit capacity is D words.

■ When tray memory circuit 1 and tracer memory circuit 2 are connected in parallel with a bit width of 2W and a bit capacity of
Figure (a)).

At this time, the bit width switching signal 105 is input at II 1#. When the power is turned on, all circuits are initialized. When the tracer operation is started, the data input signal 103 is supplied to the tracer memory circuit 1, and the data input signal 104 is supplied to the tracer memory circuit 2. Since the bit width switching signal 105 is 0'1'', the commitment enable signals 117 and 118 of the tracer memory circuit 1 and the tracer memory circuit 2 are 1'', and the data can be written. Since the address register circuit 6 has been initialized, it is in the "OO" state.

When the basic clock input 101 and the tracer memory write signal 102 are inputted in this state, the contents of the data input signals 103 and 104 are written into addresses 6-00 of the tracer memory circuits 1 and 2, respectively. Subsequently, when the basic clock signal 101 and the tracer memo IJW signal 102 are input,
Each L of tracer memory circuit 1 and tracer memory circuit 2
The contents of data input signals 103 and 104 are written to address IO131. In this way, the basic clock input signal 101
Each time the tracer memo IJW signal 102 is inputted, the address register circuit 6 continues to be sequentially incremented by 1 by the adder circuit 7.

Eventually, when the address register circuit 6 starts to reach %N al111'', the overflow instruction signal 112 of the address register circuit 6 is output, and the trace memory switching control flip circuit 9 is set to II l# through the AND circuit 8. However, the bit This signal is not used during 2W width operation.

Also, at this time, if the trace operation stop signal does not become active, the address register circuit 6 is 'allO'''
data input signal 103 and data input signal 104 are rewritten to trace memory circuit 1 and tracer memory circuit 2. This operation continues until a trace operation stop instruction signal is generated.

■ When the tracer memory circuit 1 and the tracer memory circuit 2 are connected in cascade, and the bit width is W1 and the pit is 2D (
In this case, the waveform diagram of each part is shown in FIG. 3.

3(a) to 3(i) are waveform diagrams of portions with the same symbols in FIG. 1, respectively.

At this time, the bit width switching signal 105 is input as '0''. When the tracer operation is started, the tracer memory lltM
1 is supplied with the data input signal 103. Since the trace memory switching control flip-flop circuit 9 is tt O#l, the output signal 115 becomes 'l', the logic circuit output signal 117 becomes at1$1, and only the tracer memory circuit 1 is in the storage possible state. Since the address register circuit 6 has been initialized, it is in the Nl 00 I+ state.

When the basic clock signal 101 and the tracer memory input signal 102 are input in this state, the contents of the data input signal 103 are written into the tracer memory circuit 1 at address ``00''. Subsequently, when the basic clock signal 101 and the tracer memory write signal 102 are input, the contents of the data input signal 103 are written to the address '01''.In this way, the basic clock signal 101 and the tracer memory write signal 1
Each time 02 is input, the address register circuit 6 continues to be sequentially incremented by 1 by the adder circuit 7.

Eventually, when the address register circuit 6 becomes -all, the address register circuit 60 overflow instruction signal 112 is output, and the trace memory switching control flip-flop circuit 9 is set to "1" through the AND circuit 8.This causes the logic The output signal 117 of the summation circuit 10 is “
``0'', writing to the tracer memory circuit 1 is prohibited, and at the same time, the output signal 118 of the OR circuit 11 becomes ``1'''', allowing writing to the tracer memory circuit 2. At this time, the address The register circuit 6 is "all"
O”.

Subsequently, when the basic clock signal 101 and the tray 9-1 write signal 102 are input, the contents of the data input signal 103 are written to the tracer memory circuit 20'00'' address via the OR circuit 5. Thereafter, the address register circuit 6 continues to be incremented by 1, and the contents of the data input signal 103 are written to all addresses.

When the address register circuit 6 becomes "al l l", the overflow instruction signal 112 is output, and the trace memory switching control flip-flop circuit 9 becomes "ls".
From z to u 01', output signal 1 of OR circuit 11
18 becomes "0", and the write operation to the tracer memory circuit 2 is prohibited.At the same time, 1=g, the output signal 117 of the OR circuit 10 changes from "0" to 1# again, and a trace operation stop signal is generated. If not, the contents of the data input signal 103 are written again from address "00" of the tracer memory circuit 1. These operations continue until a trace operation stop signal is generated.

In this way, by preparing a plurality of small bit width, small capacity tracer memories, and making it possible to connect the tracer memories in parallel or cascade using a bit width switching signal, the memory element can be We have collected a wide range of information that can be used effectively and be beneficial depending on the situation.
Enables data search and speeds up information analysis.
It becomes possible to improve the operating rate of the device.

〔Effect of the invention〕

As explained above, the present invention utilizes a plurality of tracer memory groups with a small pit width and a small capacity, and has a configuration that allows multiple parallel connections or cascade connections depending on the situation, thereby making the memory element effective. This makes it possible to collect useful data in one go, speed up information analysis, and improve the operability of the equipment.

[Brief explanation of drawings]

Figure 1 is a basic block diagram of an embodiment of the present invention, Figure 2 (
a) and (b) are diagrams explaining the two states of the connection, the third
The figure shows a waveform diagram of the operations performed in FIG. 1.2... Tracer memory circuit, 3...
- Selection instruction circuit, 4...Negation circuit, 5, 10.
11...OR circuit, 6...address register circuit, 7...addition circuit, 8...
- AND circuit, 9... tracer memory switching control flip-flop circuit) 12°°°°°° multiple selection circuit. 360- (α) <b> Sheep 2 b

Claims (1)

[Claims] A plurality of tracer memories, a switching circuit that switches data input signals, an address register that supplies addresses to the tracer memories, an adder circuit that adds output signals of the address registers, and generates a write permission signal for the tracer memories. a tracer memory switching control flip-flop controlled by an overflow signal of the address register, and an OR circuit to which an output signal of the flip-flop and a signal specifying a trace bit width are input; A data processing device having a trace function, characterized in that the following are connected in parallel or in cascade under the control of the OR circuit.