JPS59205674A - Matrix multiplication circuit for graphic display - Google Patents

Abstract

PURPOSE:To improve the arithmetic speed by storing plural types of element matrices to an RAM for each element, giving a direct access to an area where a desired element is stored and reading out the element serially by a shift clock to omit the loading process to a shift register. CONSTITUTION:RAM2-17 having areas corresponding to matrix elements M11- M44 are provided to an element matrix data store part 1 to store the elements M11-M44. A high order address counter 18 which selects areas and a low order address counter 19 which reads out the data elements stored in the RAM2-17 are connected to these RAMs. While multipliers Kx-Kw which perform the multiplication of each pair are connected to the output sides of RAM2-17, and adders Nx-Nw are connected to the output sides of multipliers Kx-Kw respectively. Then a direct access is given to a desired area of RAM4-17 with the clock given from a clock signal source, the shift frequency setting signal of a data bus 21, etc. Then desired elements M11-M44 are read out. Thus the arithmetic speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial type matrix multiplication circuit suitable for graphic displays.

As shown in Figure 1, a three-dimensional graphic display enlarges, reduces, rotates, and performs perspective transformation of graphic data transferred from a host computer in response to commands from an input device A such as a keyboard or joystick. This is a device that performs these operations and displays the results on a CRT. In this device, as shown in Fig. 2, point P left (X person, Vc'+
position t object (t point PL+1(XL
+i + Yj+1 + Z; -+1), the matrix multiplier circuit C converts the coordinate matrix data [Xn, ye, ZL.

1′] by the element matrix U, that is, affine transformation, = [x,, 1. YL+1+ "Lq+ ']
Find the transformed coordinate data matrix by
After verifying with a clip circuit whether the coordinate of
The configuration is such that the image is stored in the Plumn tube G and then displayed as a straight-line approximation figure.

Conventionally, as shown in FIG. 3, this matrix multiplication circuit uses a load instruction (m in FIG. 4) to call up the element matrix U required for the operation from the stack memory H storing various element matrices, and calculates each matrix element. Mi
j is temporarily stored in each of the shift registers Jll~J44, and each matrix element Mjj is converted into serial data by a shift clock (TV) and input as a multiplier (V) to the multiplier Kll~44, and the data bus L It was configured to perform serial multiplication using the coordinate matrix [x'j, y, z; -, 1] as the multiplicand. Note that in the figure, symbols N1 to N4 indicate adders that add the multiplication outputs of each column, and Pi to P4 indicate heifer registers, respectively.

By the way, stack memory is a very convenient memory for arithmetic processing that requires frequent updating of stored data, but as mentioned above, each time a multiplication is performed, the multiplier is placed in a shift register via a load instruction. As a result, it takes time T (m in FIG. 4) to input the multiplier to the multiplier, and there is a problem that the calculation time for 1≠−even becomes long.

On the other hand, a graphic display has the characteristic that the number of data in the element matrix U serving as a multiplier is finite, and there is no need to change the data in the memory storing the element matrix.

Focusing on such characteristics, the present invention stores multiple types of element matrices element by element in a random access memory, directly accesses the area where the desired matrix element is stored, and simultaneously serializes it using a shift I clock. It is an object of the present invention to provide a matrix multiplication circuit which can omit loading into a shift register by reading the data into a matrix, thereby improving the calculation speed.

Therefore, the details of the present invention will be explained below based on illustrated embodiments.

FIG. 5 is a block diagram of a circuit showing an embodiment of the present invention, and reference numeral l in the figure represents an element matrix data storage unit which is a special feature of the present invention;
~M44, that is, 16 RAMs 2 to 17, each RAM is divided into 64 areas with 64 bits as one area, as shown in FIG. Each matrix element data [Mij]n constituting one element matrix Un is stored and 6
It is configured so that four types of element matrices can be read out. The output side of each RAM is connected to the multiplier input terminals of multipliers Kxll to Kx44 that execute multiplication of each column, and the address terminals are connected to the upper address terminals All...A6 that select area n and It is divided into two groups of lower address terminals A5...AO for reading element data [Mij]n stored in the RAM, and a common upper address counter is connected to the upper address terminals All...A6 of each RAM. 18 output terminal to the lower address terminal A5.
...AO contains the data of the selected area n [Mij]
Common lower address counter 19 that reads n serially
It is configured by connecting. 20 is a shift counter that receives a clock signal from a clock signal source and a data bus 21;
The shift count determination signal from , and the AND gate 2 described later.
When the signal from 2 is input, and after the start signal is input and the shift count signal is input, the enable signal is sent out until the number of clock signals set by -1 is output. Reference numeral 22 denotes the aforementioned AND gate, which is configured to output a shift clock only during the period when the enable signal is output from the shift counter 20. Note that the symbols Kxll to Kw4 in the figure
4 uses coordinate data from the data bus 21 as a multiplicand,
A multiplier for serially multiplying the multiplier from the element matrix data storage section l is shown, and Nx-Nw shows an adder for adding the outputs from each multiplier and outputting the result to the buffer registers Px to Pw. .

Next, the operation of the circuit configured as described above will be explained based on the timing chart shown in FIG.

When data is input from the keyboard, the lower address counter 19 is cleared (see FIG. 7), and the graphics processor selects a specific required element matrix Un corresponding to this data. Matrix element 1M1l]
n... [M44 RAM 2 to 1 storing n
The address of area n of No. 7 is set in the upper address counter 18 (m). At this point, the shift clock (
IV), the data [Mij]n of the selected area n of each RAM 2 to 17 is read out in serial format starting from the least significant bit LSB according to the timing of the shift clock, and the multiplier K connected to each x 1
Output to the multiplier input terminal of 1 to Kw44 (V). On the other hand,
``Synchronizing with this readout, the multiplier Kx is sent from the data bus 21.
Serial format coordinate data matrix [x, y,
z, l] bit by bit, and the output from the multiplier groups Kx to Kw of each column element is added to the adder K x −K.
The multiplication result, that is, the converted coordinate data matrix [X, Y,
Z.

Output 1.

In this embodiment, the multiplication of a matrix of 4 rows and 4 columns was explained as an example, but when a matrix of m rows and m columns is used as a multiplier, the RAM and the multiplier constituting the storage section are each multiplied by m. You can set them up one by one.

As described above, according to the present invention, RAMs corresponding to the number of matrix elements of an element matrix are provided, each RAM is divided into a plurality of areas, and one element matrix is configured for each same area of each RAM. In addition to storing the matrix elements, the area where the required element matrix is stored is selected by random access and read out serially, which greatly reduces the time required to input the multiplier to the multiplier. This not only allows matrix operations to be performed at high speed, but also eliminates the need for a shift register for serial conversion, improving space performance and reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a graphic display, FIG. 2 is an explanatory diagram showing movement of figures, FIG. 3 is a circuit block diagram showing an example of a conventional matrix multiplication circuit, and FIG. 4 is a block diagram showing an example of a conventional matrix multiplication circuit. , a timing diagram showing the operation of a conventional circuit, FIG. 5, and a block diagram of a circuit showing an embodiment of the present invention, FIG.
The figure is a conceptual diagram showing the structure of the data area of the RAM in the above circuit, and FIG. 7 is a timing diagram illustrating the operation of the above circuit. 1...Element matrix data storage section 2-17...
...RAM 18... Upper address counter 19... Lower address counter Applicant: Daini Seikodai Co., Ltd. Agent Patent Attorney Yasutoshi Nishikawa Katsuhiko Kimura No. 20 No. 3

Claims (1)

[Claims] RA corresponding to the number of elements m2 of a matrix with m rows and m columns
means for dividing M into the same number of areas and storing each element data constituting one matrix for each same area; means for specifying each area of the RAM by an upper address; A matrix multiplication circuit for a graph ink display, comprising means for serially reading an area according to a lower address, and means for using the data read by the means as a multiplier and multiplying it by a multiplicand in a serial format.