JPH01142934A - Information processing circuit - Google Patents

Abstract

PURPOSE:To obtain data which is an integral multiple of data fast without lowering the efficiency of a ROM by providing a readable and writable register or memory where data is written, a circuit which calculates an integral multiple of data, and a readable register or memory where the integer multiple of the data is stored. CONSTITUTION:The magnifying rate of the data to be found is written in a writable register (MW) 7 previously. Then this data is inputted to a multiplier 9 through a control line 9 to determine the magnifying rate of the data to be found. Then the data is written in the readable and writable register (MRW) 5. This data is inputted to the multiplier 9 and the data obtained by multiplying the data by the magnifying rate set in the MW 7 is inputted to the readable register (MR) 6. This is only read out to obtain the target integer multiple of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information processing circuit that can obtain integral multiples of data at high speed.

Conventional Technology Conventionally, when an array is set in memory, in order to make the array variable correspond to an address in memory, the array variable is converted to an address in memory using an addition circuit that adds the array variable or a shift circuit that shifts the array variable. was.

The method of determining the address of the array will be explained below with reference to FIGS. 5 and 6.

Figure 5 is an example of memory array element distribution when each element of the array requires 3 bytes, where 1 is the address on the memory of each array element, 2 is each 3-byte array element, and 3 is the array element. It is the name of (hereinafter referred to as C(0), C(1), C(2)
,=,C (written as n>...) Also, address 1
The first BP is an address space pointer, and the memory address is determined based on this pointer.

Now, as an example, find the address Bp+3n of C(n),
A method for inserting constant quantities as data here will be explained with reference to the flowchart shown in FIG.

First, take the array variable n into the register Rφ and add 2
Perform degree addition to obtain 3n. Next, address space pointer BP is taken into register Aφ. and register A
Address Bp+3n, which is the sum of φ and register Rφ, and input the constant i.

Next, FIG. 7 shows a diagrammatic representation of the case where the scale factor is used in the addressing mode.

Similarly to the above, this means that the array variable n is placed in the register Rφ,
Read address space pointer BP into register Aφ. , and puts the constant i into the address indicated by the sum of the register Aφ and the scale factor (sf) times the register Rφ. This allows direct addressing.

Problems to be Solved by the Invention The conventional method of performing addition requires a large number of program steps and is complicated. Also, the scale factor (
sf) in the addressing mode, the scale factor (sf) can only take a value of 2 to the nth power, and the above example of a 3-byte array element cannot be realized. Furthermore, in order to realize this addressing mode, the operand must be bit-expanded for the scale factor, which has the problem of lowering ROM efficiency.

The present invention solves the above-mentioned conventional problems.
The object of the present invention is to provide an information processing circuit that can multiply data by an integer at high speed without reducing efficiency.

Means for Solving the Problems The information processing circuit of the present invention includes a readable and writable register or memory for writing data, a circuit for obtaining an integral multiple of the data, and a readable register or memory for storing the integral multiple of the data. It is equipped with registers or memory.

Effect: According to the information processing circuit of the present invention, data that is an integer multiple of data can be obtained at high speed without reducing ROM efficiency.

Embodiment An embodiment of the information processing circuit of the present invention will be described with reference to the block diagram shown in FIG.

In this circuit block, a readable and writable register (hereinafter referred to as MRW) 5, a readable register (hereinafter referred to as MR) 6, and a writable register (hereinafter referred to as MW) 7 are connected to a data bus 4. MW7 is connected to the multiplier 9 through the control line 8, MRW5 is also connected to the multiplier 9 through the control line 10, and the multiplier is connected to the multiplier 9 through the control line 10.
This structure is connected to MR6 through 1.

Next, the operation of this circuit block will be explained. First, write the desired data magnification into MW7 in advance. (Or it may be control data for the multiplier 9 to operate in the same manner.) Then, this data is input to the multiplier 9 through the control line 8, and the magnification of the desired data is determined. Note that this multiplier may be one that can only obtain a simple specific magnification.

Next, data is written to MRW5. Then, this data is input to the multiplier 9, and data obtained by multiplying the data by the magnification set in MW7 is input to MR6. Just by reading this, the desired integral multiple of data can be obtained.

Next, a method for determining the address Bp+3n of C(n) shown in FIG. 5 using this circuit will be explained with reference to the flowchart shown in FIG.

At this time, a magnification of 3x is set in advance for MW7.

First, array variable n is taken into register MRW5. Next, the address pace pointer BP is taken into the register Aφ (not shown). Then, MR6 receives 3 by multiplier 9.
Since the data of n has been set, all that is left is to set the target B.
Address p+3n and enter the constant quantity.

Although only one MRW5 is set in FIG. 1, as shown in FIG.
2, a plurality of M RW 5 a
, 5b, and 5c, and the arithmetic circuit 13 converts the desired integer multiple data into MR.
6 may be entered. In this way, integral multiples of the target data can be obtained without limiting the MRW.

Another embodiment is shown in the block diagram of FIG. In this figure, the data bus 4 is MRW5 and MR6a.

Connected to 6b, 6ce 6d, M R6a -6b
These circuit blocks are connected from the MRW5 through the control line 14 and adders 15a and 15b so that r6 c e 6 d are set to twice, three times, four times, and five times the data, respectively.

To obtain an integer multiple of data from this circuit, first, MRW
Write the required data in 5. Then, the data is transferred to the control line 14 as it is, twice the data is sent to MR6a, and three times the data is sent to MR6b through the adder 15a.
Similarly, 4 times the data is entered into MR6c, and 5 times the data is entered into MR6d. After that, the register containing the data of the desired magnification is selected from among the MRs 6a to 6d and read out. If you do this, there is no need to set the magnification in advance.

Here, we have shown an example of obtaining 2 to 5 times more data, but
Other magnifications can be set in the same way.

Further, the circuit may be configured so that only a specific magnification can be obtained.

Note that although registers are used in the embodiment, a memory may be used instead of the registers.

Effects of the Invention According to the information processing circuit of the present invention, by providing a readable and writable register (or memory) for writing data and a readable register (or memory) for storing integral multiples of the data, data can be read and written. Integer multiple data can be obtained at high speed without reducing ROM efficiency.

[Brief explanation of the drawing]

1, 3, and 4 are circuit block diagrams showing embodiments of the present invention, and FIG. 2 is a flowchart in which the present invention can be used. 4...Data bus, 5, 5a, 5b, 5c...
...Readable and writable register (MRW)
, 6, 6a, 6b, 6c, 6d...readable register (MR), ? ...Writable register (RW), 8, 10, 11.14...
・Control line, 9... Multiplier, 12... Input selection circuit, 13... Arithmetic circuit, 15a, 15
b... Adder. Name of agent: Patent attorney Toshio Nakao and one other person Figure 3 Figure Otsu Figure 4

Claims (1)

[Claims] An information processing circuit comprising: a readable and writable register or memory into which data is written; a circuit that obtains an integral multiple of the data; and a readable register or memory that stores the integral multiple of the data.