JP3333779B2 - Matrix arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix operation device for performing, for example, multiplication of matrices. A matrix arithmetic unit used for multiplication of a matrix has one multiply-accumulate unit as an arithmetic unit, or has a plurality of multiply-accumulate units operating simultaneously and in parallel, and has one or more multiply-accumulate units The present invention relates to a matrix operation device having a register or a memory capable of efficiently inputting data for a required matrix operation to an operation unit.

[0002]

2. Description of the Related Art In the case of matrix multiplication, multiplication and addition of matrix terms are performed more than the total number of matrix terms. This means that the number of multiplications is increased by the number of terms in the matrix on the left when multiplied by the number of terms to be calculated, and the number of terms in the matrix on the left when multiplied This is because the number of additions is increased by an amount obtained by multiplying the number of terms obtained by subtracting one from the number of included terms and the number of terms to be obtained. Therefore,
Conventionally, as a method of performing such matrix multiplication at high speed,
For example, there is a method as disclosed in Japanese Patent Application Laid-Open No. 63-86079, in which a plurality of arithmetic units for multiplication and addition are provided, and high-speed processing is performed using a parallel operation method for simultaneously performing a plurality of operations.

In addition, in matrix multiplication, a matrix column term on the right side is required for a matrix row term on the left side when multiplying. In the case of continuous extraction and calculation, it was necessary to rearrange the data.
There has been a technique for eliminating the need for using a memory for row and column conversion. For example, see JP-A-1-82175.

[0004]

However, when a matrix is multiplied by a computing unit, it is necessary to give the matrix terms to the computing unit that performs multiplication and addition one after another, which is a part of the matrix term. Data could be given to rows and columns one after another, but there was no way to keep the entire matrix data inside and give it one after another.

In order to capture the data amount of the entire matrix term larger than the rows and columns, a storage device using a dedicated circuit for storage such as a memory is required as compared with a storage device using a logic circuit such as a flip-flop. Is smaller in circuit size and more efficient, but it has been conventionally used only for a buffer of a pipeline, for example, using data in the order in which data is input like FIFO.

Therefore, according to the present invention, the arithmetic processing is performed at a high speed by simultaneously supplying all the necessary data in the matrix operation to one arithmetic unit or a plurality of arithmetic units operating in parallel. An object of the present invention is to continuously perform calculations on the entire matrix without loading additional data of the matrix from an external storage device by previously loading data of terms of the entire matrix into storage means.

[0007]

According to a first aspect of the present invention, there is provided a matrix operation device which decodes an input matrix operation instruction and outputs a write control signal, a read control signal, a selection control signal, and an operation control signal. A plurality of storage means for storing a plurality of matrix term data read from the external storage device, and a plurality of matrix term data by providing a write signal to the plurality of storage means by inputting a write control signal; A write unit for writing to the plurality of storage means, and a plurality of data from the data of the matrix terms stored in the plurality of storage means by applying a read control signal to the plurality of storage means as input. A read-out unit for simultaneously reading out, a matrix operation with an operation control signal and a plurality of operation data as inputs and outputting the operation result An arithmetic unit, a selector unit provided between the plurality of storage units and the arithmetic unit, and selectively inputting the plurality of data and the selection control signal and providing a plurality of arithmetic data to the plurality of input terminals of the arithmetic unit; It has. Then, when storing the data of the terms of the matrix in the plurality of storage means, the data of the terms required for the operation in the computing unit is divided into a number that can be output at the same time and stored. All the data of the terms required for the operation are simultaneously output from the means to the arithmetic unit in accordance with the read control signal.

Here, the matrix has four rows and four columns, the number of storage means is four, and the data of the terms of the matrix required for the matrix operation are divided into four and stored in the storage means.

When the data of the terms of the two matrices are stored in the first to fourth storage means, the first matrix has one row and one column, one row and three columns, and two rows and two columns. Columns, 2 rows, 4 columns, 3
Row 1 column, 3 row 3 columns, 4 row 2 columns, 4 rows 4 columns are stored in the first storage means as 1 row 2 columns, 1 row 4 columns, 2 rows 1 column of the first matrix,
2 rows and 3 columns, 3 rows and 2 columns, 3 rows and 4 columns, 4 rows and 1 column, and 4 rows and 3 columns are stored in the second storage means as 1 row, 1 column, 1 row 3 of the second matrix.
Column, 2 rows and 2 columns, 2 rows and 4 columns, 3 rows and 1 column, 3 rows and 3 columns, 4 rows and 2
Columns, 4 rows, 4 columns in the third storage means, 1 row, 2 columns, 1 row, 4 columns, 2 rows, 1 column, 2 rows, 3 columns, 3 rows, 2 columns, 3 rows, 4 columns of the second matrix Four rows and one column and four rows and three columns are stored in the fourth storage means.

According to this configuration, the writing section writes data of all the items of the matrix into the plurality of storage means in accordance with the write control signal, and the reading section reads the data necessary for the matrix operation from the plurality of storage means in accordance with the read control signal. A plurality of data are simultaneously read, and the selector selects a plurality of data in accordance with the selection control signal and supplies a plurality of operation data to the arithmetic unit. Further, when the data of the terms of the matrix is stored in the storage means, the data of the plurality of terms required for the operation in the arithmetic unit are divided into a number that can be output simultaneously, and stored. Can output all the data of the terms required for the operation to the arithmetic unit simultaneously in accordance with the read control signal.Also, in the case where the internal operation for performing the matrix multiplication is performed continuously, the Data can be continuously provided to the arithmetic unit.

In addition, when multiplying matrices of 4 rows and 4 columns, necessary data can be continuously and simultaneously extracted by appropriately distributing the data of the terms of the matrices and storing the data in the storage means.

According to a second aspect of the present invention, there is provided a matrix operation device.
In the described matrix operation device, a plurality of operation units are provided, and the plurality of operation units can be operated in parallel.

According to this configuration, since a plurality of operation units operate in parallel, a plurality of operations can be performed simultaneously, and a matrix operation can be performed at high speed.

According to a third aspect of the present invention, a matrix operation device decodes an input matrix operation instruction and outputs a write control signal, a read control signal, a selection control signal, and an operation control signal, and is read from an external storage device. A plurality of storage means for storing a plurality of matrix term data, and a matrix control data is input to the plurality of storage means to write the matrix term data to the plurality of storage means. A read unit for simultaneously reading a plurality of data from the data of the matrix items stored in the plurality of storage units by providing a read unit to the plurality of storage units with a read control signal as an input; A computing unit that performs a matrix operation with an operation control signal and a plurality of operation data as inputs and outputs an operation result; Provided between the storage means and the computing unit and a selector unit providing a plurality of arithmetic data a selection control signal and a plurality of data as input selectively to a plurality of input terminals of the arithmetic unit. Then, when storing the data of the terms of the matrix in the plurality of storage means, the data of the terms required for the operation in the computing unit is divided into a number that can be output at the same time and stored. From the means to the arithmetic unit,
All the data of the terms required for the operation are output simultaneously according to the read control signal.

Here, the matrix has 4 rows and 4 columns, the number of storage means is eight, and the data of the matrix term necessary for the matrix operation is divided into eight and stored in the storage means.

When the data of the terms of the two matrices are stored in the eight storage means from the first to the eighth, the first matrix has the first row, the first column, the second row, the fourth column, the third row, and the third row. Column, 4 rows, 2 columns in the first storage means, 1 row, 2 columns, 2 rows, 1 column of the first matrix,
3 rows and 4 columns and 4 rows and 3 columns are stored in the second storage means, and 1 row and 3 columns, 2 rows and 2 columns, 3 rows and 1 column, and 4 rows and 4 columns of the first matrix are stored in the third storage means. 1 row 4 columns, 2 rows 3 columns, 3 rows 2 of the first matrix
Column, 4 rows, 1 column in the fourth storage means, 1 row 1 column, 2 rows, 4 columns, 3 rows, 3 columns, 4 rows, 2 columns of the second matrix in the fifth storage means, 1 row, 2 columns, 2 rows, 1 column, 3 rows, 4 columns, 4
Row 3 column is stored in the sixth storage means, 1 row and 3 column of the second matrix,
Two rows and two columns, three rows and one column, and four rows and four columns are stored in the seventh storage means,
The first row, fourth column, second row, third column, third row, second column, and fourth row, first column of the first matrix are stored in the eighth storage means.

According to this configuration, the writing section writes data of all the items of the matrix into the plurality of storage means in accordance with the write control signal, and the read section reads the data necessary for the matrix operation from the plurality of storage means in accordance with the read control signal. A plurality of data are simultaneously read, and the selector selects a plurality of data in accordance with the selection control signal and supplies a plurality of operation data to the arithmetic unit. Further, when the data of the terms of the matrix is stored in the storage means, the data of the plurality of terms required for the operation in the arithmetic unit are divided into a number that can be output simultaneously, and stored. Can output all the data of the terms required for the operation to the arithmetic unit simultaneously in accordance with the read control signal.Also, in the case where the internal operation for performing the matrix multiplication is performed continuously, the Data can be continuously provided to the arithmetic unit.

Further, when performing multiplication between matrices of 4 rows and 4 columns, by appropriately distributing the data of the terms of the matrices and storing them in the storage means, necessary data can be continuously and simultaneously extracted.

According to a fourth aspect of the present invention, there is provided a matrix operation device according to the third aspect.
In the described matrix operation device, a plurality of operation units are provided, and the plurality of operation units can be operated in parallel.

According to this configuration, since a plurality of operation units operate in parallel, a plurality of operations can be performed simultaneously, and a matrix operation can be performed at high speed.

[0021]

Embodiments of the present invention will be described below with reference to FIG. In the following description, a configuration example in the case of using a product-sum operation unit including two multipliers and an adder for adding two multiplication results is described as an operation unit.

In FIG. 1, 1 is an instruction. Reference numeral 2 denotes a decoder which decodes the input instruction 1 and outputs a control signal 4. In this case, the control signal 4 is divided into a write control signal, a read control signal, a selection control signal, and an arithmetic control signal.

Numeral 19 denotes an arithmetic unit having a function as a product-sum arithmetic unit. A writing unit 21 receives a control signal 4 (write control signal) as an input and outputs a write signal 22.
A read unit 3 receives a control signal 4 (read control signal) and outputs a read signal 24.

Reference numeral 3 denotes an external storage device such as a main storage which stores all data of matrix terms used for calculation.
The bus width of the data in the external storage device 3 is one item.

6, 7, 8, and 9 are 1 from the external storage device 3.
This is a matrix data division storage memory serving as storage means for inputting data 5 output for each term and storing data in accordance with a write signal 22. The matrix data division storage memories 6 to 9 output data 10 to 13 according to a read signal 24 given from the read unit 23.
Are output.

14 is a matrix data division storage memory 6
The selector 14 receives the output data 10 to 13 from the selectors 9 to 9 as input, and the selector 14 outputs the data for operation 15, 16, 17, 1 as data necessary for the arithmetic unit 19.
8 is output to the arithmetic unit 19. The arithmetic unit 19 performs an operation (product-sum operation) using the data 15 to 18 according to the control signal 4 (operation control signal), and outputs an operation result 20. The calculation result is also input to the writing unit 21 and stored in any of the matrix data division storage memories 6, 7, 8, and 9 according to the control signal 4 (write control signal).

Here, as a specific example of the matrix operation, 2
A case where multiplication of the matrices α and β is performed will be described.
2 is stored in the matrix data division storage memories 6, 7, 8, and 9.
The data of the terms of the matrices α and β used when multiplying the two matrices α and β are stored. Then, the read unit 23 receives the control signal 4 (read control signal) and receives the matrix data division storage memories 6, 7, 8, 9
, A plurality of pieces of data 10, 11, 12, and 13 necessary for one product-sum operation are simultaneously read from the term data of the matrix stored in. The selector unit 14 includes a plurality of data 10, 11,.
A plurality of operation data 15, 16, 17, and 18 are supplied to an arithmetic unit 19 by using the input signals 12 and 13 and the control signal 4 (selection control signal). Then, the arithmetic unit 19 receives the plurality of operation data 15, 16, 17, and 18 and outputs the operation result 20.
Is output to the writing unit 21.

As an example of an operation using the above-described matrix operation device, consider a case where a matrix α is multiplied by a matrix β from the left. The data in the matrix α is (Equation 1), and the data in the matrix β is
Suppose that it consists of (Equation 2).

[0029]

(Equation 1)

[0030]

(Equation 2)

First, in order to obtain a term of one row and one column, a
× A, b × E, c × I, d × M, and their addition are required. In the above-described arithmetic unit (product-sum arithmetic unit) 19, two multiplications and the addition of the multiplication results can be performed at the same time, so that a × A, b × E, and the addition of these results can be performed only once. it can. In the next cycle, c × I, d × M,
These results are added, and the whole is added in the last cycle to obtain the result of the item of 1 row and 1 column.

At that time, first, the four terms a, A, b, and E are simultaneously required, and then the four terms c, I, d, and M are simultaneously required. In the last cycle, it suffices that the two terms of the result of the first operation be simultaneously. Hereinafter, the remaining matrix operations can be performed in the same manner.

In order to continuously perform the operation for each term of the matrix as described above, an average of 10/3 per cycle is required.
($ 3.3) is required at the same time. However, the data from the external storage device 3 such as the main memory has only one item of bus width, and data of four items cannot be input at the same time. Therefore, the data of all the terms of the matrices α and β are distributed and stored in the matrix data division storage memories 10, 11, 12 and 13 so that the terms necessary for the operation can be output simultaneously.

In the case of performing the above-mentioned multiplication of the matrices α and β of 4 rows and 4 columns, the four matrix data division storage memories 10, 11, 12 and 13 store, for example,
Distribute data. That is, 1 row 1 of the first matrix α
Column, 1 row, 3 columns, 2 rows, 2 columns, 2 rows, 4 columns, 3 rows, 1 column, 3 rows, 3
Column, 4 rows, 2 columns, 4 rows, 4 columns of data a, c, f, h,
i, k, n, p are stored in a matrix data division storage memory 10
In the first matrix α, 1 row and 2 columns, 1 row and 4 columns, 2 rows and 1 column,
The data b, d, e, g, j, l, m, and o of the items of 2 rows and 3 columns, 3 rows and 2 columns, 3 rows and 4 columns, 4 rows and 1 column, and 4 rows and 3 columns are stored in the matrix data division storage memory 11. In the second matrix β, terms of 1 row and 1 column, 1 row and 3 columns, 2 rows and 2 columns, 2 rows and 4 columns, 3 rows and 1 column, 3 rows and 3 columns, 4 rows and 2 columns, and 4 rows and 4 columns Data A, C, F,
H, I, K, N, and P are stored in the matrix data division storage memory 12 in the first row, second column, first row, four columns, and second row of the second matrix β.
Column, 2 rows and 3 columns, 3 rows and 2 columns, 3 rows and 4 columns, 4 rows and 1 column, 4 rows and 3
The data B, D, E, G, J, L, M, and O of the column items are stored in the matrix data division storage memory 13.

As described above, all the terms of the matrices α and β are stored in the matrix data division storage memories 10 to 13 when the terms such as 1 row, 2 columns, 1 row, 3 columns,. This is because it is inefficient to read out the external storage device 3 again when it is desired to reuse the previously used term because the same term is required several times. Also, by storing all terms of the matrices α and β,
Even when the matrix is multiplied from the right or from the left, it can be dealt with simply by changing the instruction, without changing the order of the terms inside.

According to the matrix operation device of this embodiment,
The writing unit 21 writes the data of the matrix term into the plurality of matrix data division storage memories 10 to 13 according to the control signal 4, and the reading unit 23 reads the matrix data from the plurality of matrix data division storage memories 10 to 13 according to the control signal 4. A plurality of data necessary for the operation are simultaneously read out, and the selector unit 14 selects a plurality of data according to the control signal 4 and sends the plurality of operation data 15 to 18 to the arithmetic unit 19.
When the data of the terms of the matrix are stored in the matrix data division storage memories 10 to 13, the number of data 10 to 13 of the plurality of terms required for the operation by the arithmetic unit 19 can be simultaneously output. Since the data is divided and stored, the matrix data division storage memories 10 to 13 are used to
In response to this, all of the data of the term necessary for the operation
Can be output simultaneously, and even if the internal calculation for multiplying the matrix is continuously performed, the data of the terms of the matrix can be continuously provided to the arithmetic unit.
Therefore, the matrix operation can be performed at high speed.

In the above-described embodiment, only one arithmetic unit for performing the product-sum operation is provided. However, two or four product-sum arithmetic units operating in parallel may be provided. The number of arithmetic units is not limited to these numbers, and may be any number. As described above, when a large number of arithmetic units are provided in parallel, a plurality of arithmetic operations can be performed at the same time, many operations can be performed in a small number of operation cycles, and the speed of the matrix operation can be increased. At this time, if the number of arithmetic units increases, the number of data to be output at the same time increases. Therefore, it is necessary to increase the number of matrix data division storage memories accordingly. It is possible to use eight or more.

Here, taking as an example the case where the matrix α and β of 4 rows and 4 columns are multiplied when the number of matrix data division storage memories is eight, the eight matrix data division storage memories include, for example, Distribute the data as follows. That is, when the data of the terms of the two matrices are stored in the eight matrix data division storage memories from the first to the eighth, the first matrix α has the first row, the first column, the second row, the fourth column, and the third matrix.
The data a, h, k, and n of the row 3 column, 4 row 2 column items are stored in the first matrix data division storage memory in the first matrix α in the first row, the second column, the second row, the first column, and the third row 4 The data b, e, l, and o in the column, row 3 and column 3 are stored in the second matrix data division storage memory in the first matrix α in the first row, the third column, the second row, the second column, and the third row 1
The data c, f, i, and p in the column, row 4 and column 4 are stored in the third matrix data division storage memory in the first matrix α in rows 1 and 4, 2 and 3, 3 and 2 columns, Data d of 4 rows and 1 column term,
g, j, and m are stored in the fourth matrix data division storage memory in the first matrix β, row 1, column 2, row 4, column 3, row 3, and column 3,
The data A, H, K, and N of the 4-row, 2-column term are stored in the fifth matrix data division storage memory in the first row of the second matrix β.
Column B, row 1, column 3, row 4, column 4, row 3, column data B,
E, L, and O are stored in the sixth matrix data division storage memory in the first matrix β in the first row, three columns, two rows, two columns, three rows, one column,
The data C, F, I, and P in the 4-row, 4-column terms are stored in the seventh matrix data division storage memory in the first matrix β in the first row 4
The data D, G, J, and M of column 2, row 3 and column 3
In the matrix data division storage memory.

Then, based on the data read from the eight matrix data division storage memories, a product-sum operation is performed using two or four arithmetic units to perform matrix multiplication.

[0040]

According to the matrix operation device of the present invention, there is provided storage means for storing data of the entire matrix, and the storage means is provided so that data necessary for the operation of the operation unit can be simultaneously supplied to the operation unit. Is divided into a plurality of pieces of data, and the data required simultaneously for the matrix operation is stored in separate storage means, so that the necessary data can be continuously provided to the arithmetic unit until the entire matrix operation is completed. Becomes possible,
There is an effect that matrix operation can be performed at high speed.

By providing a plurality of arithmetic units,
A plurality of operations can be performed at the same time, the number of operations can be reduced, and the operation can be performed at higher speed.

Also, by storing specific matrix terms in a specific storage means, data necessary for performing a matrix operation can be continuously and simultaneously extracted and stored in a specific storage means. Thus, there is an effect that a plurality of operations can be performed using the same matrix.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a matrix operation device according to an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 instruction 2 decoder 3 external storage device 4 control signal 5 data 6 matrix data division storage memory 7 matrix data division storage memory 8 matrix data division storage memory 9 matrix data division storage memory 10 output data of matrix data division storage memory 6 11 matrix data Output data of the division storage memory 7 12 Output data of the matrix data division storage memory 8 13 Output data of the matrix data division storage memory 9 14 Selector unit 15 Operation data 16 Operation data 17 Operation data 18 Operation data 19 Operation unit 20 Calculation result 21 Write section 22 Write signal 23 Read section 24 Read signal

Continuation of front page (56) References JP-A-54-120546 (JP, A) JP-A-62-97060 (JP, A) JP-A-8-255151 (JP, A) JP-A-5-346935 (JP) JP-A-5-324700 (JP, A) JP-A-4-43461 (JP, A) JP-A-2-77967 (JP, A) JP-A-60-1001671 (JP, A) 55-49763 (JP, A) Yasushi Kiyoshi, A Special-Purpose Computer for Solving Dense Matrix Based on Gaussian Elimination Algorithm Graduate School of Arts and Sciences, Tokyo, Japan, 1996. Tsuyoshi Kiyoki and 5 others, Development of a dedicated computer GENERA-1 for dense matrix, Research Report of the Information Processing Society of Japan, Information Processing Society of Japan, March 10, 1995, Vol. 95, No. 29, ( 95− RC-111), p. 65-72 Tsuneo Nakanishi and 3 others, DPG: Data-separated graph, Information Processing Society of Japan research report, Japan, Information Processing Society of Japan, January 28, 1994, Vol. 94, No. 13, (94- ARC-104, 94-OS-62), p. 121-128 Yoshimasa Obayashi, 4 others, Programming of Parallel Description Language ADETRAN Using Data Structure of Physical PE and Its Effective Performance, Information Processing Society of Japan, IPSJ, IPSJ, August 19, 1993 Vol. 93, No. 72, (93-HPC-48), p. 1-7 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/10-17/18

Claims (4)

(57) [Claims] 1. A decoder that decodes an input matrix operation command and outputs a write control signal, a read control signal, a selection control signal, and an operation control signal, and a plurality of matrix term data read from an external storage device. A plurality of storage means for storing the write control signal as input, and a writing unit for writing data of the items of the matrix to the plurality of storage means by giving a write signal to the plurality of storage means with the write control signal as an input; Read-out for simultaneously reading out a plurality of data from the data of the items of the matrix stored in the plurality of storage means by providing the read-out control signal as an input and providing a read-out signal to the plurality of storage means. A computing unit that performs a matrix operation with the operation control signal and a plurality of operation data as inputs and outputs an operation result. Receiving the plurality of data and the selection control signal as inputs between the plurality of storage means and the arithmetic unit to selectively supply the plurality of arithmetic data to the plurality of input terminals of the arithmetic unit And a selector unit, when storing the data of the terms of the matrix in the plurality of storage means, by dividing the data of the terms necessary for the operation in the computing unit into a number that can be output simultaneously. Storing, in accordance with the read control signal, all the data of the terms required for the operation from the plurality of storage means to the arithmetic unit at the same time; The data of the matrix term necessary for matrix operation is divided into four and stored in the storage means, and the data of two matrix terms are stored in the first to fourth storage means. Is stored in the first matrix Line 1
Column, 1 row, 3 columns, 2 rows, 2 columns, 2 rows, 4 columns, 3 rows, 1 column, 3 rows, 3
Columns, 4 rows and 2 columns, and 4 rows and 4 columns are stored in the first storage means in the first matrix, 1 row and 2 columns, 1 row and 4 columns, 2 rows and 1 column, 2 rows and 3 rows
Columns, 3 rows and 2 columns, 3 rows and 4 columns, 4 rows and 1 column, and 4 rows and 3 columns are stored in the second storage means as 1 row, 1 column, 1 row, 3 columns of the second matrix,
2 rows and 2 columns, 2 rows and 4 columns, 3 rows and 1 column, 3 rows and 3 columns, 4 rows and 2 columns,
Four rows and four columns are stored in the third storage means, in the second matrix, 1 row and 2 columns, 1 row and 4 columns, 2 rows and 1 column, 2 rows and 3 columns, 3 rows and 2 columns,
A matrix operation device wherein three rows and four columns, four rows and one column, and four rows and three columns are stored in the fourth storage means. 2. The matrix operation device according to claim 1, wherein a plurality of operation units are provided, and the plurality of operation units can operate in parallel. 3. A decoder that decodes an input matrix operation command and outputs a write control signal, a read control signal, a selection control signal, and an operation control signal, and a plurality of matrix term data read from an external storage device. A plurality of storage means for storing the write control signal as input, and a writing unit for writing data of the items of the matrix to the plurality of storage means by giving a write signal to the plurality of storage means with the write control signal as an input; Read-out for simultaneously reading out a plurality of data from the data of the items of the matrix stored in the plurality of storage means by providing the read-out control signal as an input and providing a read-out signal to the plurality of storage means. A computing unit that performs a matrix operation with the operation control signal and a plurality of operation data as inputs and outputs an operation result. Receiving the plurality of data and the selection control signal as inputs between the plurality of storage means and the arithmetic unit to selectively supply the plurality of arithmetic data to the plurality of input terminals of the arithmetic unit And a selector unit, when storing the data of the terms of the matrix in the plurality of storage means, by dividing the data of the terms necessary for the operation in the computing unit into a number that can be output simultaneously. Storing, in accordance with the read control signal, all the data of the terms required for the operation from the plurality of storage means to the arithmetic unit at the same time; The data of the matrix terms necessary for matrix operation are divided into eight and stored in the storage means, and the data of the two matrix terms are stored in the first to eighth storage means. Is stored in the first matrix Line 1
Columns, 2 rows and 4 columns, 3 rows and 3 columns, and 4 rows and 2 columns are stored in the first storage means as 1 row, 2 columns, 2 rows, 1 column, 3 rows, 4 rows of the first matrix.
Columns, 4 rows and 3 columns are stored in the second storage means, and 1 row and 3 columns, 2 rows and 2 columns, 3 rows and 1 column, and 4 rows and 4 columns of the first matrix are stored in the third storage means. 1 row, 4 columns, 2 rows 3 of the first matrix
Columns, 3 rows and 2 columns, and 4 rows and 1 column are stored in the fourth storage means, and 1 row and 1 column, 2 rows and 4 columns, 3 rows and 3 columns, and 4 rows and 2 columns of the second matrix are stored in the fifth storage means. In the storage means, 1 row and 2 columns of the second matrix,
Two rows and one column, three rows and four columns, and four rows and three columns are stored in the sixth storage means, in the second matrix, in one row and three columns, two rows and two columns, and three rows and one row.
Columns, 4 rows and 4 columns are stored in the seventh storage means, and 1 row and 4 columns, 2 rows and 3 columns, 3 rows and 2 columns, and 4 rows and 1 column of the second matrix are stored in the eighth storage means. A matrix operation device, characterized in that: 4. The matrix operation device according to claim 3, wherein a plurality of operation units are provided, and the plurality of operation units can be operated in parallel.