JPS59200448A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59200448A
JPS59200448A JP58074473A JP7447383A JPS59200448A JP S59200448 A JPS59200448 A JP S59200448A JP 58074473 A JP58074473 A JP 58074473A JP 7447383 A JP7447383 A JP 7447383A JP S59200448 A JPS59200448 A JP S59200448A
Authority
JP
Japan
Prior art keywords
insulator substrate
substrate
external lead
semiconductor device
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58074473A
Other languages
Japanese (ja)
Inventor
Yoichi Emura
江村　羊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58074473A priority Critical patent/JPS59200448A/en
Publication of JPS59200448A publication Critical patent/JPS59200448A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve heat radiation by bonding an insulator substrate having excellent thermal conduction with a surface reverse to a semiconductor element of a metallic plate and bonding the tip of an external lead-out lead wire with the insulator substrate. CONSTITUTION:An insulator substrate 66 having thermal conduction better than a sealing resin 11, such as an alumina substrate, a beryllia substrate, etc. is bonded with a surface reverse to a pellet 22 of a metallic plate 33, external lead-out lead wires 44 are formed so as to reach to the insulator substrate 66, and the tips of the lead wires are bonded with the insulator substrate 66. A heat radiating section consists of the metallic plate 33, the insulator substrate 66 having excellent thermal conduction and the external lead-out lead wires 44, heat can be made escape without being passed through the sealing resin 11, and transient thermal resistance and further thermal resistance can be reduced.

Description

【発明の詳細な説明】 本発明は半導体装置に関し特に樹脂封止された集積回路
等の半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device such as an integrated circuit sealed with resin.

従来、この種の半導体装置の内部構造としては、第１．
２図に示すような樹脂封止された集積回路がある。Conventionally, the internal structure of this type of semiconductor device is as follows.
There is a resin-sealed integrated circuit as shown in Figure 2.

即ち、半導体素子２は、金属板３に接着固定され各電極
は、ボンディング線５によシ各々外部引出しリード線４
に接続され、そしてこれらは封止樹脂１によシ封止され
ている。That is, the semiconductor element 2 is adhesively fixed to a metal plate 3, and each electrode is connected to an external lead wire 4 through a bonding wire 5.
, and these are sealed with a sealing resin 1.

かかる集積回路において、直流電力、あるいはパルス電
力を印加した場合、内部発熱の熱放散径路としては半導
体素子が発熱後熱が金属板を通り、金属板と外部リード
線が対向する部分の封止樹脂を通シ、外部引出しリード
線を介し熱放散される部分と、外部引出しリード線を介
さずに外部引出しリード線と対向していない封止樹脂よ
シ外部へ熱放散される部分がある。しかしながら封止樹
脂は金属板、外部引出しリード線に比べ熱伝導が悪い為
、前者が支配的である。このような支配的である熱拡散
径路において、金属板と外部引出しリード線の対向部分
に封止樹脂が介在している為、熱抵抗特に過渡熱抵抗が
大きくなる欠点があった。In such an integrated circuit, when DC power or pulsed power is applied, the heat dissipation path for internal heat generation is that after the semiconductor element generates heat, the heat passes through the metal plate, and the sealing resin is used at the part where the metal plate and the external lead wire face each other. There is a portion where heat is dissipated through the external lead wire and a portion where heat is dissipated to the outside through the sealing resin that does not face the external lead wire without passing through the external lead wire. However, since the sealing resin has poor thermal conductivity compared to metal plates and external lead wires, the former is predominant. In such a dominant heat diffusion path, the sealing resin is interposed between the opposing portion of the metal plate and the external lead wire, which has the drawback of increasing thermal resistance, particularly transient thermal resistance.

特に消費電力の多い集積回路では問題となる。This is especially a problem in integrated circuits that consume a lot of power.

本発明は、これら従来技術からなる欠点を解消、シ、熱
放散を良好にした半導体装置を提供するものである。The present invention eliminates the drawbacks of these conventional techniques and provides a semiconductor device with improved heat dissipation.

本発明による半導体装置は、金属板の半導体素子と反対
の面に熱伝導の良い絶縁体基板を接着し、各々の外部引
出しリード線の先端を絶縁体基板に接着させる。かかる
構成によシ封止樹脂を通さずに外部へ熱放散を行うこと
ができ、過渡熱抵抗を小さくすることが可能となる。In the semiconductor device according to the present invention, an insulating substrate with good thermal conductivity is bonded to the surface of a metal plate opposite to the semiconductor element, and the tips of each external lead wire are bonded to the insulating substrate. With this configuration, heat can be dissipated to the outside without passing through the sealing resin, and the transient thermal resistance can be reduced.

以下、図面を用いて、本発明を分かシやすく説明する。Hereinafter, the present invention will be explained in an easy-to-understand manner using the drawings.

第３図は本発明の一実施例による樹脂封止された集積回
路の内部斜視図、第４図は断面図である。FIG. 3 is an internal perspective view of a resin-sealed integrated circuit according to an embodiment of the present invention, and FIG. 4 is a sectional view.

即ち金属板３３のペレット２２と反対の面に封止樹脂１
１よシ熱伝導の良好な絶縁体基板６６、例えばアルミナ
基板ベリリア基板等を接着し、各々の外部引出しリード
線５５を絶縁体基板６６迄とどくように形成し、その先
端を絶縁体基板６６に接着したものである。That is, the sealing resin 1 is placed on the surface of the metal plate 33 opposite to the pellet 22.
1, an insulating substrate 66 with good thermal conductivity, such as an alumina substrate or a beryllia substrate, is bonded, and each external lead wire 55 is formed so as to reach the insulating substrate 66, and its tip is attached to the insulating substrate 66. It is glued together.

かかる集積回路において、直流電力、あるいはパルス電
力を印加した場合、熱放散径路は、金属板３３．熱伝導
の良好な絶縁体基板６６、外部引出しリード線４４とな
）封止樹脂１１を通さずに熱を逃がすことができ、過渡
熱、抵抗、さらには熱抵抗を小さくすることができる半
導体装置が得られる。尚、本発明は上記実施例に限定さ
れず、様々の接着の仕方が可能である。即ち絶縁体基板
を外部引出しリード線までとどく大きさにしても良い。In such an integrated circuit, when DC power or pulsed power is applied, the heat dissipation path is formed by the metal plate 33. A semiconductor device that can release heat without passing through the sealing resin 11 (such as an insulator substrate 66 with good heat conduction and external lead wires 44), and can reduce transient heat, resistance, and even thermal resistance. is obtained. Note that the present invention is not limited to the above embodiments, and various bonding methods are possible. That is, the insulating substrate may be made large enough to reach the external lead wire.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来の半導体装置の一例の内部斜視図
と断面図である。 第３図、第４図は本発明による半導体装置の一実施例の
内部斜視図と断面図である。FIGS. 1 and 2 are an internal perspective view and a sectional view of an example of a conventional semiconductor device. FIGS. 3 and 4 are an internal perspective view and a sectional view of an embodiment of a semiconductor device according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を搭載する金属板と、該半導体素子の電極に
ボンディング線を介して接続され該半導体素子を樹脂封
止する容器の外部に導出された少なくとも２本のリード
線を有する半導体装置に於いて、前記金属板の半導体素
子と反対の面に熱伝導のよい絶縁体基板を接着し、前記
リード線を該絶縁体基板に接着したことを特徴とする半
導体装置。In a semiconductor device having a metal plate on which a semiconductor element is mounted, and at least two lead wires connected to the electrodes of the semiconductor element via bonding wires and led out of a container in which the semiconductor element is sealed with resin. . A semiconductor device, characterized in that an insulating substrate with good thermal conductivity is bonded to the surface of the metal plate opposite to the semiconductor element, and the lead wire is bonded to the insulating substrate.
JP58074473A 1983-04-27 1983-04-27 Semiconductor device Pending JPS59200448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58074473A JPS59200448A (en) 1983-04-27 1983-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58074473A JPS59200448A (en) 1983-04-27 1983-04-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59200448A true JPS59200448A (en) 1984-11-13

Family

ID=13548258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58074473A Pending JPS59200448A (en) 1983-04-27 1983-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59200448A (en)

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