JPS59200346A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce the control storage by using both the execution using a microprogram and the execution using a microprogram with intervention of an instruction program to execute a software instruction. CONSTITUTION:A main memory 1 stores a software program 11 containing the 1st and 2nd type software instructions and an instruction program 12 in which each function of the 2nd type software instruction is formed with the 1st type software instruction. When the software instruction which is read out of the memory 1 by an address given from a switch circuit 48 is equal to the 1st type software instruction, the instruction is executed by a microprogram stored in a control memory 31. If the software instruction read out of the memory 1 is equal to the 2nd type software instruction, the instruction is executed by the microprogram by the intervention of the program 12 stored in the memory 1.

Description

[Detailed description of the invention] The present invention relates to a microprogram controller.

In addition to storing the microprogram in the control memory, it is also possible to store the microprogram in the main memory and directly execute the microprogram, or store it in a specific area of the control memory for each required function. Conventionally, a system has been used in which the data is imported into an arbitrary area using a cache method and then executed on the control memory.

In such conventional equipment, the aim is to speed up processing.
As memory elements become faster, processing becomes more complex.

As the scale of microprograms increases, so-called horizontal microinstructions with a large pit structure are becoming losers in attempts to increase the number of functions that can be executed in a single step of the microinstructions that make up a microprogram, and to improve parallelism. There is.

For frequently used basic arithmetic instructions, the above-mentioned horizontal micro-instructions can be fully utilized to reduce the number of micro-instructions required to execute software instructions, thereby reducing software instruction execution time. It is extremely effective in shortening the time. However, many other instructions, such as list processing instructions that repeat data handling in main memory, and various control instructions, often involve sequential processing, and highly horizontal microinstructions are required for these functions as well. When using a micro-instruction, only some of the bits that make up each micro-instruction are used at a time, and the rest of the bits are not used. This method has the disadvantage that storage, control storage, etc. are wasted.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control device that eliminates the drawbacks of the conventional devices described above and greatly reduces waste in main memory, control memory, etc. for storing microinstructions.

The apparatus of the present invention is a data processing apparatus that is inversely controlled by a microprogram stored in a control memory, and includes a software program having a first type of software instructions and a second type of software instructions; storage means for storing an instruction program in which at least a part of each function of each type of software instruction is performed by a first type of software instruction; and software to be read from the software program stored in the storage means. Set the instruction address to 18 of the second type
address setting holding means for holding the address in response to the supply of the first type of signal and releasing the holding in response to the supply of the first type of signal; and a software instruction to be read from the instruction program stored in the storage means. address setting means for setting an address; and address setting means for selecting an address supplied from the address setting holding means in response to the supply of a first type of signal and in response to supplying a second type of signal. selecting means for selecting an address supplied from said selecting means; and if a software instruction read from said storage means according to an address supplied from said selecting means is a first type of software instruction, said selecting means for selecting said address supplied from said control memory; control means for executing the instruction by a microprogram; and when the software instruction read from the storage means by the address supplied from the selection means is a second type of software instruction, the instruction is specified by the instruction; generates the second type of signal according to a microinstruction of the microprogram to be executed, and sets a predetermined value to the address setting means as an execution start address of the instruction program corresponding to the second type of software instruction; and signal generating means for generating a signal.

Next, the present invention will be explained in detail with reference to the drawings.

As described above, software instructions can be broadly divided into a first group of instructions suitable for execution using horizontal microphone mouth instructions and a second group of instructions unsuitable for such execution. The first instruction group is used much more frequently in software programs than the second instruction group. Therefore, the first instruction group accounts for most of the software program execution time, and the second instruction group contributes to a relatively small amount of the software program execution time (6D), and the present invention focuses on this. Therefore, the handling of the second group of instructions was considered to enable effective use of the main memory, etc., which was the intended purpose.

Furthermore, buffer memory, parallel processing,
There have been recent developments in high-speed processing technology for large computers, such as pipeline processing. As a result, it is now possible to expect a significant reduction in the processing time for basic arithmetic instructions.

Therefore, in the present invention, the software instructions belonging to the first instruction group (hereinafter collectively referred to as A) use horizontal microinstructions, and the software instructions belonging to the second instruction group (
A program (hereinafter collectively referred to as B) is a program written using software instructions belonging to the first instruction group (hereinafter referred to as an instruction program). Therefore, when executing B, multiple A's, that is, A□, A
2゜A3 etc. must be executed, and for this purpose A
It is necessary to execute a plurality of horizontal microinstructions comprising l+A2+Aa, etc. The reason why BffiA has multiple configurations as described above is that BffiA often performs sequential processing, so even if horizontal microinstructions are used, only one function is executed at a time, and vertical microinstructions are This is because it is used in the same way as , so even if you write it as A, it will mean the same thing.

Moreover, since parallel processing of nine software instructions can be performed, such as the pipeline processing described above, the execution time is actually in the direction of being shortened.

In order to realize the above idea, it is necessary to
It is not enough to simply decode the software instructions and execute the microprogram. ), access the instruction program corresponding to B, and further access the microprogram to execute this program.

Next, the above operation will be explained in detail using the drawings.

The figure is a block diagram of one embodiment of the present invention. Referring to the figure, one embodiment of the present invention has a main memory (1v1ivi) 1
, an arithmetic circuit 2 , a control storage circuit 3 , an instruction data 7 and an Esochi circuit 4 .

The main memory 1 stores a software program 11 that performs predetermined processing and a plurality of instruction program groups 12 written in software instructions. The arithmetic circuit 2 is controlled by the control storage circuit 3 and performs various arithmetic processes. The control memory circuit 3 includes a control memory (C8) 31 that stores a microprogram written in microinstructions.
and a control memory control circuit (C8
CONT) 34 and flip-flop circuit (FF) 3
5 and the control storage address (
sxR) There is a register circuit 2 and an address addition circuit 33. The instruction data fetch circuit 4 is controlled by the C3 CONT 34, and is a circuit that takes out software instructions and data from the main memory 1 and stores all the data. a data register (DR) 44 for temporarily storing data issued or to be stored; an instruction counter (IC) 45 for temporarily storing address data of instructions to be read from the software program 11 in the main memory 1; An instruction counter (IC) 47 that temporarily stores address data of instructions to be read from the instruction program group 12 in the main memory 1. IC4
5 and IC 47, and an address adder circuit 46 that creates the address of the next instruction to be read.
, an address adder (ADD) 42 for creating an address of data to be read or written, and an address register 43 for temporarily storing the address.

In the initial state, FF35 is reset and 9 connection lines 11
The signal through 2 is logic 110'' and DEX048 is I
C45 data is selected. When FF35 is set, the signal through the connection line 112t becomes logic 1"!D
The IC45 is in a state where it retains the stored data9.
, EXC48 selects the data of IC47.

First, the operation in the case of the software instruction A□ belonging to the first instruction group will be explained.

This person 1 is handled in exactly the same way as in the conventional device. That is, in this case, the BXC 48 selects the address signal stored in the IC 45 and supplies it to the main memory 1, and one instruction in the software program 11 stored at the address specified by the address signal is sent to the connection line 1.
The - instruction read out via 01 and stored in lR41 is A1.
This is a rare case. According to A1, the start address for reading the microprogram stored in 9C831 is 5A.
This address signal is stored in R32 and connected to connection 1101-
A series of horizontal microinstructions are read out and decoded by the C3CONT34, and the control signal is sent to the C831.
13 to the arithmetic circuit 2 to execute Alt.

In this execution, necessary data is read out from the main memory 1 and stored, but since this is a known technique, the explanation will be omitted.

On the other hand, the address of the ninth instruction according to A□ is created by the address adder circuit 46 and stored in the IC 45. When the execution of A1 by the microinstruction is completed, a request for the next instruction is issued from the C3 CONT 34, the address signal stored in the IC 45 is supplied to the main memory 1, and the above-mentioned operations are all repeated. A□+ belonging to the instruction group of
A2...An instruction is executed.

Next, the operation in the case of software instruction B□ belonging to the second instruction group will be explained. In the case of a counterfeit, the instruction read out from the software program 11 in the main memory 1 by the address signal of the IC 45 and stored in the lR 41 is B□. In B□, the address of the next instruction is stored in the IC 45 in the same manner as in A above. Furthermore, the address of C831 specified by B□ is 5AR through all connection lines 105.
32 to the C831 and the microinstruction stored at the address is read out. The control operation executed by the microinstruction (referred to as MI□) read by B1 is to generate a control signal, set FF35-i, and
5 to data retention state and EXC48 to l047
Address data supplied from C3CONT34 to switch history to select all connections if! lif? via IC
47, the address data is supplied to the main memory 1 via EXC48t, and the data is stored at the address B1.
The purpose of this is to read out the instruction program corresponding to the .

The address is the address specified by B1, and B0 is the address specified by A.
This is the start address of the main memory area where the instruction program written in is stored. In this way, the instruction program group 12 stored in the p main memory 1 is accessed by the microinstruction, and the first instruction Ai' (i7 fetched lR
41. AI is a software instruction belonging to the first instruction group, and is executed by horizontal microinstructions stored in the C831 in the same manner as described above. Below B□
Software instructions forming an instruction program corresponding to A I+1 r A I+2 +...A, +. are read sequentially and executed in the same way. Finally, the last software instruction A of the instruction program corresponding to B□. is extracted and stored in lR41. The control operation executed by the microinstruction (referred to as +vtIo) stored in C831 that is connected to Ao generates a control signal to FF35! j
The first step is to select the booter of the IC 45 by setting EXC 48e, supplying the address data to the main memory, and reading out the next instruction of the software program 11 stored at the address. Since the address data stored in the IC 45 is the address at which the instruction following %B1 is stored, the unread instruction becomes the instruction to be executed following B□. As described above, for A belonging to the first software instruction, a highly horizontal microinstruction is used and executed as before, and for B belonging to the second software instruction, the instruction program written in A is executed. It is stored in main memory 1 as a micro-controller by Bn. accesses and executes the command program to execute the last software command A. Microinstruction 1VliIo
ft is executed and the program moves to execution of the software instruction following Bn.

By doing so, the number of inefficient horizontal microinstructions stored in the control memory 31 is significantly reduced, and the control memory 31 can be used efficiently.

If the second software instruction group is made into a microprogram, the microprogram will be different for each computer system and must be designed for each system, but if it is made into an instruction program, it is written in software instructions. Therefore, it is highly compatible and only needs to be designed once.

As described above, the present invention can significantly reduce control memory by executing software instructions by a microprogram and executing the microprogram via an instruction program, and is compatible with other systems. This has the effect of allowing microprogram control that is rich in functionality.

In this embodiment, an example is shown in which the software instructions of the second software instruction group are composed of the first software instructions except for tvtI, , mIo, but the present invention is not limited to this. In other words, even when some of the second software instructions are executed directly by the microprogram and others are executed via the first software instructions, the microinstructions 1VII are related to the software instructions of the cylinder 2.
, , 1VI1. The present invention can be applied with some modifications.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. In the figure, 1... main memory (ytM), 2...
Arithmetic circuit, 3...Control memory circuit, 4...
・Instruction data fetch circuit, 11... Software program, 12... Instruction program group,
31... Control memory (C8), 32...
Control storage address register (SAR), 33...
・Address addition circuit (10m bar 34...Control memory control circuit (C8CONT), 41...Instruction register (IR), 42...Address adder (ADD)
), 43...Address register (AR), 44
...Data register (DR), 45...
・Instruction counter (IC), 46...address addition circuit (-1-n), 47...instruction counter C
IC), 48...Switching circuit (EXC), 101
~119... Connection line.

Claims (1)

Claims: A data processing device controlled by a microprogram stored in a control memory, comprising: a software program having a first type of software instructions and a second type of software instructions; storage means for storing an instruction program in which at least a part of each function of the software instructions is constituted by a first type of software instructions; address setting and holding means for setting an address, holding the address in response to the supply of a second type of signal, and releasing the holding in response to the supply of the first type of signal; an address setting means for setting an address of a software instruction to be read from an instruction program, and an address setting means for selecting the address supplied from the address setting holding means in response to the supply of the first type of signal, selection means for selecting an address supplied from the address setting means in response to the supply; and when the software instruction read from the storage means according to the address supplied from the selection means is a first type of software instruction; A second type of software instruction includes a control means for executing the instruction according to the microprogram stored in the value control memory, and a software instruction read from the storage means according to an address supplied from the selection means. In this case, the microinstruction of the microprogram specified by the instruction generates the second type of signal and sets a predetermined value to the second type of signal.
A microprogram control device comprising: address supply means for supplying the address setting means as an execution start address of the instruction program corresponding to the type of software instruction; and means.