JPS59197918A - Serial buffer device - Google Patents

Abstract

PURPOSE:To minimize the hardware of a CPU and give a buffer function to numerous terminal devices, by installing each one of S-P converter and P-S converter to a serial buffer device. CONSTITUTION:Asynchronous data sent from a CPU to plural terminal devices T1-T4 are inputted into the serial-parallel (S-P) converter 12 of a multi-output type serial buffer device 10 through a data line 11. Every one character input of the data parallel-converted by the converter 12 is inputted into a microprocessor 13 as an interrupt signal. The inputted signal is stored in buffer memories M1-M4 in accordance with interrupting softwear at the processor 13. At the processor 13, the receiving condition of the devices T1 and T4 is monitored at the same time and the data of the memories M1-M4 are added to a parallel- serial (P-S) converter 14. The data added to the converter 14 are parallel-converted by the converter 14 by switching a multiplexer 17 in accordance with the designation of the processor 13. Then, data are outputted from a multiplexer 15 to each device T1-T4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-output buffer device that is effective for transmitting data from a high-speed central processing unit to a low-speed terminal device.

Generally, the central processing unit of a computer or instrumentation control system is
Since internal data processing is performed at high speed, input/output to terminal devices such as typewriters and CRTs must also be performed at high speed.

However, these terminal devices are inherently slow due to their mechanism and man-machine interface conditions, and the effective speed of data transmission considering the transmission frequency in the case of an asynchronous type is extremely slow. For this purpose, a terminal buffer area is provided in the main memory of the central processing unit and a spooler is implemented using software, or a terminal device, or even a buffer device, is provided on the output data line to adjust the speed. Conventional measures have been taken. However, in the former case, the memory capacity of the central processing unit decreases, part of the processing speed is lost due to spooling program execution, and the software becomes more complex, resulting in a software cost of 1 to 1.
In the latter case, the same number of back 7 devices as the number of terminal devices is required, which increases the hardware cost. Furthermore, when the system is expanded to include an increase in the number of terminal devices, both of these devices are required by the central processing unit. The latter method has the disadvantage that one buffer device must be added for each terminal device that increases as described above.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and is capable of outputting data from the central processing unit to a large number of output terminal devices by connecting to one output line from the central processing unit. The purpose of this invention is to provide a novel multi-output serial buffer device.

Hereinafter, the present invention will be explained with reference to the drawings. Fig. 1 is a system diagram showing an embodiment of a multi-output type serial buffer device 10 based on four filters. 12 is a serial-to-parallel converter, 13 is a microprocessor + Ml to Mto are buffer memories corresponding to asynchronous terminal devices T1 to T4.

14 is a parallel-to-serial converter, 15 is a demultiplexer, 16 is a baud rate generator, and 17 is a multiplexer.

＼ Multi-output serial buffer device 10 configured in this way
To explain the operation, data h<9600 bp is sent from the central processing unit (not shown) to each terminal device T1--.
S is assumed to be input to the serial-to-parallel converter 12 via the output data line 11 in the form of an asynchronous signal of S. The structure of the data input to this serial/parallel converter 12 is as shown in FIG. The terminal device number of the data transmission destination is attached.This serial data is sent to the serial/parallel converter 1.
2, parallel conversion -1d"', heat, and a small parallel signal is sent to the microprocessor 13 every time one character is input.

The microprocessor 13 has a buffer memory M corresponding to the terminal devices T1 to T4 specified by the interrupt processing software.
The data that should not be sent is stored in the husband of +-M+. That is, the letter A.

B, C, D to buffer memory M1, characters E, F-.

G, H to buffer 1 memory Mi, character 1. J.K.

L is stored in the buffer memory M8, and characters M, N, O, and P are stored in the buffer 7 memory M1, respectively.

At the same time as this storage operation, the microprocessor 13 monitors whether transmission data can be received among the terminal devices 1 to T, and stores the data in the first one of the corresponding buffer memories M+-M+ for the terminal devices that can receive the data. The received data is transmitted sequentially.

In this case, the output data is transmitted to the parallel-to-serial converter 14.
The transmission clock Ck at this time is the output of the baud rate generator 16)] is switched by the multiplexer 17 according to instructions from the microprocessor 13 to obtain the transmission speed of each individual port rate output of the terminal devices T1 to T4. It is something that can be done. That is, for example, the data A to be sent to the terminal device T.

8, C, D are 110 bpS, data sent to terminal device Nh E,;
ps, data sent to terminal N T4 M, N, O
, Pc is set to 9600 bps (7) transmission once, etc. When the multiplexer 17 switches the transmission clock ck, the microprocessor 13 at the same timing switches the demultiplexer 15 to send the above-mentioned transmission data A, B, C, D to the terminal device T1, for example.
It is configured to transmit data via the data line L1 at a transmission rate of 10 bps (7), and the following terminal devices Tx, T
, y, and T4, the data line is included at the transmission speed corresponding to the above-mentioned sending data.

j, and 14, respectively.

Therefore, when expanding the system, it is necessary to add software on the central processing unit side, but unlike the conventional system, there is no need to add interface hardware.

As described above in detail, according to the multi-output serial buffer device according to the present invention, the interface hardware of the central processing unit can be prepared for one terminal device regardless of the number of terminal devices to which data should be sent. As a result, the cost of the hardware of the central processing unit can be reduced, and therefore system expansion is easy. By providing one each, the buffer device has advantages such as being able to provide a buffer function to a large number of terminal devices, although it is almost the same as a conventional single output type buffer device.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an embodiment of a multi-output serial buffer device according to the present invention, and FIG. 2 is a diagram showing the structure of input data. 10...Multi-output serial buffer device 12...Serial/parallel converter 13...Microprocessor 14...Parallel 8/serial converter 15...Demultiplexer 16...Baud rate generator 17...・Mall γ plexer M1~・Loincloth buffer memory T1~T4...Asynchronous terminal device J11~ノ+...Data transmission line Patent applicant Japan Radio Co., Ltd.

Claims (1)

[Claims] Sending from the central processing unit to multiple aperiodic terminal devices = m,
A serial-to-parallel converter receives serial data as 15x transmission data via a single output line and converts it into parallel data for each character, and stores the parallel data for each character separately for each terminal device. A plurality of buffer memories, a parallel/serial converter that converts character data stored in the buffer memory into serial data, a baud rate generator that outputs a plurality of clock lines, and a clock line from the baud rate generator to the terminal device. a multiplexer that selects a clock that matches the reception transmission speed of the serial data and sends it to the parallel-to-serial converter; a demultiplexer that switches the serial data to a data line to be sent out for each terminal device; The parallel data is stored in the plurality of buffer memories for each terminal device, and the parallel data is extracted from the buffer memory for each terminal device, and the parallel data is sent to the multiplexer to match the receiving transmission speed of the terminal device. The central processing unit converts the output data received via the output line of 9 (S) and the serial data of J into parallel data, and 1. A multi-output serial buffer device, characterized in that it is configured to transmit data to an asynchronous terminal device through separate data transmission lines.