JPS59197879A - Synchronizing circuit of signal - Google Patents

Abstract

PURPOSE:To synchronize completely a signal whose time is different in processing unit by processing a processing unit changing circuit, making a time of a processing unit of one signal coincide with a time of a processing unit of the other signal, and thereafter, synchronizing a signal by a synchronizing circuit, and simultaneously, a generating a coincidence signal. CONSTITUTION:A video signal V1 of 1/2NM unit is inputted to an input terminal 5, and also, a video signal V2 of 1/3NM unit is inputted to an input terminal 6 and inputted to a processing unit changing circuit 10. A time of a processing unit is changed to 1/2NM from 1/3NM at every 1NM unit, and outputted as a video signal V2'. In a synchronizing circuit 11, a notice is taken to the range of + or -1 of a processing unit corresponding to V1 on a processing unit of the video signal V2' basing on a processing unit in which the video signal V1 exists, as a reference, and if the video signal V2' exists in its range, it is synchronized, and simultaneously, a coincidence signal for showing its time is generated. The coincidence signal is inputted to a storing and controlling circuit 12 and stored temporarily. The synchronizing circuit 11 is operated by using a read-out signal as a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal synchronization circuit, and more particularly to a synchronization circuit for input signals whose processing units have different times, which are used in radar equipment and the like.

FIG. 1 is a schematic block diagram showing an example of a signal processing device of a conventional radar device.

First, a conventional signal processing device for a radar device will be explained with reference to FIG. A response from a reflecting target such as an aircraft received by the antenna 1 is normally outputted via the receiving device 2 as a video signal v1. Also, if necessary,
7 by providing another processing device 3 and obtaining a new video signal 2 corresponding to the response from the aforementioned reflective target.
, to improve performance or add functionality. The above-mentioned video signal v1 or V2 is a video signal displaying a reflective target, and is obtained on the image as shown in FIG. Video signal V1. V2 is input to the signal processing device 4, and the signal is detected. To perform signal detection, first, the input signal, the video signal V1. It is necessary to synchronize V2, and for this purpose, a synchronization circuit 9 shown in FIG. 2 is provided inside the signal processing device 4. usually,
The signal processing device 4 divides the input video signal into time units corresponding to predetermined distances and performs signal processing.

For example, here, the video signal v1 input to the input terminal 5 of FIG. 2 is shown in FIG. 4A, and the unit Lt 1 /
2 NauNcal M He (hereinafter referred to as NM
). Further, the video signal v2 inputted to the input terminal 6 of FIG. 2 is shown in FIG. 4B, and the unit is 1/3 NM. Video signal v1 and video signal v2 have the same processing unit time for each INM, but 1, / 2 N
They do not match in M units and 1/3 NM units. Therefore, the signal processing device 4 must first synchronize the video signal @V1 and the video signal v2, and then perform signal processing. In FIG. 4A, . indicates a video signal v1 having a unit of 1/2 NM, and in FIG. 4B, .mu. indicates a video signal V2 having a unit of 1/3 NM. FIG. 4C shows a side-by-side comparison of the video signal V11 and the video signal 2, where the video signal v2 can be associated with either the processing unit R1 or R2 of the video signal @V1.

Therefore, for video signal v1, video signal @V2
If we compare them as they are, what should originally be synchronized as shown in Fig. 4D becomes as shown in Fig. 4E. That is,
Although the processing unit in FIG. 4E has been changed from 1/3 NM to 1/2 NM, synchronization cannot be achieved due to jitter.

Since the conventional signal synchronization circuit is configured as described above, it has not been possible to completely synchronize input signals having different processing units of time.

As a result, the accuracy of signal detection in the signal processing device inevitably deteriorates, and there have been cases where a video signal from one reflecting target is separated and captured as a separate target.

Therefore, the main object of the present invention is to provide a synchronization circuit capable of eliminating the above-mentioned drawbacks and completely synchronizing signals whose processing units have different times.

In summary, the present invention provides a processing unit change circuit,
After the time of the processing unit of one signal is made to match the time of the processing unit of the other signal, the signals are synchronized by the synchronization circuit and a matching signal is generated at the same time.

The coincidence No. 5 is stored in the storage circuit 10, and the coincidence signal is read out as a control signal at the next signal detection, and is input preferentially using the position of the control signal as a reference (synchronization of No. 4 is performed, and the coincidence is again performed. generate a signal.

By continuously repeating the above operations, complete synchronization can be achieved and signal detection without jitter can be achieved.

The above objects of the invention and the objects and features of the pond will become more apparent from the detailed description given below with reference to the drawings.

FIG. 5 is a schematic block diagram showing a synchronous circuit which is an embodiment of the present invention.

The example shown in FIG. 5 includes a processing unit changing circuit 10. which changes the processing unit of the input video signal V2 from 1,/3 NM to 1/2 jM. A synchronization circuit '11 synchronizes the input video signal @v1 and the output video signal 2' from the processing unit change circuit 10 and generates a coincidence signal, and a synchronization circuit '11 that temporarily stores the coincidence signal and sends it to the synchronization circuit 11 as a control signal t1'. It is composed of a storage/control circuit 12 that outputs an l signal. 6A and 6B are diagrams showing signal processing for explaining the embodiment shown in FIG. 5. FIG.

Next, the operation of the embodiment shown in FIG. 5 will be described with reference to FIGS. 6A and 6B.

In Fig. 5, the input terminal 5 has a unit 1 shown in Fig. 4A.
/2NM video signal v1 is input.

Further, the input terminal 6 receives a video signal 2 having a unit of 1/3 NM as shown in FIG. 4B. The video signal ■2 is input to the processing unit changing circuit 10, and as shown in Fig. 6Δ, the processing unit time is changed from 1/3NM to 1/2 every 1NM.
The signal is changed to NM and output as a video signal V2'. The video signal 1 and the above-mentioned video signal V2' are input to the synchronization circuit 11. In the synchronization circuit 11, as shown in FIG. 6B, with the processing unit in which the video signal v1 exists as a reference, attention is paid to the range of ±1 of the processing unit corresponding to the above-mentioned (1) on the processing unit of the video signal V2', If the video signal V2' exists within that range, synchronization occurs at the time of the processing unit in which the video signal v1 exists, and at the same time a coincidence @ sign indicating that time is generated. The coincidence signal is input to the storage/control circuit 12 and is temporarily stored. In the storage/control circuit 12, the minimum bit of the address is 1/2NM, which corresponds to the processing unit of the coincidence signal. Therefore, the coincidence signal once stored in the storage/control circuit 12 can be read out during the next sweep for a period of time corresponding to the same processing unit as the previous sweep. The synchronization circuit 11 operates using the signal read from the storage/control circuit 12 as a control signal. Synchronous circuit 1
Video signal 1 and video signal V2' are input to 1, but when the control signal is input, the time of the processing unit in which the control signal is input, that is, Vl and Vl at the time of the previous sweep. The video signal V2' is preferentially synchronized at the same processing unit time as the position where V2' coincides, and a coincident signal is output as in the previous case. The above operation is performed using video signal V2.
The synchronization circuit 11 generates a coincidence signal and outputs a synchronized video signal. By adding the processing unit change circuit 10 and the storage/control circuit 12 to the synchronization circuit 11 in this way, jitter as shown in FIG.
As shown in the figure, complete synchronization can be achieved.

By the way, in the above-mentioned practical example, an example was explained in which both the video signal A1 word ■1 and the video signal ■2 exist, but the case where the video signal v1 is not input and only the video signal V2 is input is explained. Also, it becomes clear by i!iI1wJ(g\J) which distance, that is, which processing unit time, and there is no jitter.

As described above, according to the present invention, a processing unit change circuit and a storage/control circuit are added to a synchronization circuit, and a coincidence signal generated from the synchronization circuit is used as a control signal to be used as a reference for synchronization at the next signal detection. Since the structure is configured so that
This prevents video signals from two targets from being perceived as separate images.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an example of a signal processing device of a conventional radar device. FIG. 2 is a schematic block diagram showing a conventional synchronous circuit. FIG. 3 is a diagram showing an example in which a video signal indicating a response from a reflective target is displayed as an image. , FIG. 4A and FIG. 4B represent video signals having different processing units of time. FIG. 4C shows a comparison of the horizontal wrinkles of the video signals at different processing unit times. Figure 4D is a diagram representing a fully synchronized video signal. , FIG. 4E is a diagram representing a jittered video signal. FIG. 5 is a schematic block diagram of one embodiment of the present invention. FIG. 6A is a signal 18 diagram of the processing unit change circuit. FIG. 6B is a signal processing diagram of the synchronous circuit. In the figure, 11 is an antenna, 2 is a receiving device, 3 is another processing device, 4 is a signal processing device, 5.6 is an input terminal,
7 and 8 are output terminals, 9 and 11 are the same) No. 1 circuit, 101:
! Processing unit change circuit, 12 is memory! 11 control circuit is shown. 1st person immediately person rock increase t
Figure @3 eyes 12-biwei'' Figure 4A Figure 4B Figure 4C Figure 4D Figure 4E Figure 5 Figure 6A Figure 68

Claims (1)

[Scope of Claims] A circuit for synchronizing signals whose processing units have different times, comprising: a processing unit changing circuit that matches the processing unit time of one signal with the processing unit time of the other signal; a synchronization circuit that synchronizes the input signals whose processing units coincide with each other in the unit change circuit, and simultaneously generates a coincidence signal indicating the time of the processing unit in which the synchronized signal exists; and a synchronization circuit that temporarily stores the coincidence signal; and a storage/control circuit that outputs the coincidence signal as a control signal to the synchronization circuit, and the synchronization circuit synchronizes the input signals by preferentially using the control signal as a synchronization reference and generates the coincidence signal again. A signal synchronization circuit is characterized in that synchronization is achieved by continuously repeating this operation.