JPS59195836U - analog/digital converter - Google Patents
analog/digital converterInfo
- Publication number
- JPS59195836U JPS59195836U JP9095983U JP9095983U JPS59195836U JP S59195836 U JPS59195836 U JP S59195836U JP 9095983 U JP9095983 U JP 9095983U JP 9095983 U JP9095983 U JP 9095983U JP S59195836 U JPS59195836 U JP S59195836U
- Authority
- JP
- Japan
- Prior art keywords
- successive approximation
- analog
- signal
- digital
- digital converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は先行技術でありADCが超音波流量計として用
いられている所を説明するための図であり、第2図は本
−考案のADCであり、第3図及び第4図は本願考案を
説明するためのフローチャート及び制御信号Xと桁指定
信号Yとの関係図である。
1・・・アナログ/デジタル変換器(ADC)、2・・
・デジタル/アナログ変換器(DAC)、5・・・比較
要素、7・・・データ長レジスタ、Y・・・桁指定信号
、G・・・クロック信号。Figure 1 is the prior art and is a diagram for explaining where the ADC is used as an ultrasonic flowmeter, Figure 2 is the ADC of the present invention, and Figures 3 and 4 are the diagrams of the present application. 2 is a flowchart and a relationship diagram between a control signal X and a digit designation signal Y for explaining the invention. FIG. 1...Analog/digital converter (ADC), 2...
- Digital/analog converter (DAC), 5... Comparison element, 7... Data length register, Y... Digit designation signal, G... Clock signal.
Claims (1)
てデジタル信号に変換すうアナログ/デジタル変換器に
おいて、 A 上記逐次近似手段の逐次近似する桁を制御する桁指
定信号を出力するデータ長レジスタと、B 上記逐次近
似手段よりのデジタル信号と上記桁指定信号とを入力し
、あらかじめ設定された判定値と上記各信号とを比較し
上記データ長レジスタの出力する桁指定信号を制御する
ための上・下限信号を出力する比較要素とを具備し、C
上記桁指定信号を入力された上記逐次近似手段は、指定
された桁より上位は前回のデジタル信号が出力され、指
定された桁より下位について逐次近似を行いそのデジタ
ル信号が出力されるように構成されたことを特徴とする
アナログ/デジタル変換器。[Claims for Utility Model Registration] In an analog/digital converter that converts a repeatedly given analog signal into a digital signal using successive approximation means, A. outputs a digit designation signal that controls the digits to be successively approximated by the successive approximation means. B inputs the digital signal from the successive approximation means and the digit designation signal, compares each of the signals with a preset judgment value, and determines the digit designation signal output from the data length register. and a comparison element that outputs upper and lower limit signals for control.
The successive approximation means, which receives the digit designation signal, is configured to output the previous digital signal for the higher-order digits than the designated digit, perform successive approximation for the lower-order digits, and output the digital signals. An analog/digital converter characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9095983U JPS59195836U (en) | 1983-06-14 | 1983-06-14 | analog/digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9095983U JPS59195836U (en) | 1983-06-14 | 1983-06-14 | analog/digital converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59195836U true JPS59195836U (en) | 1984-12-26 |
Family
ID=30220923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9095983U Pending JPS59195836U (en) | 1983-06-14 | 1983-06-14 | analog/digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59195836U (en) |
-
1983
- 1983-06-14 JP JP9095983U patent/JPS59195836U/en active Pending
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