JPS59193651A - Packet transmitter - Google Patents

Abstract

PURPOSE:To decrease the number of times of ineffective packet exchange by providing a check bit area corresponding to each node to a received packet, writing a check bit at each passing of each node and deciding the state of the check bit area. CONSTITUTION:The received packet is inputted to a write control section WCT and written in packet areas PC1-PCn of a memory MEM by referencing statement areas ST1-STn. Further, a check bit deciding section JG1 decides whether or not the packet passes through the own device in the past and when it is decides that the packet passes through, the packet is ablished. On the other hand, when it is decided that the packet does not pass through the deciding section JG1, an address deciding section JG2 decides whether the packet is directed to the own device or the other device and transmits the packet to a receiving pocessing section REC or a transmission section SEN respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a network in which packet switching equipment is used as a node, and it is possible to check each packet by providing a check area indicating the nodes through which each packet passes. This invention relates to a packet transmission device that prevents packets from being endlessly exchanged within a network and not being output to devices outside the network.

Prior Art and Problems The conventional configuration for preventing infinite loops is to provide a counter for the number of exchanges in the packet, count up for each exchange node, and when the counter exceeds a certain number, an infinite loop is entered. There is a configuration that determines that this is the case and discards it, but in this configuration, when an infinite loop occurs, it is determined that an infinite loop has occurred only after the loop has been repeated a certain number of times, and this determination condition is wasteful. As a data collection and distribution device, unnecessary packets had to be exchanged, which was a major hindrance for this system, which strongly required a fast response time.

Purpose of the Invention The purpose of the present invention is to store bit information corresponding to each node in a check area for each packet, and check the corresponding bits each time the packet passes through a node, thereby preventing the packet from falling into an infinite loop. An object of the present invention is to provide a keratin transmission device that can reduce the number of invalid keratin exchanges by taking full advantage of the possibilities.

Structure of the Invention The object of the present invention is to provide a memory for storing a received message, and to determine whether the message has passed through the own device in the past based on the state of a check bit included in the message stored in the memory. a check bit determination unit that determines whether or not the packet has passed through the device; a discard unit that discards the packet when the check bit determination unit determines that the packet has passed through its own device in the past;
When the check bit determination unit determines that the packet has not passed through the self-device, the destination determination unit determines the destination of the packet, and the destination determination unit determines whether the packet is suitable for self-equipment. This is achieved by a packet transmission device characterized in that it has a reception processing unit that performs time reception processing, and a transmission unit that performs time transmission for the destination determination unit and/or other devices.

Embodiment of the Invention A network to which the device of the present invention is applied is shown in FIG. Each node 1 to 7 in the network turns on the bit in the check area CH corresponding to its own node in the packet format of FIG. 2 every time it is exchanged. Next, consider the case where a packet is sent from node 1 to node 7-4 in the network. ■−■−■−■ is considered as one of the shortest transmission paths, and in fact, when a packet to be sent from 1 to 7 enters node 1 in the packet switching equipment corresponding to each node, node 1 sends it to node 2. Suppose that the respective tables are created such that node 2 outputs to node 4, node 4 outputs to node 7, and so on.

Packets are exchanged one after another from node 1, and the packet sent to node 7 reaches node 4, and then 7
Let's consider what happened when we tried to move to . At this time, if the line goes down, node 7'-4 avoids the line and transmits the packet to node 3. Node 3 transmits it to node 2 as the shortest route to 7. However, without knowing that the line was down on node 2, node 4 reconnected.
If the packet is transmitted, the result will be an infinite loop of ■−■−■.However, in the current plan, the infinite loop continues to be repeated, and the packet is discarded only when the number of determinations has been reached. However, in this case, if the packet re-traces a node that it has passed once in the past, the corresponding check bit is turned on, so that information can be immediately known, and the packet can be immediately discarded. Even in this case, it is discarded immediately upon returning to node 2.

FIG. 3 shows an embodiment of the invention.

In the figure, WCT Ii write control unit, RCT is read control unit, MEM is memory, JGl is input determination unit, SET is check bit circuit, JG2 is header determination unit, JG3 is status area determination group, and RFC is reception processing. Department, SEN is the transmission department, Bangoda Sashio Eiji Takami PC, ~
P Cn is a packet area, AD1 to ADπ are address areas, CH1 to CHn are check areas, and ST, to STn are statement areas.One memo IJMEM has packet areas PC1 to PCn where received packets are sequentially written, and each packet is , a statement area ST indicating whether the item has already been processed for reception or transmitted to the next station, ~ST
n is provided.

To explain the operation, the received packet is written to the statement area S T under the control of the write control unit WCT.
+~Memo with reference to STn') MEM packet area PC
, ~P Cn.

At system startup, statement areas ST, ~STn
writes %1'' to indicate that all packets in the packet areas PC0 to PCn have already been processed for reception or sent to the next station.

Therefore, this packet is unnecessary for the device in question, so
It will be rewritten with the newly received packet.

When rewriting to a new packet, write %0 into the corresponding statement area.

The write control unit WCT determines that if the statement areas are the same, the corresponding bucket area cannot be written to. read out,
It is given to the check bit determination unit JG1.

The check bit determination unit JG1 determines whether the check bit is 61" or 10rr, and determines whether the check bit is 61" or 10rr.
If so, start the check pit set section SET and set the check area to "eye" via the 1-inclusive control section WCT.On the other hand, the original collection @ section RCT starts the check pit setting section SET through the 1-inclusive control section WCT. When the area is East O〃, all the contents of the packet area are read and the address judgment unit J
Input to G2.

The address determining unit JG2 determines whether the address in the packet matches the address of the own device. If it matches, the self-equipped southbound packet is input to the receiving processing VAREC as a packet, and if it does not match, it is input to the transmitting unit SEN.

The reception processing unit RFC performs processing such as code conversion for display on a printer or display, and the transmission unit SEN sends the packet to the next device. In addition, address determination unit JG
2, the write control circuit WCT is notified of the end of the determination, and the write control circuit WCT writes %1'' into the statement area corresponding to the read packet area.

When the check bit area is 1, it is determined that the packet has passed through the device itself in the past, and the write control circuit W
Notify the CT that it cannot write ``1'' in the corresponding statement area.

Effects of the Invention As described above, according to the present invention, a check bit area corresponding to each node is provided in a packet, and each time a packet passes through each node, a check bit is written and the state of the check bit area is determined. Therefore, packets that have entered an infinite loop can be detected quickly.

[Brief explanation of drawings]

FIG. 1 is a system diagram to which the present invention is applied, FIG. 2 is a diagram showing a packet format used in the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. In the figure, 1 to 7 are nodes, WCT is a write control section, RCT is a read control section, and MEM is a memo! J, JGI is a check bit determination unit, and SET is a check bit setting circuit. JG2 is a header determination unit, JG3 is a status area determination unit, RFC is a reception processing unit, SEN is a transmission unit, #D-=Image Shimo; master PC1 to PCn are packet areas, AD. ~A D n is an address area, and cHl-cHn are statement areas. No. 11Z/ Otsu d No. 2 U

Claims (1)

[Claims] A memory for storing received packets, a check pit determination unit for determining whether or not the bucket has passed through the own device in the past based on the state of check bits included in the packet stored in the memory; A discard unit that discards the packet when the Tsukubit determination unit determines that the packet has passed through the self-equipment lid in the past, and a discard unit that discards the packet when the check pit determination unit determines that the packet has not passed through the self-equipment. A destination determination unit that determines the destination of the packet; a reception processing unit that performs reception processing when the packet is destined for self-equipment; and a reception processing unit that performs reception processing when the packet is destined for the device itself; What is claimed is: 1. A packet transmission device comprising: a transmitter for transmitting data.