JPS59191198A - Memory protecting device - Google Patents

Abstract

PURPOSE:To perform unitarily memory control by a central processing unit by designating an accessible memory area from the central processing unit for each input/output channel and protecting the memory area. CONSTITUTION:A memory protecting device 106 judges whether a selected input/ output channel is going to access to a memory of an area designated beforehand. When it is working correctly, a memory access permission signal 107 is outputted to a memory system 102. When an input/output channel is going to access the memory, it is judged whether the memory address is in the designated area, and the memory access permission signal 107 is outputted only when the memory address is in the area. Accordingly, the memory can be protected scrupulously for each input/output channel. Further, by monitoring the generation of the memory access permission signal 107, an input/output channel having generated troubles can be judged easily and in an early stage.

Description

Detailed Description of the Invention (Field of Application) The present invention relates to a memory protection device for a computer system (related to Regarding equipment.

(Background) Traditional memory protection in computer systems is
Usually, the purpose is to prevent system programs, existing programs, or other user programs from being destroyed intentionally or inadvertently when executing an application program created by a user, and for security purposes. This is done from the perspective of

Therefore, for I/O devices, because they are part of the system, there is generally no protection of memory from the I/O devices or channels;
Or, at present, this is done for all input/output devices or channels at once.

However, as is well known, in computer systems where the input/output channels themselves are highly intelligent, the input/output channels can freely use memory at their own discretion, beyond the control of the central processing unit. will be accessed.

For this reason, there is a possibility that some kind of trouble may occur in the input/output channel itself, resulting in an accident such as accessing a memory area that should not be accessed. In most cases, it is almost impossible to investigate the cause of such accidents.

Therefore, it is important to protect memory from individual I/O channels so that they do not access memory that they should not access, and to remember when such a situation occurs. , it is desired to develop a method that facilitates later investigation of the cause.

(Objective) An object of the present invention is to provide a memory protection device that allows the central processing unit to centrally manage memory management by specifying and protecting accessible memory areas from the central processing unit for each input/output channel. There is something to do.

Another object of the present invention is to dynamically allocate a plurality of accessible memory areas to each input/output channel (as the program progresses). An object of the present invention is to provide a memory protection device capable of protecting memory.

(Overview) In the present invention, when an input/output channel attempts to use a bus, first (1) it sends a bus request (BUSRE) to the bus arbiter.
QUEST), and (2) start using the bus only after receiving the bus use permission signal output by the bus arbiter in response, and when the bus use signal is issued. In order to determine which input/output channel is using the bus, the contents of the RAM written in advance according to the input/output channel can be determined by comparing it with the memory address on the bus. iC% that determines whether or not memory access is possible from input/output channels
There are signs.

Furthermore, when the input/output channel accesses the memory, the present invention simultaneously outputs an identification signal of the accessible memory area allocated to the supported input/output device, and based on this, the input/output device Correspondingly, an address signal of a RAM storing a predetermined upper limit value and lower limit value of a memory accessible area is generated, and
A feature of the present invention is that by comparing the memory address signal read from M with the memory address signal on the input/output interface bus, it is determined whether or not the memory can be accessed from the input/output channel.

(Example) Embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the positioning of the memory protection device of this embodiment in a computer system.

Central processing unit 101 and multiple input/output channels 10
3 and memory system 102 are interconnected by an input/output interface 7 eighth bus 104.

In addition, each input/output channel 103 has a bus exchange control line 1
05 (consisting of a bus use request signal line and a bus use permission signal line) is connected to a bus arbiter (assumed to be included in the central processing unit 101 in the present embodiments ζ and ζ).

106 is a memory storage system according to the present invention, which determines whether the selected input/output channel is attempting to access a memory in a pre-specified area, and if it is operating correctly, Memory access permission signal 10
7 to the memory system 102.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the present invention. A BG (bus use permission) signal 201 (transmitted on the bus exchange control line 105) is latched by a latch and decoder circuit 202 and converted into a RAM address signal 203, which is input to the addresses of the high speed RAMs 204 and 205.

As a result, R corresponding to the selected input/output channel tc
The contents of AM204, 205 are read and output. In the corresponding addresses of these RAMs 204 and 205, the upper and lower limits of memory addresses that can be used by the selected input/output channel are stored as will be described later.

The lower limit value 206 and upper limit value 20 read in this way
7 and the memory address signal 208 on the bus 104 are respectively supplied to a comparison circuit 209 for comparison. For example, the following relationship, (206)≦(208)<(20
7) Only when the following holds true, the memory access permission signal 107
Output. This allows the selected input/output channel to access memory 102.

FIG. 3 is a block diagram showing a more specific example of the configuration shown in FIG. 2.

3 (H is a decoder that decodes the input BG signal 201. 302 is the decoded BG information 31
1 latch circuit, B B S Y (bus in use)
From the signal 3031, the BG information 311 - that is, R
Latch the AM address signal.

305 is a multiplexer that switches and selects the RAM address signal, and when the input/output channel is not in operation (
In other words, when the BBSY signal is not output),
In order for the processing unit 101 to access the RAMs 204 and 205 for reading and writing, another RAM is provided.
M address signal 304 can be placed in RAM 204.205.

A data buffer 306 is used by the processing device 101 to read and write the memory protection boundary value 309 of the RAMs 204 and 205. 307 is a comparator for comparing the upper limit value 207 and the lower limit value 206 with the memory address signal 208 on the path 104, and 308 is a comparator that uses the output of the comparator 307 to issue a memory access permission signal 107. This is a judgment circuit for

As is clear from the above explanation (ζ, according to this example,
When an input/output channel attempts to access memory, it is determined whether the memory address is within a prespecified area, and a memory access permission signal is output only when it is within the area. , it becomes possible to perform detailed memory protection for each input/output channel.

Therefore, memory corruption that is difficult to recover from in the computer system can be prevented.

Furthermore, by monitoring the generation of the memory access permission signal 1070, it is possible to easily and quickly determine which input/output channel has caused a failure.

Therefore, it is possible to prevent a complete system stop and quickly recover from a failure, thereby improving the reliability of the computer system.

However, in the so-called one-factor open-type protection device that allocates one memory area to one input/output channel as described above, it is a more sophisticated input/output channel, and the memory space is discrete. The disadvantage is that memory protection is not perfect for devices that can access the area that has been stored.

In other words, - For example, in the case of an input/output channel that can support multiple input/output devices at the same time and allows the central processing unit to access these input/output devices at random, the data handled is The input/output channel itself will allocate the data in a memory area and perform the input/output scheduling of that data.

For this reason, it becomes unclear from the central processing unit which memory area is being accessed.

Therefore, even if an input/output channel accesses the wrong memory area among multiple memory areas allocated to an input/output channel, this cannot be detected.
This causes the inconvenience that complete memory protection cannot be achieved.

To solve this problem, (1) limit the activation of multiple input/output devices at the same time for the central processing unit or one human output channel, or (2) use the necessary amount of memory. Possible methods include providing enough registers in parallel to specify the accessible areas above.

However, the former method is expected to have the disadvantage that it will not be able to fully utilize the capacity of the input/output channel, resulting in a significant decrease in the processing power of the computer system, and the latter method is expected to have the disadvantage that the required hardware will increase. Ru.

A second embodiment of the present invention is intended to improve the above-mentioned drawbacks, and will be described below with reference to FIGS. 4 to 6.

FIG. 4 is a schematic block diagram showing the positioning of a memory protection device according to a second embodiment of the present invention in a computer system. In this figure, the same reference numerals as in FIG. 1 represent the same or equivalent parts.

105A is a register selection line consisting of 0 signal lines provided on the bus 104, and each input/output channel 1
03 to the memory protection device 106.

Note that n is the minimum value necessary to identify discrete memory areas that are simultaneously designated to specific input/output channels. The value of n must be selected so as to satisfy the relationship 2 n'< m <2'', where m is the number of discrete memory areas. If the value of n is selected in this way, , from the input/output channel 103 which attempts to access the memory 102, the identification signal corresponding to the memory area to be used - that is, the binary number m,
Memory protection can be achieved by outputting the information m to the register selection line 105A, selecting the accessible area specifying register pair in the memory protection device 106, and reading the contents thereof.

FIG. 5 is a block diagram showing a schematic configuration of a second embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

The register selection signal (i.e., the aforementioned memory area identification signal = binary number m) on the register selection (hereinafter abbreviated as R8) line 105A is sent to the high-speed RA via the buffer 202A.
RA'M address signal 20 to M204A and 205A
Supplied as 3A.

Note that, as is clear, these high-speed RAMs 204A and 205A constitute a memory protection boundary designation register. The RAM 204A stores the upper limit value, and the RAM 205 stores the lower limit value, and these values are stored in advance in the central processing unit 101 in correspondence with the binary number m.
You can set it from

When the input/output channel 103 accesses the memo 1J102, it is configured to output the R8 signal on the R8 signal line 105A at the same time as the address signal is output on the interface node 104 (details will be described later). Yoshi,
One content in RAM 204A; 205A is selected, and the upper limit value 206 and lower limit value 2 of the memory address are selected.
07, and is output to the comparison circuit 209.

The upper limit value 206 and lower limit value 207 are compared with a memory address signal 208 on the interface bus 104 by a comparison circuit 209. Then, only when the relationship (206)≦(208)<(207) is established, the memory access permission signal 107 is output to the memory 102, and the memory 102 becomes accessible.

Therefore, as is clear, if this R8 signal (that is, the aforementioned memory area identification signal = binary number m) is made to match the number of the input/output device supported by the input/output channel, the central processing unit 101 can By configuring the contents of the RAMs 204A and 205A at the address corresponding to the input/output device to be set immediately before starting an input/output device in the input/output channel, the central processing unit 101
handles data in the order controlled by the input/output channel side without being particularly conscious of scheduling, and at that time the input/output channel displays the number of the input/output device being executed on the R8 line 1.
058, it is possible to dynamically select memory accessible areas.

FIG. 6 is a block diagram showing details of the second embodiment. In the figure, the same reference numerals as in FIG. 3 represent the same or equivalent parts. As in the case of Fig. 3, the bus permission (BG) signal 2 for each input/output channel
01 is decoded by the decoder 301.

The decoded BG information 311 is latched by the latch circuit 302 by the bus busy (BBSY) signal 303.

As described above, this BG information 311 is stored in the high-speed RAM 204A along with the R8 signal output from the input/output channel onto the R8 signal line 105A while the path is in use.

205A becomes the RAM address signal 203A.

305A is the RAM 204A, 205A
This is a multiplexer that switches and selects the address signal of
The address 304 output from the central processing unit 101 and the aforementioned B.G.
The information 311 is switched by the path busy (BBSY) signal 303.

204A is a high-speed RAM used as a register to set the upper limit of the memory accessible area; 205A;
is also a high-speed RAM for setting the lower limit.

Outputs 206 and 20 of these RAMs 204A and 205A
7 is compared with the memory address signal 208 output on the interface bus 104 in the comparator 3071 when the input/output channel accesses the memory 102.

Then, the result is judged by the judgment circuit 308, and the memory address signal 208 is the upper limit value 206 and the lower limit value 20.
7, it is determined that the memo 1J102 is being accessed correctly, and the memory access permission signal 107 is output.

As can be understood from the above, in the second embodiment of the present invention, when the central processing unit 101 accesses an input/output device, the memory retention boundary values (upper limit value and lower limit value) are stored in the RAM. In addition, when an input/output channel accesses memory, the register selection (R8) signal - that is, the identification signal of the accessible memory area is output. It is possible to reliably determine whether the input/output channel is accessing the correct one among the plurality of memory areas that have been accessed.

That is, according to the second embodiment, multiple memory protection areas can be set for one input/output channel. This has the effect of allowing precise memory preservation.

(Effects) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Since one or more memory protection areas (or accessible areas) can be designated by the central processing unit for each input/output channel, unified memory management is possible.

(2) As a result of the above, the input/output channel is completely prevented from accessing the inaccessible area, and programs, data, etc. will not be destroyed, and secrets will not be leaked.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the positioning of the memory protection device of the present invention in a computer system, FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a more specific configuration example of the embodiment. FIG. 4 is a diagram similar to FIG. 1 regarding the second embodiment of the present invention. FIG. 5 is a schematic configuration of the second embodiment of the present invention. FIG. 6 is a block diagram showing a specific configuration example similar to the second embodiment. 101... Central processing unit, 102... Memory system, 103... Input/output channel, 10
4...I/O interface bus, 105...
- Bus exchange control line, 105A... Register selection (R8) line, 106... Memory protection device, 107
... Memory access permission signal, 201 ... Bus use permission (BG) signal, 202 ... Latch decoder circuit, 203 ... RAM address signal, 204
, 205... High speed RAM, 206... RAM
Output (lower limit value), 207...RAM output (upper limit value),
208...Memory address signal, 209...Comparison circuit, 301...Decoder, 302...Latch circuit, 303...Bus in use (BBSY) signal,
304... RAM address signal, 305... Atonenos multiplexer, 306... Data buffer, 307... Comparator, 308... Judgment circuit, 309... Memory protection boundary value patent attorney Taira
Tree Road Person Figure 1 10'1 Figure 2 Figure 3

Claims (4)

[Claims] (1) A central processing unit, a memory, a plurality of input/output channels that can directly access the memory, an input/output interface bus that exchanges information between these, and between the central processing unit and each input/output channel. A memory protection device for a computer system consisting of an IC and a bus switching control line that controls the right to use the bus, and which protects the boundaries of the memory area that can be accessed from each input/output channel - that is, the upper and lower limits of memory addresses. a pair of RAMs that store values; and a decoder that receives a bus use permission signal on the bus exchange control line and outputs a RAM address signal for reading an accessible memory area corresponding to a selected input/output channel. , the RAM address signal,
means for latching by a bus busy signal output from the selected input/output channel; and comparing a boundary value of the memory area read from the pair of RAMs with a memory address signal on the bus by the RAM address signal. and a determination circuit that outputs a memory access permission signal when a memory address signal on the bus is between an upper limit value and a lower limit value of the memory area. (2) The patented device further comprises means for writing an upper limit value and a lower limit value of the accessible area corresponding to each of the input/output channels into the pair of RAMs. (3) Memory protection of a computer system including a central processing unit, memory, at least one input/output channel that can access multiple discrete areas of the memory, and an input/output interface bus that exchanges information between them. The device includes a pair of RAMs that store boundary values of a plurality of memory areas that can be accessed from each output channel, that is, upper and lower limit values of memory addresses, and output from an input/output channel that has the right to use the bus. means for receiving an identification signal of an accessible memory area and correspondingly outputting a RAM address signal for reading a predetermined accessible memory area; means for latching by a bus busy signal output from an input/output channel; and means for comparing a boundary value of a memory area read from the pair of RAMs with a memory address signal on the bus according to the RAM address signal; A memory protection device comprising: a determination circuit that outputs a memory access permission signal when a memory address signal on the bus is between an upper limit value and a lower limit value of the memory area. (4) The patent protection device further comprises means for writing an upper limit value and a lower limit value of the accessible area corresponding to each of the input/output channels into the pair of RAMs.