JPH0226251B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Application) The present invention relates to a memory protection device for a computer system, and more particularly to a memory protection device for a computer system suitable for individual memory protection for input/output channels that allow direct memory access. .

(Background) Conventional memory protection in computer systems typically protects memory from users intentionally or inadvertently when executing application programs written by users.
This is done for the purpose of preventing system programs, existing programs, or other user programs from being destroyed, and for security purposes.

Therefore, for I/O devices, there is generally no protection of memory from the I/O device or channel because it is part of the system, or for all I/O devices or channels. Currently, this is done all at once.

However, as is well known, in computer systems where the input/output channels themselves are highly intelligent, the input/output channels can freely use memory at their own discretion, beyond the control of the central processing unit. will be accessed.

For this reason, there is a possibility that some kind of trouble may occur in the input/output channel itself, resulting in an accident such as accessing a memory area that should not be accessed. In most cases, it is almost impossible to investigate the cause of such accidents.

Therefore, to prevent input/output channels from accessing memory that they should not access,
It would be desirable to develop a means to protect memory from individual input/output channels, and to remember when such a situation occurs, making it easier to investigate the cause later. There is.

(Objective) An object of the present invention is to provide a memory protection device that allows the central processing unit to centrally manage memory management by specifying and protecting accessible memory areas from the central processing unit for each input/output channel. It is in.

Another object of the present invention is to provide a plurality of accessible memory areas for each input/output channel.
An object of the present invention is to provide a memory protection device that can protect memory from each input/output channel by dynamically allocating it (as the program progresses each time).

(Summary) When an input/output channel attempts to use a bus, the present invention first (1) issues a bus request (BUSREQUEST) to the bus arbiter, and (2) responds to this by issuing a bus request (BUSREQUEST) from the bus arbiter. We focused on the process of starting to use the bus only after receiving the permission signal, and when the bus-in-use signal is issued, it is determined which input/output channel is using the bus, and then the bus is used. The feature is that the contents of the RAM written in advance according to the input/output channel are retrieved and compared with the memory address on the bus to determine whether memory access from that input/output channel is possible.

Furthermore, when the input/output channel accesses the memory, the present invention simultaneously outputs an identification signal of the accessible memory area allocated to the supported input/output device, and based on this, the input/output device Correspondingly, predetermined upper and lower limits of the memory accessible area are stored.
By generating a RAM address signal and comparing the memory address signal read from the RAM with the memory address signal on the input/output interface bus, it is determined whether the memory can be accessed from the input/output channel. The points are distinctive.

(Example) Embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the positioning of the memory protection device of this embodiment in a computer system.

Central processing unit 101 and multiple input/output channels 1
03 and memory system 102 are interconnected by an input/output interface bus 104. Each input/output channel 103 is connected to a bus arbiter (assumed to be included in the central processing unit 101 in this embodiment) via a bus exchange control line 105 (consisting of a bus use request signal line and a bus use permission signal line). It is connected to the.

Reference numeral 106 denotes a memory protection device according to the present invention, which determines whether a selected input/output channel is attempting to access memory in a pre-specified area, and if it is operating correctly, prevents memory access. Allow signal 107 to memory system 1
02.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the present invention. BG (bus use permission) signal 2
01 (transmitted on the bus exchange control line 105) is latched by the latch and decoder circuit 202 and converted to a RAM address signal 203, which is input to the addresses of the high speed RAMs 204 and 205.

As a result, the contents of the RAMs 204 and 205 corresponding to the selected input/output channel are read and output. In the corresponding addresses of these RAMs 204 and 205, the upper and lower limits of memory addresses that can be used by the selected input/output channel are stored as will be described later.

The lower limit value 206 and upper limit value 207 read in this way and the memory address signal 208 on the bus 104 are respectively supplied to a comparison circuit 209 and compared. For example, only when the following relationship holds, (206)≦(208)<(207), the memory access permission signal 1
Outputs 07. This allows the selected input/output channel to access memory 102.

FIG. 3 is a block diagram showing a more specific example of the configuration of FIG. 2.

A decoder 301 decodes the input BG signal 201. 302 was decoded
This is a latch circuit for the BG information 311, and the BG information 311-
That is, the RAM address signal is latched.

305 is a multiplexer that switches and selects the RAM address signal, and when the input/output channel is not in operation (that is, when the BBSY signal is not output), the processing unit 101 selects the RAM address signal.
Another RAM address signal 304 is used to access RAM 4,205 for reading and writing.
can be stored in the RAMs 204 and 205.

306 indicates that the processing device 101 uses the RAM 204, 2
This is a data buffer for reading and writing the memory protection boundary value 309 of 05. 307
308 is a comparator for comparing the upper limit value 207 and lower limit value 206 with the memory address signal 208 on the bus 104;
This is a determination circuit that uses the output of the comparator 307 to issue a memory access permission signal 107.

As is clear from the above description, according to this embodiment, when a certain input/output channel attempts to access memory, it is determined whether the memory address is within a prespecified area, and the area is Since the memory access permission signal is output only when the input/output channel is within the specified range, the memory can be protected in detail for each input/output channel. Therefore, memory corruption that is difficult to recover from in the computer system can be prevented.

Furthermore, by monitoring the generation of the memory access permission signal 107, it is possible to easily and quickly determine which input/output channel has caused a failure. Therefore, it is possible to prevent a complete system stop and to quickly recover from a failure, thereby improving the reliability of the computer system.

However, in the so-called one-area open type protection device that allocates one memory area to one input/output channel as described above, it is a more sophisticated input/output channel, and the memory space is discretely divided. The drawback is that memory protection is not complete for those that can access the area.

In other words, - For example, in the case of an input/output channel that can support multiple input/output devices at the same time and allows the central processing unit to access these input/output devices at random, the data handled is The input/output channel itself will schedule the input/output of the data allocated to the memory area.

For this reason, it becomes unclear from the central processing unit which memory area is being accessed.
Therefore, even if an input/output channel accesses the wrong memory area among multiple memory areas allocated to an input/output channel, this cannot be detected and complete memory protection cannot be achieved. This causes the inconvenience of being lost.

To solve this problem, (1) restrict the central processing unit from activating multiple input/output devices at the same time for one input/output channel, or (2) install the required amount of memory. Possible methods include providing enough registers in parallel to specify the accessible areas above.

However, the former method is expected to have the disadvantage that it will not be able to fully utilize the capacity of the input/output channel, resulting in a significant decrease in the processing power of the computer system, and the latter method is expected to have the disadvantage that the required hardware will increase. Ru.

A second embodiment of the present invention is intended to improve the above-mentioned drawbacks, and will be described below with reference to FIGS. 4 to 6.

FIG. 4 is a schematic block diagram showing the positioning of a memory protection device according to a second embodiment of the present invention in a computer system. In this figure, the same reference numerals as in FIG. 1 represent the same or equivalent parts. 105A is a register selection line made up of n signal lines provided on the bus 104, and is inputted from each input/output channel 103 to the memory protection device 106.

Note that n is the minimum value necessary to identify discrete memory areas that are simultaneously designated to specific input/output channels. The value of n must be selected to satisfy the relationship: 2 ^n-1 < m2 ⁿ , where m is the number of discrete memory areas. If the value of n is selected in this way, the memory 102
The identification signal corresponding to the memory area to be used, that is, the binary number m, is sent to the register selection line 1 from the input/output channel 103 that is to be accessed.
05A, the memory protection device 106 selects the accessible area specification register pair based on this information m, and reads the contents, thereby realizing memory protection.

FIG. 5 is a block diagram showing a schematic configuration of a second embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 represent the same or equivalent parts.

Register selection (hereinafter abbreviated as RS) line 105
The register selection signal on A (i.e., the aforementioned memory area identification signal = binary number m) is connected to the buffer 202.
Through A, high speed RAM 204A and 205A
is supplied as a RAM address signal 203A.

In addition, these high-speed RAM204A, 205A
As is clear, it constitutes a memory protection boundary specification register. The RAM 204A stores an upper limit value, and the RAM 205A stores a lower limit value, and these values correspond to the binary number m.
It can be set in advance from the central processing unit 101.

When the input/output channel 103 accesses the memory 102, the RS signal line 10 is output at the same time as the address signal is output onto the interface bus 104.
By configuring the RS signal to be output on 5A (details will be described later), RAM204A,
One content in A is selected and outputted to the comparison circuit 209 as the upper limit value 206 and lower limit value 207 of the memory address.

The upper limit value 206 and lower limit value 207 are compared with a memory address signal 208 on the interface bus 104 by a comparison circuit 209. Then, only when the relationship (206)≦(208)<(207) holds true, the memory access permission signal 107 is output to the memory 102, and the memory 102 becomes accessible.

Therefore, as is clear, if this RS signal (that is, the aforementioned memory area identification signal = binary number m) is made to match the number of the input/output device supported by the input/output channel, the central processing unit 10
1 is configured to set the contents of the RAMs 204A and 205A at the address corresponding to the input/output device immediately before starting an input/output device in the input/output channel.
1 handles data in the order controlled by the input/output channel side without being particularly aware of scheduling, and at that time the input/output channel outputs the number of the input/output device currently being executed to the RS line 105A. You can select the memory accessible area.

FIG. 6 is a block diagram showing details of the second embodiment. In the figure, the same reference numerals as in FIG. 3 represent the same or equivalent parts. Third
As in the case shown in the figure, the bus grant (BG) signal 201 for each input/output channel is sent to the decoder 3.
Decoded at 01. decoded
BG information 311 is latched into latch circuit 302 by bus busy (BBSY) signal 303.

As mentioned above, this BG information 311 is transmitted from the input/output channel to the RS signal line 105A while the bus is in use.
Along with the RS signal output above, the high-speed RAM 204
A, 205A becomes the RAM address signal 203A.

305A is a multiplexer that switches and selects the address signals of the RAMs 204A and 205A, and provides the RAMs 204A and 205A with boundary values (that is, upper and lower limits) of the memory protection area.
The bus busy (BBSY) signal 303 switches between the address 304 output from the central processing unit 101 and the above-mentioned BG information 311 depending on whether the address 309 is set or read. are doing.

204A is a high-speed RAM used as a register for setting the upper limit of the memory accessible area, and 205A is a high-speed RAM for similarly setting the lower limit.

Output 20 of these RAM204A, 205A
6,207 is the interface bus 104 when the input/output channel accesses the memory 102.
It is compared with the memory address signal 208 outputted above in a comparator 307.

Then, the determination circuit 308 determines the result, and when the memory address signal 208 is between the upper limit value 206 and the lower limit value 207, it is determined that the memory 102 is being accessed correctly, and the memory An access permission signal 107 is output.

As can be understood from the above, in the second embodiment of the present invention, when the central processing unit 101 accesses an input/output device, memory protection boundary values (upper limit value and lower limit value) are set in the RAM. In addition, when an input/output channel accesses memory, a register selection (RS) signal - that is, an identification signal of an accessible memory area is output. It is possible to reliably determine whether the input/output channel is accessing the correct memory area.

That is, according to the second embodiment, multiple memory protection areas can be set for one input/output channel, making it ideal for high-performance input/output channels that support multiple input/output devices simultaneously. This has the effect of providing precise memory protection.

(Effects) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Since one or more memory protection areas (or accessible areas) can be designated by the central processing unit for each input/output channel, unified memory management is possible.

(2) As a result of the preceding paragraph, input/output channels are completely prevented from accessing inaccessible areas;
Programs, data, etc. will not be destroyed, and secrets will not be leaked.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the positioning of the memory protection device of the present invention in a computer system, FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a more specific configuration example of the embodiment, and FIG. 4 is a diagram similar to FIG. 1 regarding the second embodiment of the present invention.
FIG. 5 is a block diagram showing a schematic configuration of a second embodiment of the present invention, and FIG. 6 is a block diagram showing a more specific configuration example of the second embodiment. 101... central processing unit, 102... memory system, 103... input/output channel, 104... input/output interface bus, 105... bus exchange control line,
105A...Register selection (RS) line, 106...Memory protection device, 107...Memory access permission signal, 201...Bus use permission (BG) signal, 202
...Latch decoder circuit, 203...RAM address signal, 204, 205...High speed RAM, 206...
RAM output (lower limit value), 207...RAM output (upper limit value), 208...memory address signal, 209...comparison circuit, 301...decoder, 302...latch circuit, 303...bus in use (BBSY) signal, 304
...RAM address signal, 305...address multiplexer, 306...data buffer, 307...comparator, 308...judgment circuit, 309...memory protection boundary value.

Claims (1)

[Claims] 1. A central processing unit, a memory, a plurality of input/output channels that can directly access the memory, an input/output interface bus that exchanges information between these, and the central processing unit and each input/output channel. A memory protection device for a computer system consisting of a bus exchange control line that controls bus usage rights between A pair of memory values and lower limit values.
RAM and a bus use permission signal on the bus exchange control line is input to read the accessible memory area corresponding to the selected input/output channel.
a decoder that outputs a RAM address signal;
means for latching a RAM address signal by a bus busy signal output from the selected input/output channel; , comprising means for comparing with a memory address signal on the bus, and a determination circuit that outputs a memory access permission signal when the memory address signal on the bus is between an upper limit value and a lower limit value of the memory area. A memory protection device characterized by: 2. The memory protection according to claim 1, further comprising means for writing into the pair of RAMs an upper limit value and a lower limit value of the accessible area corresponding to each of the input/output channels. Device. 3. A memory protection device for a computer system comprising a central processing unit, a memory, at least one input/output channel capable of accessing a plurality of discrete areas of the memory, and an input/output interface bus for exchanging information between them. The boundary values of multiple memory areas that can be accessed from each input/output channel - that is, a pair of RAMs that store the upper and lower limit values of memory addresses, and the accessible area that is output from the input/output channel that has the right to use the bus. means for receiving a memory area identification signal and correspondingly outputting a RAM address signal for reading a predetermined accessible memory area; and means for transmitting the RAM address signal to the selected input/output channel. means for latching by a bus busy signal outputted from the bus; and means for comparing a boundary value of the memory area read from the pair of RAMs with a memory address signal on the bus according to the RAM address signal. and a determination circuit that outputs a memory access permission signal when the memory address signal on the bus is between an upper limit value and a lower limit value of the memory area. 4. The memory according to claim 3, further comprising means for writing an upper limit value and a lower limit value of the accessible area corresponding to each input/output channel into the pair of RAMs. Protective device.