JPS59189474A - High speed foulier transformation operating device - Google Patents

Abstract

PURPOSE:To shorten time required for operation by providing two high speed access memories of minimum capacity and controlling input/output memory access of large capacity memory ingeniously. CONSTITUTION:Data of one point each is taken out from small blocks made by quartering each block and written in a high speed access memory HSM1. Next four complex number data are written in a memory HSM2 from a large capacity memory MS, and at the same time, high speed Foulier transformation operation (FFT) is made on the memory HSM1, and the result is written in HSM1. Then, FFT operation is made on the memory HSM2 and the result is written in the memory HSM2. At the same time, four complex number data of the memory HSM1 are written in the memory MS. Then, next data are written in the memory HSM1 from the memory MS. FFT operation is made on the memory HGM1 and the result is written in the memory HSM1. At the same time, data of the memory HSM2 are written in the memory MS, and then next data are read from the memory MS.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FFT arithmetic device that performs fast Fourier transform (hereinafter abbreviated as FFT).
f - (Array processor hereinafter A
(abbreviated as P), there is normally a time delay for data memory access and an increased time delay for the completion of addition, subtraction, and squaring.

Calculation input (or output) - data storage memo IJ 75
- There is a delay in reading or writing data from i! In an FFT operation that requires continuous reading or writing of a large amount of data, the calculation (processing) capability is limited by fIIj by the data exchange with the memory.

For example, two points of complex data (Complete
The time required to read and write xData) is
Each point is represented by two data, the real part and the imaginary part, so read it out! A total of 8 cycles, 4 cycles for writing, are required. In this case, even if the start of 4 multiplications and the start of 6 additions can be executed in 6 cycles by parallel processing of multiplication and Caro arithmetic, the number of memory accesses of 8 cycles determines the speed of the FFT operation. In other words, there is a problem in that the FFT calculation speed is limited by the number of memory accesses.

In view of these points, the present invention aims to provide, in addition to a low-speed, large-capacity memory for storing FFT input/output data, two minimum-capacity, high-speed access memories;
It is an object of the present invention to provide an FFT device that can shorten the time required for calculation by skillfully controlling input and output memory addresses of a large-capacity memory.

The present invention will be described in detail below using the drawings. First, the algorithm of the method of the present invention will be explained. Figure 1 is a diagram showing the signal flow of the method of the present invention, where the number of data is 1.
6. DIT method, 1n-place method.

The calculation method and data flow in an example of normal input order are shown in Figure 2, where the number of data in a block is 2.

The details of the signal flow in an example of the DIT method + In place method and normal input order are shown.

The basics of the FFT algorithm in the method of the present invention are as follows. This FFT is Ba5e2F
FT, :I 7plex data number N, 1
This is the case of n-place method, input data forward order, and DIT method, and the calculation procedure is N = 22Y and N = 22Y"
The case of 1- is shown separately as follows.

(() For N=22Y (1) N = 22Y, ND = N/2.t
= 1.

(2) Let K=O, M=O.

(3) For k=, k+1. k+2. ,,,,
, , The following calculation is performed for k+ND-1.

A=C, -□(k)-! −C, −□(k+ND)・W(
M) (1-1)c=cview-1(k)-C,
, (k+ND)・w(+lI) (1-2)
B=C(k+-ND)+C,-1(k+TND)・W(
M) (2J)z-12 D = C,, (k+ T ND)-C,1(k+ T
Year (M) (2-2)c, (k) = A+B-W
(2M) (3-:L)C, (k+
TND) = A-B-W(2M) (
3-2) Cy, (k”ND) = C+D-W(2M”
2) (4-1)c (k+-ND
) = c-D-w(2M+2)
(4-2) 2 P=Bit Reverse(i)Ij2=-1(4
) M=M+2, K=+2・immediately, and if K(N), return to (3).

(5) ND=ND/4. Let t = t + 1, and if t≦γ, return to (2).

(6) For k=o, 1,..., N-1 (output data array normalization) q = Bit ReverseJ k ) and q)k
Then CL(k) = G (b) If N=22Y+1 (1) N; 22Y+II=N/2. Let t = 1.

(2) K=O, M=O.

(3) k=to, to+4. +2. --------,
The following calculation is performed for k+IfD-4.

A-CL-1(k)+C1-1(k+ND)・W(M)
c=cmen-1(k)-CL-1(k Shibetsu・W(M)B
= C(k+ND/2)+CCL1(k+TND)°W
(+11) Immunity-1 D=C(k+ND/2)-CL-1(k+TND)・W
(cup 9, -1 C(k) = A+B-W(2M) C(k+ND/2) = h-B-W(2M) Cross C(k+ND) = C+D-W(2M+2) Look C(k+-' -ND) =C-D-W(2M+2)
2 P=Bit Reverse i), j2=J(
4) M=M+2, K +2, Rabbit, K<N
Then return to (6).

(5) ND=ND/4, t := t 10i, and if t≦γ, return to (2).

(6) k=o, 1, 2.・The following calculation is performed for T-1.

CL(2k)-CL(2k)+CL(2+4)・W(
210(5-1)C(2+1)=C(2k)-C(2
+1)・W(2k) (5-2)L
(a) Data array normalization for k-0, 1, 2, ..., N-1) q = Bit Reverse (k I and q>k
C, (q)=C, (k) Ci(k)=C Also, in the method of the present invention, each block is divided into four small blocks, and one point of data is extracted from each small block, and these four points of data are It is configured to perform processing for two loops of normal Fn at one time, and to reduce the number of large-capacity memory accesses by half.

5 and 4 are diagrams showing the relationship between loops, blocks, and small blocks. This figure shows a case where data consisting of is continuous.

FFT to implement the algorithm described above
An embodiment of the apparatus is shown in FIG. In Figure 5, RF
I and RF2 are register files consisting of a plurality of registers, and store read addresses and write addresses of the large capacity memory MS. Both RIi and RI2 are registers that provide changes in the read address and changes in the storage address. 5ELL and 5EL2 are selectors that select either input a□ or a2, and ADI, AD
2 is an adder that adds addresses. RF in 0AD1
The 100 outputs of I and 5ELI are added and the result is given to the address register MA of the MS via the selector 5EL3.

The output of ADl is fed back to the corresponding register of RIi and becomes the next address data. RF2 in AD2
and the 100 outputs of 5EL2 are added, and the result is given to MA via 5EL3. The output of AD2 is stored in the corresponding register of RF2 and becomes the next address data.

H8MI, I (8H2 is a high-speed small capacity memory),
Storage of IS read data and storage of intermediate results of FFT calculations.

It is used as a storage memory for FFT calculation results.

H8M1.2 is capable of simultaneous data read/write operations with minimum cycle time (read address and write address do not necessarily match).

The TBM is a data memory (RAM is used) that stores constants (such as W) for FFT calculations.

ADD is an adder that performs addition of Al and A2 by two people, and outputs the result to H8MI, H81i12. It can be given to each A2 input of ADD. For ADD A1 manpower, H
88ri1. I (8H2, one of the MUL outputs is selected. ADD A2 manual power is H3MIL, H8
M2. One of the outputs of ADD itself is selected. M
UL is a multiplier that multiplies Ml and H2 by two people, and outputs the results to H8MI, H8M2. It can be given to each A1 input of ADD. MUL (D Ml input has TB
The output of M is given.

For MUL's M22 manual power, one of the outputs of H3MI and H8λ12 is selected.

The IF is an interface unit with external devices (CPU, data collection device, etc.).

Data, address information, control signals, etc. are exchanged. Data transfer with the outside is performed between the MS and the external device.

csld, FFT It is a non-memory that stores the micro program for calculation. CTL is in the micro program, but ADD, MUL, 1 (SMI/H8M2 read and write operations, TBM read operations, etc. are performed in parallel. It can work.

The operation of the present invention in such a configuration will be described next.

(1) Preparation for each loop process The input data of FFT is stored in MSK.

RF],, RF2 is a register 7 aisle consisting of 8 registers each, and the initial value rtpl(j) of each register is
.

Set RF2(j) (j=o, 1., .7) as follows (RFI is for reading, RF2 is for writing).

RBA: A from the first address of real number data; Imaginary number data ND Half of the number of data in the block and the initial values of RII and RI2 are set as follows (an example when real number data and imaginary number data are separated).

From R = 1 (9-1,)R1
2=2-N'D+1 (92)W(
λ1)=W(0) and 1 (10)(2)H
3M to 1 (RBA, IBA); (RBA +T,
Write 4 complex number data corresponding to IBA +-T-) (MS-+H8MI').

(5) Write the next 4 complex number data from MS to H8M2 (MS-+H8M2).

At the same time, perform FFT operation on H8M'i (H8MI→H
3MIH algorithm (a) (3)).

(4) Process the following operations in parallel.

(1) ■ (4 complex data of SM1
If it is the first data of the block, it should be stored in the RF2(j)+RII female.If it is other than the first data of the block, it should be stored in the atl female of RF2(j)
If it is the first data of the block, RFI(j) + RI2 If it is other than the first data of the block, RFI(,j) 10R engineering 1 (7) 4 Read complex data into IISMI (1iis −+ H3MI).

(ii) I (8M2t7) 4 complex
Perform FFT operation on data (H8M2→H3M2;
Section (3) of algorithm (a)).

(5) Process the following operations in parallel.

(i) When the 4 complex data of nsh+2 is the first data of the block, store it at the address of RF2(j), and when it is other than the first data of the block, store it at the address of RF2(j)+RII (H5M2→MS), then If it is the first day or evening, RFI (j) 10RI 2 Otherwise, RFI (j) + R engineering 1 4 Read complex data into H8M2 0
．． (S-+H3M2).

(ii) H8Mi8M mino complex data
K Perform FFT operation (H8M1→I(SMli
Section (3) of algorithm (a)).

(6) The above (4) until the end of all FFT calculations for one block.
.

Repeat (5) 9 times, and after completing this calculation process, M = M+
2, and if processing of all blocks in this loop is not completed, the operation returns to step (5) again.

(7) Store the 4 Complex data of HsM2 in the MS.

After completing the processing of 1 loose, set ND = ND / 4, and if the processing of all loops is not completed, return to (1).

The above (1) to (7) are examples of algorithms for realizing high-speed FFT operations exceeding the memory access limit using the apparatus shown in FIG.

Control of the number of data processing times (n times per block), control of the number of loops, etc. are controlled by the C8 micro program.F), C
Do it on TL.

Register files RFI and RF2 have 4 points and 8 data Read Address or Write A
ddress is stored, and after reference, the contents of the register are updated to the next reference address. RI2 is used when calculating the address of the first data of the block (Read
Add, /Write Add, ), RIi are controlled to be used when calculating other data addresses.

Note that the present invention is not limited to the above-described embodiments, but can also be expanded and modified as listed below.

(1) 1 block divided into 8 (16, 32,..., division)
Then, 3 loops (4, 5,..., loop) batch processing A.
(2) Unification or separation of lines and buses for control signals, data, addresses, etc., and different connections, combinations, and connections between devices.

(3) Use of multiple adders (addition/subtraction units) (Butt
(4) Sharing and substitution of devices (1) Sharing of Apl and AD2 (5EL3 becomes unnecessary) (it) TBM to H5MI or H3N
2 and shared 0ii) When using CTL instead without cs (
5) Combining and merging devices (i) (SEL3.) Include MA in MS ((S
EL3. ) Case where MA is apparently bad) (ii) Including SELL in ADD (mountain) Including 5EL2 in AD2 6v) Combining RII and RI2 (SEL, 5E)
(L2 unnecessary) Combination of M RFI and RF2 (6) If you have two each of RII and RI2, R engineering'l,
When using RI2 as ROM (multiple ROMs)・RII, RI
In the case where there is a plurality of registers 2 and TBM is a ROM, the number of registers of RFI and RF2 is not limited to eight.As explained above, the present invention provides the following effects.

(1) High-speed F that exceeds memory access limits
FT calculation can be realized.

(2) Concise and highly applicable Ba5e2. FFT can be realized.

(3) Do not use Butterfly calculation units, etc.
A cheap and economical device can be created.

(4) The device can be made into a device that does not lose its characteristics as a general-purpose array processor.

[Brief explanation of drawings]

1 and 2 are diagrams showing the signal flow of the present invention, Figures 3 and 4 are diagrams showing the relationship between loops, blocks, and small blocks, and Figure 5 is an illustration of the FFT calculation device of the present invention. FIG. 2 is a main part configuration diagram showing an example. RFI, RF2... register file, RII,
RI2...Register, 5ELI, 5EL2.5E
L3...Selector, ADl. AD2...Adder, MA...Address register, λIS...Large capacity memo IJ, H3MI, H3N
2...High speed small capacity memory, TBM...Data memory, ADD...Adder, MTJL...Xi, xF
···interface. i=0.1,2. , B+ IL-1″7゛0′ Convex 0 Tail 4 figure

Claims (2)

[Claims] (1) Memory access is achieved by dividing the input data block, further dividing each block into small block groups, and performing FFT operations for multiple loops between the data groups extracted from the small block groups. 9. An FFT arithmetic device using an FFT arithmetic method, which is characterized by reducing the number of times, reducing delays in memory access, and enabling high-speed arithmetic operations. (2) Using double-A high-speed access memory as a buffer, the high-speed memory for this data group is controlled while controlling the input data address group and output data address group of small blocks in the low-speed large-capacity memory. A patent claim characterized in that the FFT calculation of the plural loops used and the readout operation of the next data group from the low-speed memory to the high-speed memory after storing the previous FFT calculation result in the low-speed memory are performed in parallel. The FFT calculation device according to item 1.