JPS59188143A - Multilayer interconnection member and method of manufacturing the same - Google Patents

Abstract

PURPOSE:To improve the mask accuracy for forming a plurality of connecting holes for connecting between different wirings and to improve the reliability and the integration of multilayer interconnection members by providing a dummy pedestal. CONSTITUTION:An insulating film 2 made of dioxidized silicon is formed on a semiconductor substrate 1, and a dummy pedestal 4 having no function as the wirings 3 of the first layer and as the wirings are formed. An insulating film 5 is formed, and the wirings 6 of the second layer is formed. An insulating film 7 is formed, a mask material 8 is patterned, and a mask having a hole 9 is formed. The primary base of the projection grown by multilamination is alleviated by a dummy pedestal 4, and the mask accuracy in the formed portion of the connecting hole can be improved. Connecting holes 10, 11 are formed and wirings 12, 13 of the third layer connected to the wirings 6 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to multilayer wiring technology, and in particular, to a technology that is effective when applied to a semiconductor device having a multilayer wiring structure.

[Ha Tsuki Branch Jutsu]

It is known that due to the improvement of 4+ product variation, semiconductor devices adopt a multilayer wiring structure in order to reduce the area required for wiring between semiconductor elements and between semiconductor elements and external terminals. There is. In a multilayer wiring structure, insulating films and wiring are alternately formed in multiple layers on a semiconductor substrate that constitutes a semiconductor device, and the connection between wiring arranged in different layers is a factor that affects the reliability of the semiconductor device. There are many people. Between the wirings, a contact hole (also called a through hole) is formed by removing the insulating film at the connecting part using a photoresist mask placed above the connecting part of the insulating film formed between the wirings.
is formed, and the connection is made through the connection hole.

In such a semiconductor device with a multilayer wiring structure, as the degree of multilayering increases, the degree of undulation of the top layer also increases, and it is difficult to form the photoresist for forming a mask on such a base with many undulations. As a result, a problem has arisen in that the thickness of the film differs significantly from part to part.

The photoresist film is very much an N1 film, and the underlying layer on which it is formed may have undulations, so it has traditionally been formed by making a fluid photoresist into a thin film and removing its fluidity. are doing. As a result, the upper surface of the photoresist film is flattened by a slope l, which causes the above-mentioned problem.

Due to the problem of a semiconductor device having such a multilayer wiring structure, when forming all the masks for forming contact holes by patterning the photoresist film, each contact hole forming part is formed in the same manufacturing process. Photoresist film strength [1 lower thread condition, if falling, light exposure amount, development conditions, etc. will be different. This fc causes a difference in the dimensions of each connection hole, which tends to cause misalignment of the pattern between the wiring and the connection hole, and a sharp, frebus-like difference, which can shorten the migration life and cause wire breakage. was. Therefore, the reliability of a semiconductor device with a multilayer wiring structure is reduced, and there are many drawbacks in that the degree of integration cannot be improved.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned defects in a multilayer wiring member, make the size of connection holes uniform in the same manufacturing process for connecting different wirings, and improve reliability. It is an object of the present invention to provide a multilayer wiring member that is optimal for integration and a method for manufacturing the same.

Another object of the present invention, similar to the above object, is to provide a semiconductor device that can improve reliability and has a multilayer wiring structure that is optimal for high integration.

In addition, the above-mentioned and other objects and novel 'P's of the present invention
r, % will become apparent from the description herein and the accompanying drawings.

[Summary of the invention]

Outline of typical inventions disclosed in this application are as follows.

That is, in a multilayer wiring member, the reliability of the multilayer wiring member is improved by improving the accuracy of a mask for forming a plurality of connection holes in the same manufacturing process for connecting different wirings, and by forming the connection holes using the mask. The aim is to improve performance and integration.

[Example 1] Hereinafter, the present invention will be described in detail along with one embodiment.

Embodiment 1 will be described using a semiconductor device having a multilayer wiring structure consisting of three layers of wiring.

1A and 2 to 7 are cross-sectional views of main parts of a semiconductor device having a multilayer wiring structure in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention, ) in FIG. 1 is a top view of FIG. 1(A), and FIG. 1(A) is a sectional view taken along the line X--X of FIG. 1(B).

In all the figures, parts having the same function are given the same details, and repeated explanations are omitted.

First, a semiconductor substrate 1 made of, for example, silicon single crystal is prepared for forming the cow feeding device #7.

This semiconductor substrate 1 has a memory function on its surface.
Semiconductor elements and the like for constructing a 4:9 function are being formed. Next, in order to electrically isolate semiconductor elements (not shown), etc., an insulating film 2 made of silicon dioxide (sioz), for example, is formed over the entire surface of the semiconductor substrate 1.
? ]l-form. After this, Figure 1 (Shu.

As shown in (B), the first layer wiring 3 for connecting between the V1 semiconductor elements (not shown in the figure) intersects with a predetermined first region on the top of the substrate 1. form.

In the upper part of the first region of the wiring 3, a second layer wiring and a third layer wiring are formed with an insulating film interposed therebetween in a later manufacturing process, and in order to make all the connections between the wirings. A connection hole (also referred to as a through hole) is formed in the insulating film. Simultaneously with the formation of the wiring 3, a connection hole for connecting the first wiring is formed in the insulating film between the second layer wiring and the third layer wiring in a later manufacturing process. However, a dummy pedestal 4 having no function as a wiring according to an embodiment of the present invention is formed in a second region where the first layer wiring is not present in the connection hole -1.

This dummy pedestal 4 is provided to equalize the height of the upper surface of the contact hole formed in the upper part of the first region and the upper surface of the contact hole connected to the upper part of the second region in the semiconductor substrate 1. The shape of the dummy pedestal 4 may be determined by taking into account the shape of the connection hole formed in the upper part of the dummy pedestal 4, the misalignment of masks in the manufacturing process between the dummy pedestal 4 and the connection hole formed in the upper part, and the like. Note that the wiring 3
The dummy pedestal 4 may be made of aluminum (AZ)V made using sputter lid technology, for example.

After the steps shown in FIGS. 1(A) and (J3), as shown in FIG. An insulating film 5 for isolation is formed. This insulating film 5 can be formed using, for example, a chemical vapor deposition technique [hereinafter, OV D (Oh
emica, I Vapor Dep081tiOn
It is sufficient to incorporate silicon dioxide using ``) technology''.

After the process shown in FIG. 2, as shown in FIG.
A second layer wiring 6 is formed on the insulating film 5 so as to extend over the first region of the dummy pedestal 4 and the second region of the dummy pedestal 4 . The wiring 6 may be made of, for example, aluminum laminated using a thin film or double evaporation technique.

After the process shown in FIG. 3, as shown in FIG.
Then, an insulating film 7 is formed for electrical isolation from the third layer wiring formed in a later manufacturing process. This insulating film 7 may be made of silicon dioxide produced by OVD technology, for example.

As shown in FIG. 4, after the TI process, as shown in FIG. An insulating film 7 is formed on the entire surface of the soil. For this mask material 8, a resist is used. The photoresist film initially has fluidity,
Due to the fluidity and the rotational force applied to the semiconductor substrate 1, the mask material 8 is thinned and the upper surface of the mask material 8 is flattened. Therefore, among the bases with undulations at the bottom of the mask material 8, a thin mask material 8 is formed at the base located at the highest level from the semiconductor substrate 1, and a thick mask material 8 is formed at the base at the lowest position from the semiconductor substrate @1. It has become so. That is, the thickness of the mask material 8 for the connection hole formed in the first head region between the wiring 6 and the third r@th wiring formed in the later manufacturing process, and the thickness of the mask material 8 for the connection hole formed in the first head area between the wiring 6 and the third r@th wiring formed in the later manufacturing process. The thickness of the mask material 8 for the connection hole formed in the second region is equal to that of the third layer wiring. This can be achieved by forming the dummy pedestal 4 according to an embodiment of the invention in the second region where the upper surface of the undulations will be lower than the upper surface of the undulations of the first mound due to multilayering. It is something.

After the step shown in FIG. 5, as shown in FIG. 6, a connection hole is formed to connect the wiring 6 in the upper part of the first area and the second area to the wiring in the third layer formed by the bale manufacturing process. For this purpose, the mask material 8 is patterned to completely form a mask having openings 9.

The dimensional accuracy of the connection hole depends on the dimensional accuracy of the opening 9. In conventional multilayer wiring technology, masks are required for the areas where connection holes are formed because they are the base for the undulating areas that grow as a result of multilayering. ? Lee had no choice but to give up the fourth grade. However, according to this embodiment,
The dummy pedestal 4 relaxes the base of the undulating portion that grows due to multilayering, and the mask accuracy in the portion where the connection hole is formed can be improved. That is, mask material 8
In this case, the pattern linking conditions in the first area and the second area are equal.

After the step shown in FIG. 226, the insulating film 7 is etched using the mask, and a connection is made in the first Wj region for direct connection between the wiring 6 and the third layer wiring formed in a later manufacturing process. - Let go of Jllo, 26th e; area 61 men 6
A connection for connecting with the third layer wiring which will be formed in the later manufacturing process! :F1.11 complete form. After this, mask discrimination 8 is removed 1. Then, as shown in FIG. 7, a third layer of wiring 12 is formed to connect to the wiring 6 through the connection hole 10, and the wiring 6v is connected to the wiring 6 through the connector 1.11.
A third layer wiring 13 is formed to connect this. This arrangement 12, 13 may be made of aluminum, for example by Nupatta deposition technique.

Through a series of steps, the semiconductor device of this 1m example is completed. In addition, after this, is there any treatment such as a protective film? ]7#
You may.

FIGS. 8 and 9 are top views of essential parts of a semiconductor device having a multilayer wiring structure in one manufacturing process for explaining the practical aspects of the present invention.

8 and 9, after forming an insulating film 2 on a semiconductor substrate 1 through a predetermined manufacturing process,
A dummy pedestal 4 is extended from one side end of the wiring layer 3 to form a shape 5y. The IOA is a connection hole forming portion in a first region formed in an insulating film between the first line in the second layer and the wiring in the third layer, which will be formed in a later manufacturing process. IIA
is a connection hole forming portion in a second region formed in an insulating film between a second layer wiring and a third layer wiring formed in a later manufacturing process. Although the dummy pedestal 4 shown in FIGS. 8 and 9 is integrated with the wiring 3, it does not function as a wiring, and improves the dimensional accuracy of the connection hole that will be formed above them. It is for the purpose of

[Efficacy]

According to the present invention, in a semiconductor device having a multilayer wiring structure in which a plurality of insulating films and wirings are alternately formed on a half-dead I-body substrate, fC3 provided on the semiconductor substrate is provided. A first wiring arranged in a predetermined wiring layer of a predetermined wiring layer of a first region W having a predetermined number of layers or nine or more wiring layers, and two wirings arranged under the predetermined wiring layer. The height from the semiconductor substrate of the top surface of the insulating film provided between
A third wiring which is provided on a semiconductor substrate different from the first area and which is in the same wiring layer as the first wiring in a second area which does not fill the predetermined wiring layer, and a fourth wiring arranged below the third wiring. A tummy pedestal is provided such that the height of the upper surface of the insulating film provided between the semiconductor substrate and the height of the upper surface of the insulating film in the first region 10 is equal to the height of the upper surface of the insulating film in the first region 10 on the wiring layer at the bottom of the second region 10. can be provided.

Due to the stiffness, the heights of the upper surfaces of the insulating films on the first area and the second area are made equal, and the heights of the first and second wirings to be provided on the respective insulating films are The thickness of the mask for forming the connection hole for connection between the third wiring and the fourth wiring can be reduced, and the mask precision in that part can be improved. Therefore, in order to improve the dimensional accuracy of each contact hole, the multilayer wiring structure (in addition, the reliability of the semiconductor device can be improved,
Its degree of integration can also be improved.

The above inventions made by the inventor have been put into practice. Although the present invention has been specifically explained based on the above embodiments, the present invention is not limited to the above-mentioned embodiments.
Needless to say, various changes can be made.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the multilayer wiring technology of semi-through fittings, which is the background field of application, and was explained in terms of fc cases. For example, it can be applied to multilayer wiring technology in wiring boards.

[Brief explanation of the drawing]

FIG. 1 (8) and FIGS. 2 to 7 each illustrate a yarn spinning method according to an example of the present invention. ! A sectional view of the main parts of a semiconductor device with a multilayer wiring structure in the IT manufacturing process, Figure 1C
B) shows the main part of a semiconductor device having a multilayer wiring structure in one manufacturing process for explaining another embodiment of the present invention. It is a top view. In the figure, 1... semiconductor substrate, 2, 5. 7... insulating film, 3
．． 6.12.13... Wiring, 4... Dummy pedestal, 8... Mask material, 9... Opening, io, 1i
... Connection Ut hole, 1. OA, IIA... connection hole forming parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] 1. In a multilayer wiring system in which a plurality of insulating films and wiring layers are alternately formed on a substrate, a first @ having three layers or a predetermined number of wiring layers on the force field on the substrate; the height from the substrate of the upper surface of the insulating film provided between the first wiring arranged in the predetermined wiring layer in the region and the second wiring arranged in the layer below the first wiring; A third wiring placed on the same wiring layer as the first wiring in a second area that does not have a predetermined wiring layer coverage L5 on a different substrate, and a fourth wiring placed on the lower layer thereof.
A multilayer comprising at least one dummy pedestal in one of the wiring layers on the second region so that the height from the substrate of the upper surface of the insulating film provided between the wiring and the wiring is equal to each other. Wiring member 1. 2. A multilayer wiring member, wherein the multilayer wiring system according to claim 1 is a semiconductor device. 3. Form a first wiring on a substrate in a first area, and connect it to the first wiring on a substrate in a second area different from the first area, and install a dummy pedestal so as to straddle and separate it. a step of forming a first insulating film on the entire surface; a step of forming a second wiring by printing the first insulating film on the first and second mounds; and a step of forming a second wiring on the entire surface. A process of forming a second insulating film, a connection hole for an IC that connects a second wiring above the first region and a third wiring formed in a later manufacturing process, and
forming a mask on the second insulating film for forming a connection hole for connecting the second wiring on the upper part of the second button trough and the third wiring formed in a later manufacturing process; forming a first connection hole in the second insulating film above the first region using the mask; forming a second connection hole in the second insulating film above the second region; A third wiring is formed to connect to the second wiring through the second connection hole, and the third wiring is connected to the second wiring through the second connection hole.
A method for manufacturing a multilayer wiring member, comprising the step of forming a third wiring to be connected to the wiring.