JPS59183034U - DA converter offset removal circuit - Google Patents

DA converter offset removal circuit

Info

Publication number
JPS59183034U
JPS59183034U JP7732083U JP7732083U JPS59183034U JP S59183034 U JPS59183034 U JP S59183034U JP 7732083 U JP7732083 U JP 7732083U JP 7732083 U JP7732083 U JP 7732083U JP S59183034 U JPS59183034 U JP S59183034U
Authority
JP
Japan
Prior art keywords
converter
output
sample hold
subtracter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7732083U
Other languages
Japanese (ja)
Other versions
JPH0138997Y2 (en
Inventor
萩田　宏之
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP7732083U priority Critical patent/JPS59183034U/en
Publication of JPS59183034U publication Critical patent/JPS59183034U/en
Application granted granted Critical
Publication of JPH0138997Y2 publication Critical patent/JPH0138997Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＤＡコンバータにおけるオフセット除去
回路を示す回路図、第２図は本考案の＝実施例を示す回
路図である。 ３・・・・・・ＤＡコンバータ、６・・・・・、・減算
器、７・・・・・・ゼロデータ検出回路、８・・・・・
・サンプルホールド回路、９・・・・・・タイミング回
路、１０・・・・・・ローパスフィルタ。FIG. 1 is a circuit diagram showing an offset removal circuit in a conventional DA converter, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 3...DA converter, 6..., subtracter, 7...zero data detection circuit, 8...
- Sample hold circuit, 9... timing circuit, 10... low pass filter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＤＡコンバータの出力に発生する直流オフセットを除去
する回路であって、ＤＡコンバータに入力されるディジ
タル入力がゼロまたはゼロに近い値であることを検出す
るデータ検出回路と、該入力に対するＤＡコンバータに
よる変換出力を抽出して保持するサンプルホールド回路
と、該サンプルホールド回路の出力をＤＡコンバータ出
力から減じる減算器と、該サンプルホールド回路と該減
算器との間に設けられてサンプルホールド出力の変化時
の高調波の発生を防止するローパスフィルタとからなる
ことを特徴とするＤＡコンバータのオフセット除去回路
。A data detection circuit that removes a DC offset generated in the output of a DA converter and detects that a digital input input to the DA converter is zero or a value close to zero, and a conversion by the DA converter of the input. A sample hold circuit extracts and holds the output, a subtracter subtracts the output of the sample hold circuit from the DA converter output, and a subtracter is provided between the sample hold circuit and the subtracter to detect when the sample hold output changes. 1. An offset removal circuit for a DA converter, comprising a low-pass filter that prevents the generation of harmonics.
JP7732083U 1983-05-23 1983-05-23 DA converter offset removal circuit Granted JPS59183034U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7732083U JPS59183034U (en) 1983-05-23 1983-05-23 DA converter offset removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7732083U JPS59183034U (en) 1983-05-23 1983-05-23 DA converter offset removal circuit

Publications (2)

Publication Number Publication Date
JPS59183034U true JPS59183034U (en) 1984-12-06
JPH0138997Y2 JPH0138997Y2 (en) 1989-11-21

Family

ID=30207351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7732083U Granted JPS59183034U (en) 1983-05-23 1983-05-23 DA converter offset removal circuit

Country Status (1)

Country Link
JP (1) JPS59183034U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844825A (en) * 1971-10-04 1973-06-27
JPS54136163A (en) * 1978-04-14 1979-10-23 Hitachi Ltd Digital-analog converting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844825A (en) * 1971-10-04 1973-06-27
JPS54136163A (en) * 1978-04-14 1979-10-23 Hitachi Ltd Digital-analog converting device

Also Published As

Publication number Publication date
JPH0138997Y2 (en) 1989-11-21

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