JPS59182703U - Adjustment device abnormality detection device - Google Patents

Adjustment device abnormality detection device

Info

Publication number
JPS59182703U
JPS59182703U JP7746383U JP7746383U JPS59182703U JP S59182703 U JPS59182703 U JP S59182703U JP 7746383 U JP7746383 U JP 7746383U JP 7746383 U JP7746383 U JP 7746383U JP S59182703 U JPS59182703 U JP S59182703U
Authority
JP
Japan
Prior art keywords
host computer
set value
adjustment device
abnormality detection
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7746383U
Other languages
Japanese (ja)
Inventor
三浦 利一
Original Assignee
株式会社日立製作所
株式会社日立コントロ−ルシステムズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所, 株式会社日立コントロ−ルシステムズ filed Critical 株式会社日立製作所
Priority to JP7746383U priority Critical patent/JPS59182703U/en
Publication of JPS59182703U publication Critical patent/JPS59182703U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の調節装置の機能の概略図、第2図は本
考案の上位計算機と調節装置のデータ受は渡しを示す図
、第3図は本−案の異常検出の論理図である。 1・・・プロセス変数、2・・・目標設定値メモリ、3
・・・操作出力値メモリ、4・・・制御情報メモリ。
Fig. 1 is a schematic diagram of the functions of the regulating device of the present invention, Fig. 2 is a diagram showing the transfer of data between the host computer and the regulating device of the present invention, and Fig. 3 is a logic diagram of abnormality detection of the present invention. be. 1... Process variable, 2... Target set value memory, 3
...Manipulation output value memory, 4...Control information memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御変数と制御情報を上位計算機と受は渡すための通信
手段をもち、前記上位計算機から与えられた目標設定値
と制御対象からのプロセス変数を比較し、前記フ恥セス
変数が予め与えられた条件、   を満足するときは、
前記プロセス変数を前起目標設定値に近づけるように操
作出力を行ない、プラントへの設定値制御が可能な調節
装置を用いて、前記上位計算機から目標設定値を与えつ
つ制御を行なう時、制御変数と制御情報の通信により調
節装置側異常を検出することを特徴とする調節装置異常
検出装置。
The host computer has a communication means for passing the control variables and control information to the host computer, and compares the target set value given from the host computer with the process variable from the controlled object, and compares the process variables given in advance to the host computer. When the condition, is satisfied,
When controlling the process variable while giving the target set value from the host computer using a control device capable of controlling the set value to the plant by performing a manipulated output so as to bring the process variable closer to the preset target set value, the control variable An adjustment device abnormality detection device, characterized in that it detects an abnormality on the adjustment device side by communicating control information with the adjustment device.
JP7746383U 1983-05-25 1983-05-25 Adjustment device abnormality detection device Pending JPS59182703U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7746383U JPS59182703U (en) 1983-05-25 1983-05-25 Adjustment device abnormality detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7746383U JPS59182703U (en) 1983-05-25 1983-05-25 Adjustment device abnormality detection device

Publications (1)

Publication Number Publication Date
JPS59182703U true JPS59182703U (en) 1984-12-05

Family

ID=30207490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7746383U Pending JPS59182703U (en) 1983-05-25 1983-05-25 Adjustment device abnormality detection device

Country Status (1)

Country Link
JP (1) JPS59182703U (en)

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