JPS605505U - Upper and lower limit setting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a conventional upper and lower limit setting circuit, FIG. 2 is a circuit diagram showing the configuration of an upper and lower limit setting circuit according to an embodiment of the present invention, and FIGS. 3 and 4 are the above-mentioned circuit diagrams. It is an explanatory diagram of operation of an example. 1... Upper and lower limit setting circuit, 2.3... Upper and lower limit value setter, 4a, 4b... Comparison circuit,
5...Intermediate value calculation circuit.

Claims (1)

[Scope of utility model registration request] An upper limit setter that gives a control upper limit value of a controlled variable, a lower limit setter that gives a lower control limit value, and a control amount that is input as a control target is compared with the above upper limit value and lower limit value, and the deviation amount is sent out respectively. In the upper/lower limit setting circuit which controls the controlled variable within the range of the upper/lower limit values and includes each comparator, when the controlled variable deviates from the range of the upper/lower limit values, the upper limit value or the lower limit value is set to the upper limit value or the lower limit value. An upper and lower limit setting circuit comprising an intermediate value calculation circuit that outputs a command signal so as to obtain an intermediate value.