JPS59182373A - Level display device - Google Patents

Abstract

PURPOSE:To display a signal level at an optional speed through a simple constitution by latching a digital signal at a specific period, and performing on-off control over a display element according to the contents of respective latched bits. CONSTITUTION:A read signal read out of a digital audio recording disk is decoded by a digital signal decoder 1 into a digital signal, which is supplied to a D/A converter 2 to obtain a line output. A digital composite signal, on the other hand, is latched by a latch circuit 3 with the latch timing signal of a timing control circuit 5 which operates by the output of a clock oscillator 4. The latch output of this latch circuit 3 is inputted to a data inverter 7 and a digital signal represented by an absolute value is inputted to a display device 9 through a driver 8. The clock period of the oscillator 4 is varied freely by operating a variable element 6 manually, so this clock frequency is set to a desired value to set the latch period freely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level display device for digitized audio information, and in particular to a digital audio signal level display device suitable for use in a playback device that plays back digitized audio information and converts it into an audio signal. It is related to the device.

・ Digitize analog audio signals and convert them into binary ・
There are various methods for converting data into a data signal, but the commonly used methods include the OB (offset binary) method, the 2'c (two's complement) method, and the folded binary method. An example is shown in FIG. In this example, for simplicity, we are converting an analog signal into a digital signal with a total of 3 bits, and in each method, the lower two bits represent the level information of the analog signal, and the MSB (most significant bit) represents the level information of the analog signal. It is designed to represent the polarity of Therefore, with these three bits, the analog signal level can be represented by a digital signal of eight or seven levels. Note that the intermediate level between each stage is rounded up or down by a method such as rounding.

Generally, is a 16-bit digital signal, and M
Since the analog signal level is displayed using 15 bits excluding SB, more accurate A/D (analog/digital) conversion is possible.

Let us consider the case where such digital signals are used to display audio levels. In the OB method, when all 16 bits are 1'', it corresponds to OdB, and when only the MSB is 1'' and all others are 0'', it becomes 1 to dB,
When all 16 bits are "0", it becomes OdB again. In other words, if all 15-bit data other than the MSB is inverted when the MSB is '0' (when the analog signal has negative polarity), the MSB when the MSB is '1' (when the analog signal is positive polarity) The absolute value of the digital signal is obtained by approximately matching the other 15 pit data. Conventionally, the digital signal indicating the absolute value obtained in this way is subjected to level calculation according to the weight of each bit, and the so-called par It generates a display signal to the display.

The same applies to digital signals of other systems.

In this way, in order to display the level using a digital signal, the arithmetic circuit that performs the arithmetic operation for weighting each bit becomes extremely complicated, which is a cause of high cost. In addition, the level display mode is simply a display display with a lighting display of a length corresponding to the analog signal level, and is not different from the display mode of conventional analog audio equipment. . Therefore, a special display format is desired as a level indicator for a so-called digital audio device that handles digital signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital audio signal level display device that has a simple configuration and is extremely suitable for displaying the level of a digital audio device.

The level display device according to the present invention latches a digital signal at a predetermined period, and includes display means constituted by a display element corresponding to the number of latch bits of the latch means, and displays each latched signal of the latch means. The lighting of the corresponding display elements is controlled according to the contents of the bits.

Preferably, when the digital signal is latched to the launch means, the launch period can be controlled as desired.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic block diagram of this embodiment, and the fallen read signal is decoded by the digital signal decoder 1 into digital signals of each method explained in FIG. This decoded signal is input to the 1]/A converter 2, where it is converted into an analog audio signal and output as a line output.

On the other hand, the dinotal decoded signal is latched in the launch circuit 3 to display the level, but the period of this latch timing is controlled by the launch timing signal of the timing control circuit 5 which operates based on the output of the clock oscillator 4. . The clock period of the oscillator 4 is variable element 6
Therefore, by selecting this clock frequency as desired, the latch period can be freely set. Furthermore, the decoder H'ζ
A mask clock signal and a synchronization signal are applied to the timing control circuit 5 to synchronize the latch timing and the digital signal.

The latch output of the latch circuit 3 is input to the data inverter 7, where the lower 15 bits are inverted according to the state of the MSB, and a digital signal indicated by an absolute value is output. The output of this data inverter 7 is input to a driver 8 to drive a display 9. However, turnaround 2
In the case of the decimal system, the inverter 7 is not required.

FIG. 3 is a circuit diagram showing an example of the data inverter 7. It is provided with an exclusion or cabinet 1 that handles digital signals (lower 15 bits) by one person.
is taken into the latch circuit 72 and stored, and this stored output becomes the individual input of the ORDART 71 via the inverter 73. This gate output is written into a shift register 74, and this register output becomes a digital signal indicating an absolute value.

This example is applied to OB type serial data; when MBS is "0", it is at a negative polarity level, so it is necessary to invert all the data in the lower 15 bits. The data is inverted using the power of the other person in the card 1 as °l°'. M
It is clear that equivalent inversion does not occur when SB is 1''.In the case of the 2'c method, the MSB is II II II
Since it is necessary to invert the data of the lower 15 bits when
Inverter 73ij' becomes unnecessary. Incidentally, the data inverter 7 shown in FIG. 3 may be provided before the launch circuit 3 shown in FIG. 2.

FIG. 4 shows another specific example of the data inverter 7, which is applied to 013 type parallel data. Exclusive oak doors 1-1 to '71-15 are provided in which each of the lower 15 bits is powered by one person, and a signal obtained by inverting the MSB by an inverter 73 is commonly applied to each of the doors. The output of each gate may be written to a launch circuit (not shown) and taken out in parallel at the same time.
It may be taken out serially at a certain clock rate. Of course, in the 2'c method, the inverter 73 is omitted.

Incidentally, even if the output of the digital signal decoder 1 is parallel data, it is sufficient to derive it as serial data in the latch circuit 3 and use the data inverter 7 shown in FIG. 3.

FIG. 5 is a diagram illustrating an example of the display 9, in which display elements corresponding to each bit from LSB to MSB, such as LE
It has a configuration in which 16 D (light emitter node diodes) are arranged in a line. The rightmost element corresponds to a weight of 2 and displays -90 dB. The second element from the left end corresponds to a weight of 2, resulting in a -6 dB display. The leftmost element corresponding to the MSB indicates polarity, but it does not need to be provided.

FIG. 6 shows an example of the display of the display shown in FIG. 5, in which elements indicated by diagonal lines are in a lit state. That is, the MSB, the 4th, 7th, 10th, 13th, 14th, and LSB bits counting from the MSB are
1"' and the display elements corresponding to these bits are lit. Therefore, the signal polarity is positive and at least 1"
At first glance, it is surprising that the level is above dB. As mentioned above, if the launch cycle of latch circuit 3 is made faster, the LED
The lighting position changes quickly, and if you change it later, it becomes slower, which not only creates a kind of decorative effect, but also allows you to recognize the level by the deisotal representation of °'l'' and °゛0''. This makes it suitable for digital level display.

However, as shown in Figure 5, by displaying the upper 4 bits excluding the MSB in red, the middle 5 bits in yellow, and the lower 6 bits in green, it is easier to roughly identify the levels. This is the result.

Figure 7 shows a specific circuit example of the block shown in Figure 2, with two channels (left and right audio channels).
This is an example of 16 binotoparallel day data of 013 format. Components having the same functions as those in FIG. 2 are designated by the same reference numerals. In the figure, the output (B) of the oscillator 4 that determines the latch period is a DFF with a two-stage cascade configuration.
(Delay ↑° Furinogfurono 7″) first stage DFF51
The Q output (C) and sub-output (D) of these two FFs 51 and 52 are the data inputs of the NAND key.
It will be a two-man force of 53.

The outputs (E) of each of the gates 54 and 55 are made by one person, and the outputs (G) of each of the gates 56 and 57 are generated by two people.
(H) is supplied by husband and wife.

L/R signal (A
) directly to NAND gate 56, and NAND +' -
57 and 57 are applied via the input parter 58, respectively.
A master clock signal (F) is supplied to each of the darts 56 and 57. and gates 54 and 5
The outputs (J) and (I) of 5 are latch circuits 31L.

It is used as each latch timing signal of 32L, 311%, and 32R. Each CK of previous DFF51.52
The L/R signal (A) is used for the large input.

The dinotal signals of the left and right channels, which consist of 16 binoto signals arranged alternately according to the time series in each sampling time of the left and right channel signals, are sequentially input to the left and right channels in response to the L/R signal (A). Circuit 3L, 3
A parallel input is made to R.

The latch circuits 31L and 32L each latch the upper 8 bits and lower 8 bits of the 7 parallels of the left channel signal. In addition, the latch circuits 31R and 321 (, are the upper 8 binods of the right channel signal input,
The lower 8 bits are each latched.

Each latch output is input to inverting circuits 7L and 7R each consisting of 16 exclude registers, and is inverted according to the state of the MSB of the input node.

The output of each oak becomes a drive signal for the corresponding rows 9L and 9R of display elements (indicated by LEDs).

Figures 8 (A) to (J) are signals (A) of each part of the circuit in Figure 7.
The timing waveforms of (7J) are shown in correspondence with each other. If the relationship between the oscillation output that determines the launch period and the L/R signal is as shown in Figures (A) and (B), then D
, I';' F 5], , 52's Q and Q outputs are (
C) and (D), and Ryokawa's NAND output becomes as shown in (E). That is, in each cycle of the oscillation output (B), a signal (E) is obtained that is at a high level only in one data section of each of the left and right channel signals.

The clock signal from the post-signal unit 1 is as shown in (F'), which has a width equal to the period of the signal A times I, /R, so that Each output is ((
(1-1). As a result, gate 54,
'55 outputs are as shown in (J) and (I), and at the rising edges of these outputs, each parallel data of the right channel and left channel is transferred to each latch circuit 31R5.
32R, 31L, and 32L will be replaced.

Here, the anodes of each LED of the indicators 9L and 9R are biased to the positive terminal\voltage, and the inverter 7 is connected to each cathode.
The outputs L, 7R, and 7R are applied. In order to turn on the LED when the latch output bit is 1, it is necessary to invert and use it as the cathode input of the LED, so in the OB method, as shown in the figure, This means that the contents of the MSB are directly controlled by each exclusive port (without going through an inverter).

In the case of the 2'C method, it is sufficient to insert an inverter into the input or output section of the MSB of the latch circuit.

FIG. 9 shows another specific example of the block shown in FIG.
This is an example of 16-bit serial digital data of a channel and a 2'C system. 2.7. Parts equivalent to those in the figure are designated by the same reference numerals.

The connection relationship between the oscillators 4, D, r")" 51, 52 and the NAND gate 53 is the same as the example shown in FIG.
The output (G) of the gate 53 is the single power of the Nantes gate 59, and the mask clock (A) is applied to the power of the gate 59. , on the other hand, the J, /R, signal (B) is used as the data input of the DFF 61 via inverters 60, 60', and its Q output (C) becomes the single input of the exclusive or cabinet-1-62. The L/R signal (13) is applied to the Sennin power of Ketoro 2, and its output (
D) uNandoke''-163 and 64 are each operated by one person.The DFF 61 is operated by the clock signal (A), and the DI'', Ii''51 and 52 are operated by the L/R signal (B).

There is an L/R signal (B) in the hermit power of gate 63.
Toro 4's Sennin Power has an L/R signal (B) inverter 60.
An inverted signal according to is applied to each. both gates 6
3°64 outputs (E) and (F) are DFF 72L for MSB latch.

72 R, is used as the clock input! The inverted signal from the digital signal input inverter 65 serves as the data input for both DF and I''.These DI'F' 72L
, both Q outputs of 72R (i.e. launch output of MSH)
is an exclusive OR gate 71L for data inversion.
, 71R are each powered by one person, and both cases'-) 71L
, 71R are input to the first stages of shift registers 32L and 32R of data latch circuits 3L and 3R, respectively.

Shift registers 31L, 32L, 31R, and 321 (
are arranged in a cascade configuration, and 8 bits each of the left and right channel data (8 bits and 7 bits if the MSB does not need to be lit) are latched, respectively. The respective outputs (J) and (I) of the two-man powered Nando Ketoro 6.67 are used as this syntonoculus.

The output of gate 59 (
H) is used, and L/R is used for the other person's power at gate 66.
The signal (B) is also triL/1 to the hermit power of gate 67.
The output signals of the % signal (B) from the inverter 60 are respectively applied. And each shift register 3L.

Each bit output of 3R controls the lighting of indicators 9L and 1, which are LED arrays, respectively.

10 and 11 are timing charts showing the operation of the circuit shown in FIG. 9. First, referring to FIG. It is assumed that the output of 4 has the relationship shown in the figure. Therefore, the output (G) of the Nant gate 53 has a waveform of a signal such that one group 70 of left and right channel data is extracted every cycle of the oscillation output of the oscillator 4, as shown in the figure.

FIG. 11 is a timing chart in which time 1 is expanded to make it easier to understand compared to the timing chart in FIG. 10, and FIGS.
The waveforms of (J) are shown in correspondence with each other.

In addition, figure (K) shows shift registers 3L, 311. It shows each bit number.

Each of the outputs of Ketoro 3 and 64 has a signal that is synchronized with the MSB part of the left and right channel data in the period of Ketoro 53 and pulse (G), as shown in (E) and (F). Gurus is obtained. DF F72L, 72R by synchronizing with this MSB Cruz (E), (F)
, are triggered and the MSB of data is latched, respectively. Therefore, data is inverted according to the MSB of each output of the exclusive door 1L and 71H and sent to each shift register 32L and 32R.The shift registers are sent to (J) and (I). As shown, the contents of each bit of the left and right channels are introduced into the corresponding shift register and latched.In this way, it is possible to display lighting according to the contents of each bit.

Incidentally, in the OB method, the inverter 65 that inverts the digital signal may be deleted, but since the inverter 65 has a function as a buffer that reduces fan-out, the outputs from the DFFs 72L and 72R are not deleted. The Q output may also be derived.

In the examples shown in FIGS. 7 and 9, if the oscillation frequency of the oscillator 4 is adjusted by the gamut 6, the launch period can be made variable, making it possible to display a level according to the user's preference.

In addition, in the case of the folded binary system, lighting may be displayed in accordance with the value of each bit except the MSB. Furthermore, OB or 2
In the case of the 'c method, when the signal level is negative, it is displayed as a level that is one step smaller than when it is positive, but this is within the error range for level display and does not pose a practical problem. For more accurate display, the circuit becomes more complicated, but when the signal level is negative, ``1'' is added modulo 2 to the inverted value of each bit except MSI3.

As shown above, according to the present invention, the digital audio signal level can be displayed digitally with a simple configuration, and the display state changes at a speed according to the individual's preference by controlling the latch cycle. It has the advantage that it can also have a decorative effect. In particular, the level display is different from that of an analog audio device, and has the effect of visually appealing to the user that it is a digital audio device. Of course, the present invention is not only applicable to digital audio disc solayers that play discs recorded as digital signals by converting analog audio signals into PCM, but also to A/J) converters.
By adding this, it can also be applied to ordinary analog audio equipment such as a caseno toteso recorder.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining a mode of digitizing an analog signal, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 are specific examples of the data inverter 7 of the block in FIG. 2. 5 is a diagram showing a specific example of the display, FIG. 6 is a diagram showing one display example of the display, FIG. 7 is a circuit diagram of one embodiment of the present invention, and FIG. 8 is a diagram showing a specific example of the display. Circuit operation in Figure 7? The timing chart shown in FIG. 9 is a circuit diagram of another embodiment of the present invention, and FIG.
Is the circuit operation in Figure 9 and Figure 11 the same as in Figure 9? FIG. Explanation of symbols of main parts l...Digital signal decoder 3...Latch circuit 5
...Timer control circuit 7...Data inverter 9...Display applicant
Pioneer Corporation Representative Patent Attorney Motohiko Fujimura (1 other person)

Claims (2)

[Claims] (1) A level display device for audio information converted into a digital signal, comprising a latch means for latching a digital signal at a predetermined period, and a display means constituted by a display element corresponding to the number of latch bits of the latch means. 1. A level display device comprising a level display device, wherein lighting control is performed on each of the corresponding display elements according to the content of each bit latched by the launch means. (2) The level display device according to claim 1, wherein the launch period of the launch means is controllable.