JPS5824864A - Level meter circuit - Google Patents

Abstract

PURPOSE:To eliminate the effect to be exerted on the action of a memory from simultaneous operation of writing and resetting by replacing the past peak memory value with the current value utilizing a reset signal of a peak value memory circuit as a writing signal of the circuit. CONSTITUTION:Input signals from a signal input terminal 1 are latched with a latch circuit 3 by a timing pulse of a timing signal generation circuit 6 through an analog-digital convertion circuit 2 and indicated on a display section 5. A peak value memory circuit 7' memorizes as peak value outputs of the latch circuit 3 by a pulse of an updating pulse generation circuit 9 which outputs pulses receiving outputs of a comparator circuit 8 and the circuit 6 when the outputs of the circuit 3 are larger than the peak value memorized in the circuit 7'. On the other hand, a signals from a peak value reset signal generating means makes the circuit 7' memorize the outputs of the circuit 3 as peak value through a gate 11 whether they are larger than the peak value memorized or not.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level meter circuit, and more particularly to a level meter circuit having a peak value storage function, which can be effectively used as a level meter for, for example, a tape recorder.

In a level meter such as a tape recorder or a cassette recorder, it is required to indicate the peak value of the audio level in order to correctly set the recording level and obtain good recording during recording. For this reason, level meters used in these applications are provided with a configuration that stores and displays the peak value, and a configuration that allows the peak value to be reset at a predetermined timing or at any time desired by the user.

Figure 1 shows a conventional example of this type of level meter circuit, where 1 is a signal input terminal, 2 is an A-D conversion circuit, 3 is a latch circuit, 4 is a display decoder circuit, and 5 is, for example, a T, ED or fluorescent display tube. 6 is a timing j signal generation circuit, 7 is a peak value memory circuit, 8 is a comparison circuit, 9 is an update pulse generation circuit, and 10 is a peak value reset means.

FIG. 2 shows an example of a display on the display section, where L indicates a current value that varies according to the analog input voltage to be measured, and L indicates a peak value stored in the memory circuit 7 of FIG.

In the configuration shown in FIG. 1, the analog input signal to be measured applied to the signal input terminal 1 is converted into a digital signal by the A-D conversion circuit 2, and is launched in the latch circuit 3 according to the timing pulse of the timing signal generation circuit 6. . Latch circuit 3
The output is decoded by the display decoder circuit 4 and displayed on the display section 5.
As shown in FIG. 2, the current value of the length is displayed according to the analog input voltage to be measured.

The peak value Lp of the analog input signal to be measured is stored and displayed in a peak value memory circuit 7, a comparator circuit 8, and an update pulse generation circuit 9. The comparison circuit 8 compares the peak value of the memory circuit 7 with the output of the latch circuit 3, which is the current value, as a digital signal, and the current value (output of the launch circuit 3) is the peak value of the memory circuit 7.
If the current stored peak value is exceeded, a signal to that effect is output. The update pulse generation circuit 9 receives the output of the comparison circuit 8 and the timing pulse of the timing signal generation circuit 6, and applies the timing pulse of the circuit 6 to the write input terminal of the memory circuit 7 when the current value exceeds the memory peak value. I can do it. As a result, the output value of the launch circuit 3, which is the current value of the dog, is written in the memory circuit 7 instead of the previously stored peak value. Therefore, the maximum value, that is, the peak value, of the analog input signal under test is always stored in the memory circuit 7, and when an input signal with a level higher than the stored value is applied, that level value is stored as a new peak value.

The output signal (peak value signal) of the memory circuit 7 is also given to the decoder circuit 4 and displayed on the display unit 5 after being decoded. For the peak value signal, the decoder circuit 4
As shown in FIG. 2, the current value and the peak value Lp are displayed in a distinguishable form.

The above-mentioned memory circuit 7 has a reset function and is reset at any time by receiving a signal from the peak value reset means 10 at the reset input terminal.

As a result of the conventional level meter circuit configured as described above, it has the following drawbacks.

(a) Since the memory circuit has a reset function, the circuit configuration becomes complicated.

(b) When a write pulse and a reset signal to the memory circuit are applied almost simultaneously, there is a possibility that the desired operation cannot be expected.

(C) A state in which no peak value exists in the memory circuit exists until a write signal is applied after the memory circuit has completed the centrifugation.

SUMMARY OF THE INVENTION Accordingly, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its object is to provide a level meter circuit that does not require a reset function in the peak value memory circuit.

A feature of the present invention for achieving this object is that a level meter circuit that converts an input analog signal from analog to digital and displays a level according to the analog signal includes a memory circuit that stores the peak value of the analog signal. , a comparison circuit that compares the peak value of the memory circuit and the current value of the input analog signal; an update pulse generation circuit that provides an output signal when the comparison result is current value ≧ peak value; and a peak value reset signal generation circuit. and a logic gate circuit which receives the output signal of the update pulse generating circuit and the reset signal of the peak value reset signal generating means and provides a write signal to the memory circuit according to any of these signals, The level meter circuit stores the current value of the input analog signal in accordance with the stored peak value in the memory circuit according to the signal.

The present invention will be explained in detail below with reference to the drawings.

FIG. 3 shows an embodiment of the level meter circuit according to the present invention.
Items with the same reference numerals as those in the figures indicate the same items.

In the figure, 7' is a peak value memory circuit that does not have a reset function, and 8 is a peak value memory circuit that does not have a reset function, and 8 compares the peak value of the memory circuit 7' with the output (current value) of the latch circuit 3. 9 is a comparison circuit 8 which outputs a signal indicating that
An update pulse generation circuit receives the output of 1 and the timing pulse of the timing signal generation circuit 6, and outputs the timing pulse of the circuit 6 according to the output of the comparison circuit 8. 10 is a peak value reset signal generation means, and 11 is a logic gate circuit.

The logic gate circuit 11 inputs the output of the update pulse generation means 9 and the reset signal of the reset signal generation means 10, and outputs a write signal to the memory circuit 7' by either of these signals. Consists of.

In the above configuration, the comparator circuit 8 compares the peak value of the memory circuit 7' and the output (current value) of the latch circuit 3, and updates when the current value is equal to or equal to the peak value of the memory circuit 7'. A signal to that effect is given to the pulse generation circuit 9. When the update pulse generation circuit 9 receives this signal, the circuit 9 outputs a timing pulse. This pulse is OR, gate 1
1 as a write signal to the memory circuit 7', the current value at that time (output of the latch circuit 3) is stored as a new peak value in the memory circuit 7', as described above.

On the other hand, when a reset signal is output from the peak value reset signal generating means 10, this signal is similarly applied to the memory circuit 7' via the OR gate 11 as a write signal.

Therefore, regardless of whether the current value at that time (output of the latch circuit 3) is smaller than the stored peak value, the current value is stored as the peak value in the memory circuit 7'.

That is, by storing the current value and erasing the past stored value, an operation equivalent to resetting the peak value of the memory circuit 7' is performed. Moreover, the current value is simultaneously stored as a new peak value instead of the past peak value, so
It is not unreasonable that the peak value no longer exists in memory.

Note that the display of the peak value and the display of the current value are the same as in the conventional example.

As explained above, according to the present invention, the reset signal is used as the write signal of the peak value memory circuit to replace the past peak value with the current value, so the reset function is unnecessary for the memory circuit, and On the other hand, even if write and write operations are performed almost simultaneously, there is no risk of causing a problem in circuit operation.

[Brief explanation of drawings]

FIG. 1 shows a conventional example of a level meter circuit, FIG. 2 shows an example of a display on a display section, and FIG. 3 shows an embodiment of a level meter circuit according to the present invention. 1; Analog signal input terminal 2; A-D conversion circuit 3; Latch circuit 4; Display decoder circuit 5; Display section 6; Timing signal generation circuit 7.7'; Peak value memory circuit 8; Comparison circuit 9; Update pulse Generating circuit 10; Peak value reset signal generating means 11; Logic gate circuit patent applicant. Oki Electric Industry Co., Ltd. Patent Application Agent Patent Attorney Megumi Yamamoto

Claims (1)

[Claims] In a level meter circuit that performs A-D conversion of an input analog signal and displays a level according to the analog signal, there is a memory circuit that stores the peak value of the analog signal, and a memory circuit that stores the peak value of the analog signal and a signal between the peak value of the memory circuit and the input analog signal. a comparison circuit that compares the current value with the current value, an update pulse generation circuit that provides an output signal when the comparison result is the current value ≧ the peak value, a peak value reset signal generation means, and an output signal of the update pulse generation circuit and the peak value. a logic gate circuit that receives a reset signal of a value reset signal generating means and supplies a write signal to the memory circuit depending on any of these signals, and the peak value stored in the memory circuit is generated by the write signal. A level meter circuit characterized in that the current value of the input analog signal is stored instead of the current value of the input analog signal.