JPS59181545A - Wiring method of lead - Google Patents
Wiring method of leadInfo
- Publication number
- JPS59181545A JPS59181545A JP58055704A JP5570483A JPS59181545A JP S59181545 A JPS59181545 A JP S59181545A JP 58055704 A JP58055704 A JP 58055704A JP 5570483 A JP5570483 A JP 5570483A JP S59181545 A JPS59181545 A JP S59181545A
- Authority
- JP
- Japan
- Prior art keywords
- rubber sheet
- thin rubber
- semiconductor element
- lead wires
- conductive ink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、チップ状となった半導体素子とこれとを接続
するリード線の配線方法に関するものである。更に詳し
くは、本発明は例えば放射線検出素子として用いられる
CdTeのような、もろくかつ、割れやすい化合物半導
体素子にリード線を配線する場合等に適用して有効なリ
ード線配線方法に関するものでおる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for wiring chip-shaped semiconductor elements and lead wires that connect them. More specifically, the present invention relates to a lead wire wiring method that is effective when applied to, for example, wiring lead wires to a fragile and easily breakable compound semiconductor element such as CdTe used as a radiation detection element.
従来、半導体素子をステムや基板に取付け、リード線を
配線する方法として、超音波ポンディ7グが利用されて
いる。しかしながら、もろく割れやすい化合物半導体素
子においては、超音波ボンディングの手法を適用すると
、素子の特性を大幅に変更させたり、接続個所に細いク
ラック等が入ったシする欠点があυ、この手法を適用す
ることはできなかった。Conventionally, ultrasonic pounding has been used as a method for attaching semiconductor elements to stems or substrates and wiring lead wires. However, when applying ultrasonic bonding to compound semiconductor devices that are brittle and prone to breakage, there are drawbacks such as significantly changing the characteristics of the device or creating thin cracks at the connection points. I couldn't.
ここにおいて、本発明は、従来技術におけるこのような
欠点のないリード線の配線方法を提供しようとするもの
である。Here, the present invention seeks to provide a lead wire wiring method that does not have such drawbacks in the prior art.
本発明に係る方法は、はじめに薄ゴムシート上に導電性
インクを所定の接続個所に対応して途布し、次に薄ゴム
シート上に僅かな間隙を隔てて配線したい半導体素子及
びリード線を配置させ、その後薄ゴムシートに圧力を加
え薄ゴムシートを半導体素子側に軽く接触させ、薄ゴム
シート上の導電性インクを半導体素子とリード線の所定
の接続個所に転写するようにした点に特徴がある。In the method according to the present invention, conductive ink is first applied to predetermined connection points on a thin rubber sheet, and then semiconductor elements and lead wires to be wired are placed on the thin rubber sheet with a slight gap between them. After that, pressure is applied to the thin rubber sheet to bring it into light contact with the semiconductor element side, and the conductive ink on the thin rubber sheet is transferred to the predetermined connection point between the semiconductor element and the lead wire. It has characteristics.
第1図〜第5図は本発明に係る方法の手順を説明するだ
めの説明図である。1 to 5 are explanatory diagrams for explaining the procedure of the method according to the present invention.
第1図において、(a)は本発明の方法を実現するため
の装置の一例を示す平面図、(b)は(a)図における
b−b断面図である。これらの図において、1は厚さが
例えば0.1〜0.3 mm程度の薄ゴムシート、2は
この薄ゴムシートの周縁部に設置され九〇 IJソング
、これらは基台10とカバー11の間に薄ゴムシート1
の一部がカバー11の開孔12から出るように介挿され
ている。3は空気、玉流入口で、薄ゴムシート1の裏側
に空気圧を導びくようになっている。In FIG. 1, (a) is a plan view showing an example of an apparatus for implementing the method of the present invention, and (b) is a cross-sectional view taken along line bb in FIG. In these figures, 1 is a thin rubber sheet with a thickness of, for example, about 0.1 to 0.3 mm, 2 is an IJ song installed on the peripheral edge of this thin rubber sheet, and these are a base 10 and a cover 11. Thin rubber sheet 1 between
A part of the cover 11 is inserted so as to come out from the opening 12 of the cover 11. Reference numeral 3 denotes an air and ball inlet, which guides air pressure to the back side of the thin rubber sheet 1.
本発明の方法は、このような装置を使用し、まずはじめ
に、薄ゴムシート1上に、例えば銀ペースト等の導電性
インクで、リード線接続パターン6を、例えばシルクス
クリーン印刷等の手法によって塗布する。ここでリード
線接続パターン6は、所定の接続個所位置に対応して形
成される。The method of the present invention uses such an apparatus, and first, a lead wire connection pattern 6 is applied onto a thin rubber sheet 1 using a conductive ink such as silver paste, for example, by a technique such as silk screen printing. do. Here, the lead wire connection pattern 6 is formed corresponding to a predetermined connection location.
次に第2図に示すように、薄ゴムシート1上に僅かな間
隙りを隔てて、この薄ゴムシート1と配線したい半導体
素子4及びリード線41.42. 、、、4nを対向配
置させる。なお、ここでは、半導体素子4iiプリント
板5上に装着され、また、リード線41、42. 、
、 、4nはこのプリント板5上に形成されたものを例
示するが、半導体素子4がプリント板5から分離したも
のでもよい。Next, as shown in FIG. 2, semiconductor elements 4 and lead wires 41, 42, . , , 4n are arranged facing each other. Note that here, the semiconductor element 4ii is mounted on the printed board 5, and the lead wires 41, 42 . ,
, 4n are formed on the printed board 5, but the semiconductor element 4 may be separated from the printed board 5.
次に、空気圧導入口6がら空気圧を送り、薄ゴムシート
1の裏側から内圧を加え、これによって薄ゴムシート1
を第2図に示すように半導体素子4及びリード線41.
42. 、、、4n側に軽く、かつ均一に接触させる。Next, air pressure is sent through the air pressure inlet 6 and internal pressure is applied from the back side of the thin rubber sheet 1.
As shown in FIG. 2, the semiconductor element 4 and lead wires 41.
42. , , , make light and uniform contact with the 4n side.
薄ゴムシート1が半導体素子4側に接触すると、薄ゴム
シート1上に塗布した導電性インクの接続パターン6け
、半導体素子4と各リード線41.42. 、 、 、
4n間の所定の接続個所に転写され、やがて、導電性イ
ンクが乾燥して固形化し、第3図の破線に示すようにリ
ード線の配線が完了する。When the thin rubber sheet 1 comes into contact with the semiconductor element 4 side, six connection patterns of conductive ink applied on the thin rubber sheet 1, the semiconductor element 4 and each lead wire 41, 42, . , , ,
The conductive ink is transferred to a predetermined connection point between 4n and 4n, and the conductive ink dries and solidifies, completing the wiring of the lead wire as shown by the broken line in FIG.
このようなリード線配線方法によれば、半導体素子4に
は、導電性インクの転写時に、薄ゴムシート1に内圧が
加えられて、はじめてこの薄ゴムシートが接触し、この
際の接触も均一で、かつ軽く々されるもので、半導体素
子4を傷付けたp1割っだシすることはない。従って、
化合物半導体素子であっても、その特性変更を与えるこ
となく多数のリード線配線を一度に行なうことができる
。According to such a lead wire wiring method, the thin rubber sheet 1 comes into contact with the semiconductor element 4 only after internal pressure is applied to the thin rubber sheet 1 during transfer of the conductive ink, and the contact at this time is also uniform. Moreover, it is applied lightly and does not damage p1 which may damage the semiconductor element 4. Therefore,
Even in the case of a compound semiconductor element, a large number of lead wires can be wired at the same time without changing its characteristics.
また、薄ゴムシート1は、これが接触する相手の形状に
合せて変形し、密着するものであるから、半導体素子4
側とリード線パターン41.42.45・・・側との間
が正確に同一平面上に配置されなくとも、導電性インク
を所定の接続個所に確実に転写させることができる。Furthermore, since the thin rubber sheet 1 deforms to fit the shape of the object it comes into contact with and comes into close contact with it, the semiconductor element 4
Even if the sides and the lead wire patterns 41, 42, 45, .
なお、上記の説明では薄ゴムシート1がカバー1の開孔
部から出る部分(転写部)の形状が、はぼ矩形のものに
ついて示しだが、この転写部の形状は、配線すべき半導
体素子の接続個所に応じて、例えばリング状等、他の形
状としてもよい。また、上記の説明では半導体素子とリ
ード線との間の配線に適用したものであるが、半導体素
子内における配線に適用してもよい。また、ここでは、
接続個所は導電性インク層によって接続されるようにし
たが、必要に応じてこの部分にワイヤ等を接着し、接続
個所を補強するようにしてもよい。Note that in the above explanation, the shape of the portion (transfer portion) where the thin rubber sheet 1 emerges from the opening of the cover 1 is approximately rectangular. Depending on the connection location, other shapes such as a ring shape may be used. Further, in the above description, the present invention is applied to wiring between a semiconductor element and a lead wire, but it may also be applied to wiring within a semiconductor element. Also, here:
Although the connection points are connected by the conductive ink layer, if necessary, wires or the like may be bonded to these portions to reinforce the connection points.
以上説明したように、本発明によれば、もろく割れやす
い化合物半導体にも適用可能なリード線配線方法が提供
できる。As explained above, according to the present invention, it is possible to provide a lead wire wiring method applicable to compound semiconductors that are brittle and easily breakable.
第1図〜第3図は本発明に係る方法の手順を説明するた
めの説明図である。
1・・・薄ゴムシート、4・・・半導体素子、4j、
42.45・・・リード線、6・・・接続パターン(導
電性インク)。
革1図
(a)
(b)
犀2図
元3図
−2(1 to 3 are explanatory diagrams for explaining the procedure of the method according to the present invention. 1... Thin rubber sheet, 4... Semiconductor element, 4j,
42.45... Lead wire, 6... Connection pattern (conductive ink). Leather Fig. 1 (a) (b) Rhinoceros Fig. 2 Original Fig. 3-2 (
Claims (1)
シート上に導電性インクを所定の接続個所に対応して箪
布し、次に薄ゴムシート上に僅かな間隙を隔てて配線し
たい半導体素子及びリード線を配置し、その後前記薄ゴ
ムシートに圧力を加えて蟲該薄ゴムシートを前記半導体
素子側に接触させ、前記薄ゴムシート上の導電性インク
を前記半導体素子とリード線の所定の接続個所に転写す
るようにしたリード線の配線方法。(1) Prepare a thin rubber sheet, first apply conductive ink on the thin rubber sheet corresponding to the predetermined connection points, and then wire the semiconductor elements on the thin rubber sheet with a small gap between them. and a lead wire, and then pressure is applied to the thin rubber sheet to bring the thin rubber sheet into contact with the semiconductor element side, and the conductive ink on the thin rubber sheet is applied to a predetermined area between the semiconductor element and the lead wire. A wiring method for lead wires that is transferred to the connection location.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58055704A JPS59181545A (en) | 1983-03-31 | 1983-03-31 | Wiring method of lead |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58055704A JPS59181545A (en) | 1983-03-31 | 1983-03-31 | Wiring method of lead |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59181545A true JPS59181545A (en) | 1984-10-16 |
Family
ID=13006270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58055704A Pending JPS59181545A (en) | 1983-03-31 | 1983-03-31 | Wiring method of lead |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59181545A (en) |
-
1983
- 1983-03-31 JP JP58055704A patent/JPS59181545A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4458291A (en) | Package for enclosing semiconductor elements | |
US3729819A (en) | Method and device for fabricating printed wiring or the like | |
JPS5896760A (en) | Manufacture of semiconductor device | |
JP5007099B2 (en) | Power semiconductor module positioning device and power semiconductor module surface treatment method | |
JPS59181545A (en) | Wiring method of lead | |
JPH02133936A (en) | Semiconductor device | |
JPH06168982A (en) | Flip chip packaging structure | |
JPS575356A (en) | Hybrid integrated circuit device | |
JPS63283136A (en) | Method for packaging circuit substrate | |
JP3359824B2 (en) | Method of manufacturing BGA type semiconductor device | |
JPS6461923A (en) | Surface mounting for semiconductor element | |
JPS61244035A (en) | Connection of bump electrodes | |
JPH10116858A (en) | Production of bga type semiconductor device | |
JPS556852A (en) | Semiconductor device | |
JPH0452621B2 (en) | ||
JPH0432762Y2 (en) | ||
JPS58171233A (en) | Manufacture of electrostatic attracting device | |
JPH08306744A (en) | Electronic device | |
JPH11298110A (en) | Method of mounting electronic parts, and its mounting structure | |
JPS5879741A (en) | Connecting method for integrated circuit device | |
JPH02181444A (en) | Mounting method of ic | |
JPS5728344A (en) | Semiconductor device | |
JPH1131762A (en) | Semiconductor device and manufacture of the same | |
JP2006147960A (en) | Semiconductor device manufacturing method and viscous liquid coating method | |
JPS63273393A (en) | Hybrid integrated circuit device |