JPS59181068A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine gate electrode and to reduce a gate resistance by using a metal having excellent heat resistance for a gate electrode. CONSTITUTION:The first, second films 8, 9 are sequentially formed on a semiconductor substrate 1 formed with an active layer 2.The film 9 is partly covered with a mask material 6, etched by an anisotropic dry etching method to form a hole 91 in the film 9. Then, a mask material 6 is removed, and the third film 9 is provided on the entire surface of the film 9 and the hole 91. The film 92 is etched by anisotropic dry etching from the surface to allow the film 92 to remain only on the side of the hole 91 and exposed. Further, the film 8 is removed by etching to expose the substrate 1. Then, a gate metal 30 is covered on the entire surfaces of the substrate 1 and the film 9. Further, after a photoresist 60 is coated on the entire surface, the photoresist 60, the metal 30 and the film 9 are sequentially removed by dry etching. Further, the metal 30, the film 9 are sequentially removed. Moreover, the film 8 is removed by etching to form a gate electrode 3 on the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a gate electrode provided in a Schottky barrier gate field effect transistor (MBSFET).

MBSFETs using gallium arsenide (GaAs) can operate in the microwave band, and can be used in very high frequency band transformers such as circuits (integrated circuits: ICs) integrated on the same substrate, especially high-speed logic ICs. and memory ICs are being actively developed.

In order to obtain such good high frequency characteristics of MBSFET, it is necessary to have a short gate length and low gate resistance, and it is also necessary to have good uniformity of characteristics and excellent productivity. is important.

However, gate resistance is in an inversely proportional relationship, and methods for simultaneously reducing gate resistance and gate length must be selected and used depending on the properties of the metal used and the shape of the gate pattern. There are, but
There were various problems unique to each method, including the problems of gate resistance and gate length mentioned above. Next, problems with the conventional method will be explained using FIGS. 1, 2, and 3.

Figure 1 shows a schematic cross-sectional view of a MESFET with the most common structure.It is a semi-insulating (]aAs semiconductor substrate 1, an n-type active layer 2, a gate electrode 4!i3, a source electrode 'b', etc.). A low drain electrode 5 is provided.

The conventional manufacturing method of such MESFF, T is shown in Figure 2 (
This will be explained using a) t (b) and FIGS. 3(a)+(b).

As shown in FIG. 2(a), an active layer 2 is formed on a semi-insulating GaAs substrate 1 by ion implantation, and instead of the commonly used photoresist, a photoresist with an opening only in the gate region is used. A mask 6 is provided, and gate metal 3 is vertically deposited on the thorns by vacuum evaporation, and then the photoresist is removed using a solvent. Then, all the metal on the photoresist is removed, and the gate electrode 3 shown in FIG. 1 is obtained. Next, in the same way, Figure 2 (b)
As shown in FIG. 2, a photoresist mask 60' having openings only in the source and drain regions is set using photoresist, and source and drain electrode metals are deposited by vacuum evaporation. Next, the photoresist is removed and heat treated to obtain the MESFFT shown in FIG. 1, in which the gate 3, source 4, and drain 5 are provided. This method is generally called the soft-off method.

Next, the second manufacturing method will be explained using FIGS. 3(a) and 3(b). In this method, as shown in FIG. 3(a), a gate metal 3 is deposited on the entire surface of the substrate on which an active layer 2 is provided, and then a mask 6 is placed on top of the gate metal 3 to form a predetermined gate region.
is formed using photoresist, and then unnecessary portions are removed by wet etching or dry etching to form the gate electrode 3 (3rd IN(b)). Then, source and drain electrodes are provided by the lift-off method using photoresist to obtain the MESFET shown in Figure 1.

In the conventional MESFFiT manufacturing method described above, the following steps are performed:
There were some problems. First, when using a photoresist in the lift-off method, when the gate metal is deposited at a high temperature, the resist with a deformed pattern is baked and cannot be dissolved by a solvent, making lift-off difficult. In addition, gas is generated from the resist1, which significantly deteriorates the adhesion between the GaAs substrate and the gate metal, making the Schottky characteristics unstable.Furthermore, in order to perform lift-off using the resist film thickness, the gate electrode film There were problems such as not being able to obtain a large thickness. This problem is caused by metals with high melting points, such as tungsten (6) and molybdenum (MO)*.
Tantalum (Ta)? It appears prominently in materials such as platinum (Pt).

A second problem is that when using a wet etching or dry etching method, it is necessary to select a material that has a sufficient etching selectivity between the substrate and the gate metal. For example, when the gate electrode is made of aluminum (AI) using the wet etching method, the GaAs substrate is not dissolved at all, and only AI = 1/, and alloys thereof such as titanium Ringesten' (TiW) alloy are still etched well. Liquid has not been developed. Therefore, gate electrodes using these metals cannot be obtained by wet etching;

For metals to which wet etching cannot be applied, dry etching is used.

However, this method has many problems that must be solved, including the problem of redeposition, where the etched metal re-adheres to the substrate surface and deteriorates its properties, the problem of controllability of the etching end point, and the problem of etching uniformity. Currently, there are difficult problems, and a manufacturing method with good characteristics and high productivity has not been established.

The purpose of the present invention is to take advantage of both the dry etching method and the wet etching method in the formation of gate electrodes, and to achieve finer control of the gate electrode and reduction of gate resistance using ordinary photolithography technology. It is an object of the present invention to provide a method for manufacturing a semiconductor device with good uniformity of characteristics and excellent productivity.

According to the present invention, a first film is provided on a semiconductor substrate provided with an active layer, and a second film is further exposed on the first film,
Further etching is performed to remove the exposed first film to expose the semiconductor substrate, and then the semiconductor substrate and the second film are etched.
After depositing the gate metal on the entire surface of the film and applying photoresist on the entire surface, dry etching is used to
sequentially removing the photoresist, the gate metal deposited in areas other than the gate electrode portion, and the second film from the surface;
A method for manufacturing a semiconductor device is obtained, which includes the steps of exposing the first film, and further removing the first film by etching to form a gate electrode on the semiconductor substrate.

According to the present invention, by providing the first film, even if a dry etching method is used to form the opening in the second film, the opening can be formed with high accuracy without causing damage to the semiconductor substrate. Furthermore, by providing the third film, it becomes possible to manufacture a semiconductor device in which the gate length is masked.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIGS. 4(a) to (g) are diagrams for explaining one embodiment of the present invention, and each cross section of the gate electrode, source, and drain electrode of the MESFFliT semiconductor device in the main process is shown in step 1111. be.

An n-type active layer 2 is formed on a GaAs semi-insulating substrate 1 as a semiconductor substrate.Aluminum (A1) is provided as a first film 8 on the GaAs substrate 1 by 200× vacuum evaporation.

Next, as the second film 9, 6000X silicon dioxide (sho2) is formed at 470° C. or lower by the CVD method, which is normally used. The gate area is 1μ by photolithography technology.
Using a resist mask 6 with openings (61) at m, openings (91) are made in the second film 9 8i02 by anisotropic dry etching. (Figure 4(a)). 5
For dry etching of i02, CF is added to the etching gas.
4 is used. Etching power was 17 W/crl. At this time, the etching rate of 8i02 is 250X/min, and the etching rate of AI is 10X/min, so that the S+02 film thickness within the wafer surface is uniform. Next, the third film 9
2, a 5i02 film is formed over the entire surface at a temperature of 9,470° C. or lower to a desired thickness, for example, 0.3 μm (FIG. 4(b)). Then, using an anisotropic dry etching method, the third film 92 is etched from the surface under the conditions described above to open the third film 92 and expose the first film, and then phosphoric acid (
The exposed AI is removed by wet etching using N3PO4) to form an opening 81 and expose the GaAs substrate surface 21 (FIG. 4(C)). Next exposed G
A gate metal such as tungsten-titanium alloy (TiW) 30 is deposited at 50 ooX on the entire surface of the aAs substrate surface 21 using magnetron sputtering. and,
A commonly used photoresist 6o is applied to the entire gate metal surface and dried in N2 gas at 150'C (
Figure 4(d)). At this time, the photoresist 60 is thick because the opening is concave. Next, using a dry etching method such as an ion milling method, the photoresist and then the gate metal are sequentially etched from the surface to form a second layer.
lIX! Remove until 9 is exposed (Figure 4(e))
. The conditions for ion mining were: Ar was used as the ion gas, the pressure was 2X 10-' torr, the arc voltage was 500 V, the arc current was 0.6 A, and the arc current was 110 V.
A, arc voltage 30V, suppressor voltage 200 1
■ Mulberry. And photoresist (AZ-
The etching speed of 1350J (product name) is 150X/
Minutes.

Since TiW has almost the same speed at 170X, an opening is left in the gate metal deposited on the entire surface, and the other part is removed, so that a good gate electrode pattern can be obtained. Next, the exposed 8i04 film, which is the third 1-waste 92, and the 5ift film, which is the second film 9, are removed by etching using buffered hydrofluoric acid.
8 is removed using H3PO4 to form a gate electrode 3 having a gate length of 0.4 .mu.m (FIG. 4(f)).

The source and drain electrodes are then formed, for example, by using a conventional photoresist or by selectively applying a laminated metal film of AuGe alloy and N1 on the surface of the active layer 2 using a seven-off method. In addition, if a highly heat-resistant material such as the TiW alloy described in this example is used as the gate metal, following the process shown in M4 (f), as shown in FIG. 4 (g), By performing high-dose ion implantation using the gate 'H, pole 3 as a mask and annealing, it is possible to form a low resistance contact region 50 extremely close to the gate electrode 3, greatly reducing source and drain resistance. I can do it.

As shown above, the feature of the present invention is wet etching pcle.
It is difficult to form a gate electrode with high heat resistance. The equipment can form food with uniform properties and mass production. In addition, by using the third film, a finer gate length can be easily obtained than the gate mask dimensions originally used, and since it is different from the soft-off method using photoresist, the adhesion of the gate metal and the Schottky properties are improved. is improved.

Since the second film can be obtained arbitrarily, the film thickness of the gate metal is not subject to any restrictions, so that the gate metal film can be obtained thickly, thereby reducing the gate resistance.

As an example of the present invention, a case has been described in which an Al film is used as the first film, an 8i0z film is used as the second film, and an 8i02 film, which is the same as the second film, is used as the third film. Other material films may be used as long as wet etching has a sufficient selectivity between the first film, the second film, and the gate metal.

[Brief explanation of the drawing]

Figure 1, Figure 2 (a), (b) and Figure 3 (a)l
' (b) is a cross-sectional view of the element in the previous process. In the figure, 1 is a semi-insulating semiconductor substrate, 2 is an active layer, 3 is a gate electrode, 4 and 5 are a source transistor and a polar electrode, respectively, 6.60 is a photoresist, 7 is an ohmic metal, and 8 is a first 9 is a second film, 30 is a gate metal, 5o is a low resistance semiconductor region, 61, 81 and 91 are openings, and 92 is a third fiber. This is what is shown. HHF applicant Shima; Gu Hj Director Makoto Ishiita - 1st part 2nd flash 3rd figure 4 figure

Claims (1)

[Claims] an active layer is provided; and a first film is provided on the semiconductor substrate;
Further, a second film is provided on the first film, the second film is partially covered with a mask material, and this is etched by an anisotropic dry etching method to etch the second film, The first film is exposed leaving the third film only on the side surface of the opening of the second film, the exposed first film is removed by etching to expose the semiconductor substrate, and then the semiconductor substrate is etched. A gate metal is deposited on the entire surface of the substrate and the second film, and a photoresist is further applied on the entire surface, and then the photoresist is etched from the surface using a dry etching method. The method includes the step of sequentially removing the metal and then the second film to expose the first film, and further removing the first film by etching to form a gate electrode on the semiconductor substrate. A method for manufacturing a semiconductor device.