JPS59180892A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To detect the memory data in accordance with the charging or discharging direction of a column line and to accelerate the read-out speed of a semiconductor memory by detecting the column line potential with plural sense amplifiers having different levels of potential and comparing this detection data with the data obtained before a prescribed period of time. CONSTITUTION:The comparison potential has a relation of V21<-<V2n and is compared with the column line potential V1 by sense amplifiers SA1-SAn. The results of this comparison are delivered in the form of data D1, -D1-Dn, -Dn. A sense amplifier SAn is activated when the signal phi1 is set at level 1 and delivers Dn=1 and -D=0 when voltage V1>V2n is satisfied and then Dn= 0 and -Dn=1 with V1<V2n respectively. The data Dn is latched by a latch circuit 46 when the signal phi2 is set at 0. Then D'n is delivered, and a comparator 47 compares the numbers of ''1'' between D1-Dn and D'1-D'n when the signal phi3 is set at 1. Thus ''1'' and ''0'' of the detection data are deicided and delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a memory data detecting section of a semiconductor memory, particularly a ROM (!J-only memory).

[Technical background of the invention and its problems]

In general, differential sense amplifiers are often used in semiconductor memories because their operation is stable and they can detect extremely small potential differences. In this case, read/write RAM
(Random access memory), etc., outputs a pair of data with opposite levels as memory data, so this pair of data is led to a pair of input terminals of a differential sense amplifier. Since ROM only outputs data of either 1# or 0'', a comparison potential is prepared using a transistor equivalent to a memory cell as a differential sense amplifier for ROM, and the column line potential (data) is I am trying to read it.

FIG. 1 shows an insulated dart field effect transistor (MOS-F) manufactured by, for example, an N-channel process.
ET), 10 is a memory cell array, 11 groups are memory cell transistors, 12 groups are column selection transistors, 13 are row decoders, 14 are column decoders, and 15 groups are is a row line, 16 group is a column line, 17 to 19 are load transistors, 20.21 is a bias voltage generation resistor, and the above memory cell is connected to 7V-10.
Column line potential v1 determined by data read from
becomes one input of the differential sense amplifier 22. Note that in this sense amplifier 22, CE and CE are control inputs.

On the other hand, 23 is a comparison potential generation circuit, and a comparison transistor 24 is equivalent to the memory cell transistor 1.
25.26 to generate a comparison potential V2k using
27 is a bias voltage generating resistor similar to the resistor 20.21, 27 is a transistor equivalent to the column line dart transistor 12, which is turned on by applying a '1'' level to the dart from the column decoder 14; 30 are transistors equivalent to the load transistors 17 to 19. 31 and 32 are bias resistors for applying a single potential to the terminal of the comparison transistor 24.

In the above ROM, the comparison transistor 24
Since the gate potential of is constant, the comparison potential 2 is a fixed potential with respect to the passage of time, as shown in FIG.

Therefore, if the column line potential ■1 changes across the comparison potential ■2 as shown in FIG. 2 when reading data from the ROM, the output of the differential sense amplifier 22 is inverted, and the output buffer circuit The output vo changes as shown by the dotted line in FIG. For example, if the threshold of the selected memory cell is high, the memory cell will not turn on and the column line will be charged; if it is low, the selected memory cell will turn on and the column line will be discharged.

In this way, the data "1#, '0" is stored in the threshold value of the memory cell transistor. However, as can be seen from the voltage waveform in FIG. 2, the differential sense amplifier 22
In this case, the sense amplifier output level changes when the column line potential v1 crosses the comparison potential (2). Therefore, the read speed of memory data is dominated by the charging and discharging time of the column lines.

Therefore, in order to increase the read speed of memory data, various measures have been taken to speed up the charging and discharging of column line potentials.
No efforts have been made regarding the memory data detection method, that is, the differential sense amplifier section.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and aims to provide a semiconductor memory with a high read speed by improving the sense amplifier section.

[Outline of invention cost]

The present invention detects the column line potential using a plurality of sense amplifiers having different comparison potentials, and compares the detected data with the detected data before a predetermined time. It detects whether the column line is in the charging direction or the discharging direction, and thereby detects memory data while the potential of the column line is changing.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Third
The figure is a schematic configuration diagram of the present invention. In FIG. 3(a), vl is the column line potential as in FIG. 1, V21, V22...
・V2n is the comparison potential, V21<V2□〈...〈■2
n, and its potential is vl and sense amplifier SA1
z SA2 r...SAn, and the result is data DI +Dt ID2, D2 m...
Output as Dn+DB. Sense amplifier SA1~S
All Ans have the same configuration, and differ only in comparison potential. FIG. 3(b) shows the configuration of the sense amplifier SAn. This is a transistor 41.4 whose threshold voltage is approximately zero volts.
2. The enhancement type transistors 43 to 45 are activated when the signal φl is at the 1" level, and the voltage V
When l>v2n, Aki = “1”, D, = “0”, Vokuv
When 2n, Dn=゛0# and Dn-bi are output.

Next, as shown in the latch circuit 46 of FIG. 3(c), the signal φ
2=10", data Dn is latched and output as Dn'. Then, as shown in the comparator 47 of FIG. 3(d), when the signal φ3-°1", DI+D2m . 1 D'2 , . . . The number of 1'' in 9' is compared, and thereby the detected data '1'' and 0'' are determined and output. The above signals φ1, φ2, φ
The time relationship of 3 is shown in Fig. 4. First, during the period To, φ1 becomes 61'', and 1'' and 0'' of data D1 to Dn are determined according to the potential relationship between the column line potential and the comparison potential. Next, during the period T1, φ2="0" and the above D1 to Dn are latched and output as D'1 to Dn'. Then T
φ1 becomes “0” during the period T2, and then φ1 becomes 0 during the period T3.
When 1="1", the sense amplifier is activated again.

At this time, the potential of the column line has already changed due to charging or discharging. Therefore, the detection data D1 to Dn of the sense amplifiers at this time are different from the values before the predetermined time, that is, during the period To. Therefore, an integer comparison of "0" or "P1" between this period D'1-Dn' and the data D1 to Dn in period T3 indicates whether the column line is being charged or discharged. I understand. Therefore, in period T3, φ1
When the data D1%Dn is output from the sense amplifier, it becomes φ3-“1” in the period T4, and at this time, Dl-Dn and D as shown in FIG. 3(d). '1-Dn' are compared and output as detection data.For example, D1~
If the number of 1's in Dn is smaller than p/1~D01', it can be seen that the column line falls in the discharge direction υ, and data of ``0'' is given to the output buffer circuit, and the ``1'' of D1~Dn If the number of `` is greater than D'1 to Dn', it means that the column line is in the charging direction, and data of ``1'' is given to the output buffer circuit. Since it is possible to detect whether the direction is charging or discharging, memory data can be detected more quickly than the conventional method in which the column line potential crosses one fixed comparison potential.

As shown in FIG. 5, since there are a plurality of comparison potentials, it is possible to quickly detect potential changes in the column line potential V1. Furthermore, the greater the number of comparison potentials and the shorter the period of the signals φ1 to φ3, the faster memory data can be detected. As shown in FIG. 6, the signal φ1 (including φ2 to φ3) is
It is only necessary that the chip enable signal C1 is outputted for a predetermined period of time until the data is outputted after the chip enable signal C1 becomes 0'' and the Hirochi chip is selected or the address changes.

Figure 7 is a specific example of the latch circuit shown in Figure 3(c).
For depletion type transistors 51 to 54 and enhancement type (EW) transistors 55 to 62, when signal φ == a O'', r-ta I) yl + D(1
and hold it at φ2-゛1''.

FIG. 8 shows a specific example of the comparator 47 shown in FIG. 3(d),
This consists of one resistor network consisting of R,2R,) Ranjistafs 1-76, the other resistor network consisting of R,2R,) Langistafs 7-82, and transistors 83-93. It has a differential amplifier AM as well as inverters 94 and 95. This is due to the difference in the number of "1"s in data D1 to D and D71ND'6, and the difference in the potentials of V3 and V4. It is detected whether the column line is in a charging or discharging state. Also, the reason that the value of the resistor R97 is R and the signal I is input to the gate of the transistor 96 is 1
Even when the voltage reaches a stable state, an appropriate potential difference appears between v3 and v4, so that data can be detected correctly. Further, the resistance value of the resistor here is set to be sufficiently larger than that of the transistor. Note that a transistor may be used for the resistor 9 here. In Figure 8, n =
Case 6 is shown. Data D1-D3=”l’ID4
~Da ””-0”m D'l ~D'a ””-
9 shows an equivalent circuit of FIG. 8 in the case of 1"aD'5 to D'6=10". In this case, the number of 1'' in D'l-D'6 is greater than the number of 1'' in D1 to D6. That is, since the number of data biases before the predetermined time is greater, this indicates that the column line is in a discharged state. In the equivalent circuit of Fig. 9, D
1 to D3 = "'1#, D'1 to D'4 = "1", and V3<V4. Therefore, V3<V4 is detected by the differential amplifier AM in Fig. 8, and the output buffer to ″′0#
Data is output.

FIG. 10 shows a modification of the three-output circuit shown in FIG. This is transistors 1001 to 100n, 1011
.about.101n, the resistor in the circuit of FIG. 8 is replaced with a transistor. In order to make it equal to that in FIG. 8, the resistance of the transistor to which the signal Dn is input to the dart must be half that of the other transistors. A similar replacement can be made in the circuit that generates V4. FIGS. 11(a) and 11(b) are also modified examples of the respective generating circuits of V3 and v4 in FIG. 103, also 1040-104
Consisting of n, 105. In Figures 11(,) and (b), the value of V- changes depending on the number of 1's in data D1 to Dn, and the value of v4 changes depending on the number of 1s in p/l to Dn'. . As in FIG. 8, the resistance of the transistor to which Dn is dart input is the other half. This is to ensure that there is a difference between V 3 + V 4 even after the column line potential has stabilized, as described above.

FIG. 12 shows a modification of FIG. 8, with transistors 1101 to 1101.
110. ．． 11 No. 1-111n, 112. ~112.1
13nm 114nH115, 116m inverter 11
7.11B, Nordart 119. Nodes E1-E
n is determined by data shoulder # D'1 to DB + Dn', DI="l"(1="O"), D/l-a O
It becomes 1" only when n. That is, if the number of D, -DnK"'1" is large, at least one of E1 to En becomes @1", this is input to the NOR gate 119, and is input to the silatch circuit by φ3. 120 latched. Also, Dl-Dn is more
'1~Dn', if the number of 9 `` 1 '' is small, E1
~En are all '0''), φ3 is the silatch circuit 1
20 hell is latched. When the column line potential is stable at its highest value, Dn=-1" a Dn"'"0" Therefore, Y
``1'' is output to the output buffer.

FIG. 13 shows an output circuit for a signal φ3' which can be effectively used in place of the signal φ3 in FIG. 12. That is, this circuit includes transistors 1311 to 135n.

Like Nordart 136 to 138, when the data D'1 to Dn' before a predetermined time and the current data D1 to Dn are equal, the memory data before the predetermined time is output as is, and the column a potential is stabilized. In this state, a Y generating circuit as shown in FIG. 12 is not required. That is, in the circuit of FIG. 13, Dl-D'1
the law of nature. ', in the case of 5th edition = 1-', the inputs of the Noah route 136 are all '0#', so the output of the Noah gate 136 is +
17, therefore φ'3 is "0", even if φ3 changes, φ'3
Since D remains 0'', in this case, the data before the predetermined time is outputted while being latched. On the other hand, D1 to Dn.

If any one of the data from D'1 to Dn' is different, one of the inputs of the NOR gate 136 is @1'' level, so the output of the NOR gate 136 will be @0'', and φ3 will remain as φ'3. Therefore, when the new changed data is latched, it becomes \.

The present invention can be applied not only to ROMs but also to static formats. In a RAM, the memory cells are composed of cross-coupled flip-flops, so the data read out from the memory cells is usually Q and its inverted data. These Q and Q become a pair of inputs of the sense amplifier. Therefore, as shown in FIG. 14, new data is read out where Q and Q intersect. - If the power tree invention is applied, it is determined whether the column line is in a charging or discharging state, so it is not possible to
Since the data can be detected before the intersection of the Q and Q, the read speed is faster than in the past, and it is only necessary to use Q or only one of them. For example, Q may be used instead of 710 in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, the column line potential is detected by a plurality of sense amplifiers having a plurality of comparison potentials, and this detected data is compared with data before a predetermined time to determine whether the column line is being charged. In order to detect whether the column line potential is in a discharge state or not, it is possible to detect changes in the potential of the column line, and it is possible to detect data much faster than the conventional method of detecting data at the point where the column line potential crosses one comparison potential. It can be detected and the readout speed is faster.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional semiconductor memory, FIG. 2 is a waveform diagram showing the operation of the same configuration, FIG. 3 is a configuration diagram showing an embodiment of the present invention, and FIGS. 4 to 6 are the same configuration. Figures 7 through 9 are partially detailed diagrams of the same configuration, Figure 10 is a waveform diagram showing the effect of
13 through 13 are partially detailed views of different embodiments of the present invention, and FIG. 14 is a waveform diagram showing the operation of a different embodiment of the present invention. 11...Memory cell, 16...Column line, 46...Latch, 47...Comparator 1t SA1-SAn...Sense amplifier. Applicant's representative Patent attorney Takehiko Suzue Figure 2 20 ns → Time Figure 7 φ2 Figure 9 Figure 8 c Figure 11 Vc Figure 12

Claims (2)

[Claims] (1) a memory cell, a column line that receives r-data from the memory cell, a supply source of a different comparison potential, and a plurality of sense amplifiers that compare the comparison potential and the column line potential;
A semiconductor characterized in that it comprises a detection means for detecting data of a memory cell by comparing output data from the plurality of sense amplifiers before a predetermined time and output data from the sense amplifier after the predetermined time. memory. (2) The detection means compares output data from the plurality of sense amplifiers before a predetermined time with output data from the sense amplifiers after the predetermined time.
2. The semiconductor memory according to claim 1, wherein the data of the memory cell is detected by detecting whether the column line potential is in a charging direction or a discharging direction.