JP3137422B2 - Oscillator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit.
The present invention relates to an oscillator circuit for generating a refresh cycle, which is suitable for use in the field of a RAM (Dynamic Random Access Memory) and is used for automatic refresh.

For example, a typical readable / writable memory used in an information processing apparatus such as a computer is an S-type memory.
RAM (Static Random Access Memory) and DRAM
There is. SRAMs have the advantage of having a high-speed memory retention function, but are expensive and unsuitable for increasing the capacity.

On the other hand, since a DRAM has a simple structure and small memory cells, it can be manufactured at a lower cost and has a larger memory capacity than an SRAM. In this case, many designers often use DRAM as a basic building block of a memory system. However, since a DRAM does not have a memory holding function unlike an SRAM, it is necessary to refresh memory cells at regular intervals in order to hold stored data. An oscillator circuit for performing this refresh and a memory of the DRAM are used. Since the operating characteristics of the cell fluctuate with respect to the temperature, the temperature range in which the reliability is ensured is narrow, and the device using the DRAM has to be careful about the operating temperature.

Therefore, there is a demand for an oscillator circuit with improved temperature characteristics and improved reliability.

[0005]

2. Description of the Related Art FIG. 6 shows a block diagram of a 16MDRAM having a self-refresh function as a conventional memory device including an oscillator circuit of this kind. In the figure, 11
Is the first clock generator (clock generator N
o.1), 12 is a second clock generator (clock generator No. 2), 13 is a write clock generator, 14 is a mode controller, 15 is an address buffer and predecoder, 16 is a refresh address counter, 17 is a substrate bias generator, 18 is a row decoder, 19 is a column decoder, 20 is a sense amplifier I /
O gate, 21 is a memory cell, 22 is a data input buffer, and 23 is a data output buffer.

In the above configuration, in order to enter a mode in which refresh is automatically performed, that is, a self-refresh mode, first, as shown in FIG.
(/ CAS is an inverted signal of CAS and indicates a CAS signal with a top bar in FIG. 7), and is then set to “L”, and then / RAS (/ RAS is an inverted signal of RAS;
The RAS signal with a top bar in FIG. 7 is set to "L", and if this state is maintained for 100 .mu.s, the refresh operation is automatically and periodically performed inside the DRAM.

The generation of this period is shown in FIG.
Using an oscillator circuit called a ring oscillator
Is common. This oscillator circuit is
Power supply line V_CCAnd low-potential power line V_SSBetween the gate and low
P-channel MOS transistor receiving potential level signal
TA Q₁₁(Q_{twenty one}~ Q _n1), The gate which receives the input signal at the gate
Channel MOS transistor Q₁₂(Q_{twenty two}~ Q _n2) And N
Channel MOS transistor Q₁₃(Q_{twenty three}~ Q_n3),Gate
N-channel MOS transistor receiving a high potential level signal
Jista Q₁₄(Q_{twenty four}~ Q_n4) Are connected in series in order.
Inverter circuits INV1 to INVn are connected in a ring.
Thus, a predetermined clock cycle is generated.

[0008]

However, in such a conventional oscillator circuit, since a plurality of inverter circuits each composed of a MOS device are connected, there are the following problems. . That is, the relationship between the cycle of the ring oscillator and the dependence of the actual cell refresh interval on the temperature has a relationship as shown in FIG. 9, and the cycle t _{cyc of the} ring oscillator becomes slower as the temperature rises, but the memory cell has a lower temperature. Becomes higher, the memory retention time becomes shorter, and therefore, the interval of the refresh time t _REF must be shortened as the temperature rises.

In other words, if the operating temperature rises beyond the permissible operating range of the system due to the difference in the temperature characteristics between the ring oscillator and the memory cell, the worst case is that the DRA
There is a possibility that the data stored in M may be erased. [Object] It is an object of the present invention to provide an oscillator circuit with improved temperature characteristics and improved reliability.

[0010]

In order to achieve the above object, an oscillator circuit according to the present invention has a principle diagram as shown in FIG. 1 in which an oscillator circuit is connected between a high potential power supply line V _CC and a low potential power supply line V _SS. , A predetermined number of P-channel MOS transistors Q ₁₁ , Q ₁₂
(〜Q _n1 , Q _n2 ) and a predetermined number of N-channel MOS transistors Q ₁₃ , Q ₁₄ (〜Q _n3 , Q _n4 ) connected in series in order, and an inverter circuit INV 1 (〜INVn); wherein the V _CC between a low-potential power supply line V _SS, a first P to enter the potential level of the low potential power source line V _SS to the gate
The channel MOS transistors Q _A1 and a first resistor R _A1 sequentially connected in series, a first of the connection point N _A1 of said first P-channel MOS transistor Q _A1 and the first resistor R _A1 and low-potential output terminal a resistor unit 1, the said high-potential power supply line V _CC between a low-potential power supply line V _SS, a first N for inputting the voltage level of the high potential power supply line V _CC to the second resistor R _B1 and gate
The channel MOS transistors Q _B1 are connected in series in order,
The connection point N _B1 with the second resistor R _B1 and said first N-channel MOS transistor Q _B1 and a second resistor means (2) for a high-potential output terminal, a low-potential output terminal of the first resistor means 1 the plants in the inverter circuit INV1 (~INVn)
Of the constant P-channel MOS transistor Q ₁₁ (to Q _n1 )
One of the gates, and the high potential output terminal of the second resistance means 2 is connected to the inverter circuit INV1 (-
INVn), the predetermined number of N-channel MOS transistors
Connected to one gate of the Njisuta Q ₁₄ (~Q _n4), and configured to generate a predetermined clock cycle of the inverter circuit INV1 (~INVn) connected to the plurality of stages annular.

[0011]

The present invention utilizes the fact that the gm of a MOS transistor decreases with an increase in temperature, that is, the resistance value increases, while the resistance value of the resistance hardly changes with temperature. In other words, since the resistor and the MOS transistor whose gate is supplied with a predetermined potential are connected in series, this MOS transistor operates in a triode region, and can be regarded as a resistor.
The resistance value of the S transistor increases as the temperature increases.

On the other hand, the resistance value of a normal resistor hardly changes due to a rise in temperature (it can be ignored when compared with the change in a MOS transistor). The potential at the connection point changes. Here, if the action of the second resistor means is described as an example, the connection point node N _B1 N
Channel MOS transistors Q ₁₄ , Q ₂₄ ,..., Q _n4
Is set slightly higher than the threshold value of the N-channel MOS transistors Q ₁₄ , Q ₂₄ ,
_.. , Q _n4 rise, so that the N-channel MOS transistors Q ₁₄ , Q ₂₄ ,.
.., Gm of Q _n4 will increase.

The ring oscillator is composed of g of each of the N-channel MOS transistors Q ₁₄ , Q _{24 ,.}
Since the operating speed depends on m, the cycle becomes faster as the temperature rises. By the way, the connection point N in the first resistance means
_A1 and P-channel MOS transistors Q ₁₁ , Q ₂₁ ,.
, Q _n1 .

That is, since the cycle becomes faster as the temperature rises, the cycle of the self-refresh is shortened, whereby the temperature characteristics of the oscillator circuit are improved and the reliability at a high temperature is improved. Further, in this case, at the normal use temperature, a margin is provided for the refresh timing, so that the operation current at the time of the self-refresh in the actual operation can be suppressed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram illustrating Embodiment 1 of the oscillator circuit according to the present invention, and is a circuit diagram illustrating a main configuration thereof. First, the configuration will be described.

In FIG. 2, the same numbers as those given to the principle diagram shown in FIG. 1 indicate the same parts. The oscillator circuit of this embodiment is roughly divided into an inverter circuit INV
1 to INVn, first resistance means 1 and second resistance means 2. The inverter circuits INV1 to INVn are:
Like the principle diagram of Fig. 1, between the high voltage supply line V _CC and a low potential power supply line V _SS, P-channel MOS transistor Q ₁₁ which receives a signal from the first resistance element 1 to the gate (Q ₂₁ ~
Q _n1 ), a P-channel MOS transistor Q ₁₂ (Q _{22 to} Q _n2 ) and an N-channel MOS transistor Q ₁₃ (Q _{23 to} Q _n3 ) which receive an input signal at the gate, and a signal from the second resistance means 2 at the gate. N channel MOS transistor Q
₁₄ (Q _{24 to} Q _n4 ) in series.

The first resistance means 1 is connected to the high potential power supply line V _CC and the first P-channel MOS in the first resistance means 1 shown in FIG.
The gate is connected to the first P-channel M between the transistor Q _A1
A second P-channel MOS transistor Q _A2 connected to the source of the OS transistor Q _A1 is provided in series,
Similarly the second resistor means 2, between the first N-channel MOS transistor Q _B1 in the second resistance means 2 shown in FIG. 1 and a low-potential power source line V _SS, a gate of the first N-channel MOS transistor Q _B1 Second N-channel MO connected to source
An S transistor _QB2 is provided in series.

In the oscillator circuit shown in FIG. 1, the potential of a connection point (hereinafter, referred to as a node) N _B1 is
N-channel M such that the threshold value + alpha of the transistor Q ₁₄
It is necessary to adjust the resistance ratio between the OS transistor Q _B1 and the resistor R _B1 . However, the variation in the threshold of the N-channel MOS transistor Q ₁₄ occurs, N-channel MO
The current flowing through the S transistor Q ₁₄ is at risk vary greatly.

Therefore, in the present embodiment, the first resistance means 1 is provided with a P-channel MOS transistor Q _A2 and the second resistance means 2
This point is improved by adding an N-channel MOS transistor _QB2 to the circuit. That is, N channel M
Due to the OS transistor Q _B2 , the node N _B2 rises by the threshold, and the potential of the node N _B1 becomes

[0020]

(Equation 1)

## EQU1 ## Here, since the N-channel MOS transistor Q ₁₄ operates in almost saturation region, the current flowing through the N channel MOS transistor Q ₁₄ I (Q ₁₄₎ is

[0022]

(Equation 2)

Since there is no V _th (N) term in the equation, there is no dependency on the threshold value, and N is determined only by the voltage generated between the source and the drain of the N-channel MOS transistor Q _B1.
Gm of the channel MOS transistor Q ₁₄ is determined. Hereinafter, description will be made based on specific numerical values.

Generally, when the temperature rises by 50 ° C., the β of the transistor decreases to about 70%. _{Assuming that} the voltage between the source and the drain of the N-channel MOS transistor Q _B1 at 20 ° C. is V (Q _B1 R), the voltage V (Q _B1 between the source and the drain of the N-channel MOS transistor Q _B1 at 70 ° C. H)

[0025]

(Equation 3)

At this time, the current I (Q ₁₄ H) flowing through the N-channel MOS transistor Q ₁₄ is

[0027]

(Equation 4)

## EQU1 ## Thus, in this embodiment, since the current flowing through the N channel MOS transistor Q ₁₄ as the temperature rises is increased, the self-refresh cycle of the oscillator circuit becomes faster.

FIG. 3 is a diagram showing a second embodiment of the oscillator circuit according to the present invention, and is a circuit diagram showing a main part configuration thereof. In FIG. 3, the same reference numerals as those in the first embodiment shown in FIG. 2 indicate the same parts. In the oscillator circuit of the present embodiment, the low potential output terminal of the first resistance means 1 and the high potential output terminal of the second resistance means 2 are connected via a third resistor R.

That is, in the first embodiment, it is necessary to supply currents to the first resistance means 1 and the second resistance means 2, respectively.
The DC current can be reduced by sharing the data via the.
Therefore, in this embodiment, in comparison with the first embodiment,
Power consumption can be reduced during standby.

FIG. 4 is a diagram showing a third embodiment of the oscillator circuit according to the present invention, and is a circuit diagram showing a main part of the oscillator circuit. In FIG. 4, the same numbers as those in the first embodiment shown in FIG. 2 indicate the same parts. In the oscillator circuit of this embodiment, the resistance R _A1 of the first resistance means 1 shown in FIG.
And a third resistance means 3,3 'substituted on the third N-channel MOS transistors Q _RA to the input end of the gate, as well, the resistance R _B1 of the second resistance means 2 shown in FIG. 2, the input gate And a fourth resistance means 4 which is replaced by a third P-channel MOS transistor _QRB at the end, and outputs the output from the second resistance means 2 to the third resistance means 3, the fourth resistance means 4, and the third resistance means 3 '. And the output terminal of the third resistance means 3 'is connected to a predetermined number of P channels in the inverter circuits INV1 to INVn.
One of the channel MOS transistors Q ₁₁ (Q _{21 to} Q _n1 )
And the output terminal of the fourth resistance means 4 is connected to a predetermined number of inverter circuits INV1 to INVn.
Of N-channel MOS transistor Q ₁₄ of the (Q ₂₄ ~Q _n4)
It is connected to one of the gates .

That is, in the first and second embodiments, although the self-refresh cycle of the oscillator circuit is shortened as the temperature rises, the effect is about 1.42 times. In this embodiment, the effect is further enhanced by using a plurality of resistance means. That is, the source-drain voltage V (Q _B1 H) of the N-channel MOS transistor Q _B1 is changed by the second resistance means 2 in the first stage.

[0033]

(Equation 5)

At this time, the current I (Q _B1 H) flowing through the N-channel MOS transistor Q _B1 is

[0035]

(Equation 6)

## EQU1 ## Here, since the current of the N-channel MOS transistor Q _RA increases 1.42 times and the gm of the P-channel MOS transistor Q _A1 increases 0.7 times,

[0037]

(Equation 7)

Similarly,

[0039]

(Equation 8)

[0040]

(Equation 9)

[0041]

(Equation 10)

The self-refresh cycle can be greatly changed by connecting a plurality of resistance means. FIG. 5 shows an oscillator circuit according to a fourth embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a main part thereof.

In FIG. 5, the same numbers as those of the first embodiment shown in FIG. 2 indicate the same parts. In the oscillator circuit of the present embodiment, the first resistor means shown in FIG.
The potential output terminals, with connecting a first end of capacity <br/> amount C ₀ having one end connected to the high potential power supply, high-voltage of the second resistor means
To position the output end, in which one end is connected to a second end of capacitor C ₁ connected to the low-potential power supply.

That is, the nodes N _B1 ,
N _B2 is a high impedance with respect to the power supply voltage, so that the gm of the P-channel MOS transistor Q ₁₁ (Q ₂₁ ~Q _n1) fluctuates if the supply voltage fluctuates. In other words, in the present embodiment, the MO
This prevents a change in gm of the S transistor.

Thus, in this embodiment, a more stable operation can be obtained as compared with the first embodiment. In the above embodiments, the second resistance means is mainly described, but the operation in the first resistance means is also the same.

[0046]

According to the present invention, the self-refresh cycle can be shortened as the temperature rises, and the self-refresh cycle is shortened, thereby improving the temperature characteristics of the oscillator circuit and increasing the reliability at high temperatures. Can be. Also, in this case, at the normal operating temperature, there is a margin for the refresh timing, so that the operating current at the time of the self-refresh in the actual operation can be suppressed,
Low power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an oscillator circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a main part of the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a main part of a second embodiment.

FIG. 4 is a circuit diagram showing a configuration of a main part of a third embodiment.

FIG. 5 is a circuit diagram showing a configuration of a main part of a fourth embodiment.

FIG. 6 is a block diagram showing an overall configuration of a DRAM having a self-refresh function.

FIG. 7 is a waveform chart for explaining the operation example of FIG. 6;

FIG. 8 is a circuit diagram showing a configuration of a main part of a conventional example.

FIG. 9 is a diagram for explaining a problem of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st resistance means 2 2nd resistance means 3 3rd resistance means 4 4th resistance means INV1-INVn Inverter circuit

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takaaki Suzuki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shigemasa Ito 2-184-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu VSI (72) Inventor Masato Takita 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Akira Sugiura 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Inc. (72 ) Inventor Kazuko Yamaguchi 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-4-30569 (JP, A) JP-A-2-76253 (JP, A) JP-A-4 -129264 (JP, A) JP-A-61-87416 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/401-11/4 099 H01L 27/10 481 H03K 3/354 WPI (DIALOG)

Claims (4)

(57) [Claims] An inverter circuit including a predetermined number of P-channel MOS transistors and a predetermined number of N-channel MOS transistors connected in series between a high-potential power supply line and a low-potential power supply line; A first P-channel MOS transistor for inputting the potential level of the low-potential power line to a gate and a first resistor in series between the first P-channel MOS transistor and the low-potential power line; A first resistance means having a connection point with the first resistance as a low potential output terminal; and a second resistance and a gate between the high potential power supply line and the low potential power supply line. The first N-channel MOS transistors for inputting the potential level of the high potential power supply line are connected in series in order,
A second resistor means having a connection point between a second resistor and the first N-channel MOS transistor as a high-potential output terminal, wherein the low-potential output terminal of the first resistor means is the predetermined number in the inverter circuit. Of P-channel MOS transistor
As well as connected to one gate of out, said plant the high-potential output terminal of the second resistor means in said inverter circuit
One of the constant N-channel MOS transistors
Connect to over preparative and to connect the inverter circuit to the plurality of stages annular a oscillator circuit and generates a predetermined clock period, it said first resistor means, the said high-potential power supply line No. The gate between the first P-channel MOS transistor and the first P-channel MOS transistor
Second P connected to the source of the channel MOS transistor
A channel MOS transistor provided in series, the second resistance means including a second N-channel transistor having a gate connected to a source of the first N-channel MOS transistor between the first N-channel MOS transistor and a low potential power supply line; MOS transistors are provided in series .
Oscillator circuit . 2. An inverter circuit comprising a predetermined number of P-channel MOS transistors and a predetermined number of N-channel MOS transistors connected in series between a high-potential power supply line and a low-potential power supply line; A first P-channel MOS transistor for inputting the potential level of the low-potential power line to a gate and a first resistor in series between the first P-channel MOS transistor and the low-potential power line; A first resistance means having a connection point with the first resistance as a low potential output terminal; and a second resistance and a gate between the high potential power supply line and the low potential power supply line. The first N-channel MOS transistors for inputting the potential level of the high potential power supply line are connected in series in order,
A second resistor means having a connection point between a second resistor and the first N-channel MOS transistor as a high-potential output terminal, wherein the low-potential output terminal of the first resistor means is the predetermined number in the inverter circuit. Of P-channel MOS transistor
As well as connected to one gate of out, said plant the high-potential output terminal of the second resistor means in said inverter circuit
One of the constant N-channel MOS transistors
Connect to over preparative, by connecting the inverter circuits in a plurality of stages annular a oscillator circuit and generates a predetermined clock cycle, in place of the first and second resistors, said first the low potential output terminal of the resistor means and the high potential output terminal of the second resistor means the
Oscillator characterized by connecting via three resistors
Circuit . 3. An inverter circuit comprising a predetermined number of P-channel MOS transistors and a predetermined number of N-channel MOS transistors connected in series between a high-potential power supply line and a low-potential power supply line; A first P-channel MOS transistor for inputting the potential level of the low-potential power line to a gate and a first resistor in series between the first P-channel MOS transistor and the low-potential power line; A first resistance means having a connection point with the first resistance as a low potential output terminal; and a second resistance and a gate between the high potential power supply line and the low potential power supply line. The first N-channel MOS transistors for inputting the potential level of the high potential power supply line are connected in series in order,
A second resistor means having a connection point between a second resistor and the first N-channel MOS transistor as a high-potential output terminal, wherein the low-potential output terminal of the first resistor means is the predetermined number in the inverter circuit. Of P-channel MOS transistor
As well as connected to one gate of out, said plant the high-potential output terminal of the second resistor means in said inverter circuit
One of the constant N-channel MOS transistors
A plurality of inverter circuits connected in a ring to generate a predetermined clock cycle , wherein the resistance of the first resistance means has a gate as an input terminal. A third resistance means replaced by a third N-channel MOS transistor; and a fourth resistance means replaced by a third P-channel MOS transistor having a gate as an input terminal, the resistance of the second resistance means; The third resistance means and the fourth resistance means are alternately connected in a predetermined number of stages, and a low potential output terminal of the third resistance means in a final output stage is connected to the predetermined number of P switches in the inverter circuit.
Connected to the gate of one of the channel MOS transistors, and the high potential output terminal of the fourth resistance means in the last stage is connected to the predetermined number of N channels in the inverter circuit.
An oscillator circuit connected to one of the gates of the flannel MOS transistors . 4. An inverter circuit comprising a predetermined number of P-channel MOS transistors and a predetermined number of N-channel MOS transistors connected in series between a high-potential power supply line and a low-potential power supply line; A first P-channel MOS transistor for inputting the potential level of the low-potential power line to a gate and a first resistor in series between the first P-channel MOS transistor and the low-potential power line; A first resistance means having a connection point with the first resistance as a low potential output terminal; and a second resistance and a gate between the high potential power supply line and the low potential power supply line. The first N-channel MOS transistors for inputting the potential level of the high potential power supply line are connected in series in order,
A second resistor means having a connection point between a second resistor and the first N-channel MOS transistor as a high-potential output terminal, wherein the low-potential output terminal of the first resistor means is the predetermined number in the inverter circuit. Of P-channel MOS transistor
As well as connected to one gate of out, said plant the high-potential output terminal of the second resistor means in said inverter circuit
One of the constant N-channel MOS transistors
Connect to over preparative, by connecting the inverter circuits in a plurality of stages annular a oscillator circuit and generates a predetermined clock period, the low-potential output terminal of the first resistor means, one end with the other end is connected to the first capacitor connected to the high potential power source, to the high potential output terminal of the second resistor means, the other end of the second capacitor having one end connected to the low-potential power supply An oscillator circuit, which is connected.