JP3285664B2 - Dynamic random access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates a voltage (step-down voltage) lower than a power supply voltage supplied from the outside in a chip, and uses this step-down voltage as a power supply voltage in the chip.
The present invention relates to a dynamic random access memory .
Generally, semiconductor integrated circuits (dynamic random access
In order to suppress the power consumption of the access memory , or to solve the shortage of the withstand voltage due to the miniaturization of the element size such as the transistor, a step-down voltage lower than the power supply voltage is used.

[0002]

2. Description of the Related Art FIG. 16 is a block circuit diagram showing an example of a step-down power supply generating circuit. In FIG. 16, the step-down voltage V _INT generated by the step-down power supply circuit 1 (22) is lower than the externally supplied high-potential-side power supply V _CC , and is also the externally supplied low-potential-side power supply V _CC. This step-down voltage V _INT is higher than V _SS , and this step-down voltage V _INT is applied to, but not limited to, the + (plus) power supply of the multi-stage inverter gates 2 to 6 (the number of stages is an example) constituting the ring oscillator 7. . In addition,-(minus) of the inverter gates 2 to 6
The power supply is supplied with a low potential voltage V _SS .

The frequency φOSC of the ring oscillator 7 is
For example, it is used to control the refresh time of DRAM, PSRAM, VSRAM, etc.
_Assuming that the number of stages of 6 is N and the delay times are t _pLH and t _pHL , the following equation is given. φOSC = 1 / {N (t _pLH + t _pHL )} where _tpLH is the delay time until the output switches to the H level when the input changes to the L level, and t _PHL is the delay in the opposite case. It is time and is sensitive to fluctuations in power supply voltage and temperature.

FIG. 17 shows a plurality of PN diodes D ₁ and D ₁ .
_This is an example of a step-down power supply circuit in which ₂ ,..., D _n−1 and D _n are connected in series. Assuming that the forward voltage of one diode is V _FR and the number of connected diodes is M, the step-down voltage (step-down power supply voltage) V _INT is given by the following equation. V _INT = V _FR × M… Although the number of components is small, the diode has a negative temperature dependency of about 2 mV / ° C. (V _FR decreases as the temperature rises). When combined with the ring oscillator 7, the following disadvantages may occur.

In general, DRAM, PSRAM, VSRA
The refresh time such as M needs to be shortened as the temperature increases. This is because the charge of the cell is easily lost at a high temperature. That is, the appropriate refresh cycle (in other words, the storage retention time (required refresh cycle)) t _REF as viewed from the cell side is as shown in FIG.
As shown in FIG. 8, the temperature tends to be shorter as the temperature is higher. For example, there is a difference of “1/10” between 0 ° C. and 100 ° C.

On the other hand, the cycle time of the output φOSC of the ring oscillator for determining the refresh time (in other words, the actual refresh cycle) t
_CYC, the temperature change of the V _{IN T,} i.e., the diode D ₁
It indicates a negative tends to be longer as the temperature rises under the influence of the temperature dependence of the to D _n, for example, between 0 ℃ and 100 ° C.: it is open "1 2" ones. This change in t _CYC is shown in FIG.
As shown in FIG. 8, since the direction is opposite to t _REF ,
Refreshing is not enough in the middle and high temperature range,
A fatal inconvenience of losing the information held in the cell occurs.

To avoid this, conventionally, φOSC
Is set to the high frequency side, so that t _CYC in a high-temperature region (for example, 100 °) which is a worst case is substantially equal to t _REF.
Had to match. That is, t _CYC in FIG. 4 was moved downward in the drawing.

[0008]

SUMMARY OF THE INVENTION
Countermeasures can optimize the number of refreshes at high temperatures
However, the number of refreshes is excessive in the middle and low temperature range
Since this medium / high temperature area is also a normal temperature area,
There is a problem that power consumption is greatly increased. In addition,
The bandgap reference voltage type basic circuit (band) shown in FIG.
Consider using a step-down power supply circuit as the gap voltage reference).
available. In FIG. 19, Q₁~ Q_ThreeIs npn type
Bipolar transistor, R₁~ R_ThreeIs the resistance, I_CIs
It is a constant current source. Output voltage V_INTIs Q_ThreeBase-d
Voltage V between transmitters_BE3And load resistance R _TwoVoltage I_TwoR_Two
Given by the sum of V_BE3Is the negative temperature coefficient, I_TwoR_TwoIs
To have a positive temperature coefficient, V_BE3And I_TwoR_TwoPercentage of
By optimization, the higher the temperature, the higher the V_INTIs large
It is possible to provide a temperature characteristic that makes it easier to work. this
According to t_CYCIs changed to the lower right, and t
_REFCan be approached, but the bipolar tiger
Since transistors are used, power consumption cannot be sufficiently reduced.
There is a point.

SUMMARY OF THE INVENTION An object of the present invention is to provide a step-down power supply circuit having a positive temperature characteristic without complicating the configuration and advantageous in power consumption.

[0010]

FIG. 1 shows a semiconductor integrated circuit (dynamic random access memory) according to the present invention.
FIG. 2 is a circuit diagram showing a principle configuration of a step-down power supply circuit (step-down power supply generation circuit) in FIG. According to the present invention, the first power supply line V includes the depletion type MOS transistor DMOS.
cc and higher than the potential Vss of the second power supply line, and the potential increases as the temperature rises.
And the gate of the depletion type MOS transistor
A dynamic random number, comprising: a step-down power supply circuit 22 for generating a step- down power supply voltage V _INT determined by a source-to-source voltage; and a ring oscillator circuit (7) for controlling the refresh time which receives the step-down power supply voltage 22. Access memory is provided.

The step-down power supply circuit 22 is an N-channel type.
A depletion type MOS transistor DMOS and a resistance means R, and a drain of the depletion type MOS transistor DMOS is connected to the first power supply line;
A gate is connected to the second power supply line, and a source is connected to the second power supply line via the resistance means R. Alternatively, the step-down power supply circuit 22
Depletion type MOS transistor DMOS
And depletion type MOS transistor
Connecting the drain of the transistor DMOS to the second power supply line
Connecting a gate to the first power supply line, and
Is connected to the second power supply line via the resistance means R.
It has become.

[0012]

According to the present invention, a gate-source voltage of a depletion type MOS transistor (hereinafter, DMOS) appears at both ends of the resistance means R, and this voltage is taken out as a step-down voltage. Here, the gate-source voltage V _GS of the DMOS having the above configuration is a constant potential at which the source side has a positive polarity with respect to the gate side, and the DMOS operates until a negative potential lower than this potential is applied to the gate. This is a so-called normally-on type element for connecting ON. The constant potential is set to an enhancement type MOS transistor (hereinafter referred to as E
MOS). In general, the threshold is a name used only for EMOS,
Assuming that the same name is used for convenience in this specification, the threshold value of the DMOS has a positive temperature dependency.
The step-down voltage extracted according to the above-described embodiment increases its potential as the temperature increases.

Therefore, such a step-down voltage is, for example,
If the present invention is applied to an oscillator circuit for determining a refresh time, the period of the oscillation frequency φOSC can be corrected so as to become shorter as the temperature rises.
The number of refreshes of M, VSRAM, etc. can be optimized according to the environmental temperature. Note that it is preferable to increase the number of DMOSs because the change width of the step-down voltage with respect to the temperature, that is, the temperature sensitivity can be increased.

Further, if the EMOS is used together, the step-down voltage can be corrected to the decreasing side by the temperature coefficient (negative).
The number of DMOSs can be increased by the amount of the correction, and the temperature sensitivity can be increased.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, a semiconductor integrated circuit (dynamic random access memory) according to the present invention will be described.
(D: DRAM) will be described. 2 to 10 show a first embodiment of a semiconductor integrated circuit according to the present invention, which is an example applied to a DRAM. First, the configuration will be described. 2, reference numeral 10 denotes a first clock generator, 11 denotes a second clock generator, 12 denotes a write clock generator, 13 denotes a mode control circuit, 14 denotes a data input buffer, 15 denotes a data output buffer, and 16 denotes an address buffer (including). Predecoder),
17 is a row decoder, 18 is a column decoder, 19 is a sense amplifier (including I / O gate), 20 is a memory cell array, 21 is a refresh address counter, 22 is a step-down power supply circuit, 23 is a ring oscillator 23a, and a frequency dividing circuit 23b. , A self-refresh circuit group including a substrate bias generator 23c and a timing circuit 23d.

RAS (bar) is a row address strobe signal, CAS (bar) is a column address strobe signal, WE (bar) is a write enable signal, OE (bar).
(Bar) is an output enable signal, A _{0 to} A ₁₁ are address signals, DQi is input / output data, V _CC is a high-potential power supply, V _SS is a low-potential power supply, V _INT is a step-down power supply, φSR
Is a refresh cycle mode signal.

[0017] In such a configuration, A ₁ to A ₁₁ at the timing of the falling edge of RAS is taken as a row address, also, A ₁ ~ at falling timing of the CAS
A ₁₁ is taken as a column address. Then, the memory cell array 20 is accessed by these addresses, and if WE is active, data writing,
Alternatively, if OE is active, data reading is performed.

Here, the contents of the DRAM memory cell must be refreshed every predetermined time (refresh time). When a read cycle, a write cycle, a read-modify-write cycle, or the like is executed within the refresh time standard, the cell subjected to the processing is automatically refreshed. It is necessary to execute a refresh operation.

That is, when the mode control circuit 13 detects that the read / write operation has not been performed within the refresh time standard, a signal φSR is output from this circuit, whereby the refresh address counter 2
1 starts an operation to generate an internal address for refreshing, and a self-refresh circuit 23 starts an operation, divides the φOSC from the ring oscillator 23a by a dividing circuit 23b, and outputs its divided output and The AND logic result with the output from timing circuit 23d is applied to first clock generator 10, and self-refresh is started.

FIG. 3 is a block diagram of the step-down power supply circuit 22. The step-down power supply generation circuit 22 includes two depletion type MOS transistors DMOS ₁₁ and DMOS ₁₂ having drains connected to a high-potential-side power supply (line) V _CC supplied from the outside.
When, the source and the low potential side resistor connected between a power supply (line) V _SS (resistance means) R ₁₁ of DMOS _11, the resistance (resistance means) between the source and V _SS of the DMOS ₁₂ R ₁₂ and a enhancement type MOS transistor EMOS ₁₁ of diodes connected connected via, constructed by connecting the gate of the DMOS ₁₁ to V _SS.

In such a configuration, both the DMOS ₁₁ and the DMOS ₁₂ are normally-on devices, that is, devices that are turned off when the gate potential is reduced by a certain potential from the source potential. Some potential is EMOS
(Normally-off type element) is a potential corresponding to the threshold value V _TH , and when the gate potential is set as a reference (0 V), EM
The OS has a “negative” source potential and the DMOS has a “positive” source potential (however, in the case of an n-channel MOS).

For example, DMOS₁₁, DMOS₁₂And E
MOS₁₁(The absolute value of the threshold value) is 0.5V
And DMOS₁₁Gate-source voltage V_{GS (DMOS11)}When
DMOS₁₂Gate-source voltage V_{GS (DMOS12)}Together
+ 0.5V, EMOS₁₁Gate-source voltage V
_{GS (EMOS11)}Becomes -0.5 V of the opposite polarity. Therefore,
DMOS₁₁Gate potential (V_SS), DM
OS₁₁Has a source potential of +0.5 V (= V_{GS (DMOS11)}),
DMOS₁₂Has a source potential of +1.0 V (= V_{GS (DMOS1 1)}
+ V_{GS (DMOS12)}), EMOS₁₁Source potential is +0.5
(= V_{GS (DMOS11)}+ V _{GS (DMOS12)}+ V_{GS (EMOS11)})
available. That is, V_INTIs 0, as shown in FIG.
V + V_{GS (DMOS11)}+ V_{GS (DMOS12)}Level A (+1.0
V) to V_{GS (E MOS11)}Level B (+0.5
V).

Here, the threshold value of the DMOS has a temperature coefficient of "positive", while the threshold value of the EMOS has a temperature coefficient of "negative". That is, as the temperature rises, the DMO
The threshold value of S changes its value to the increasing side,
The threshold value of the EMOS changes to the decreasing side. ΔV _THD , EMO
_Assuming that the threshold change amount of S is ΔV _THE , V _INT is given by: V _INT = | V _{TH (DMOS11)} + V _{TH (DMOS12)} + 2ΔV _THD | −V _{TH (EMOS11)} + ΔV _{TH (EMOS11)} An increase of 2ΔV _THD + ΔV _THE is expected.
FIG. 5 is a diagram showing the temperature characteristics of the level A and the level B (= V _INT ).
It depends on the difference in the temperature coefficient of the MOS.

[0024] As described above, in this embodiment, in addition to the threshold level (0V) to the EMOS2 stage of the V _SS, resistance potential thresholds by subtracting the EMOS1 stages from the addition potential R _Take out from both ends of ₁₂ , for example, DRA
A step-down voltage V _INT suitable for a ring oscillator for determining a refresh cycle such as M can be generated.

That is, as the temperature rises, the step-down voltage V
_Since the potential of _INT increases, the ring oscillator 23a
The output φOSC (see FIG. 2) changes to the high frequency side as the temperature rises, and as a result, the slope of t _CYC in FIG. 18 decreases to the left and the difference from t _REF is reduced. Therefore, φOSC changes in accordance with the required refresh cycle, and the refresh cycle can always be appropriately controlled at various temperatures from a low temperature range to a high temperature range. In particular, an excessive refresh operation in a normal temperature range is performed. Avoidance can reduce power consumption. Also, MO
Since the S transistor is used, in other words, a bipolar transistor requiring a bias current is not used, so that the step-down power supply circuit 22 with low power consumption can be provided.

In the above embodiment, two DMOSs and one EMOS are used.
If it is acceptable to use _INT , it can be constituted by one DMOS. That is, from the source of the DMOS ₁₁ in FIG.
_INT may be extracted, and V _INT in this case is DMO
The potential went up from only V _SS threshold of S _11. The threshold of DMOS and EMOS is slightly sometimes fluctuate due to fluctuations in process parameters, such variation, for example, as shown in FIG. 6, for adjustment between the source and the resistor R ₁₂ of EMOS ₁₁ the R _T resistor provided can be modified by trimming the R _T resistor.

As shown in FIG. 7, DMOSs may be connected in multiple stages. For example, as shown in the figure, if there are four stages from DMOS ₂₁ to DMOS ₂₄ , the level increased by four stages of threshold (+0.5 V for one stage),
The level dropped EMOS1 stages from 2V) can be a potential of V _INT, can be suitable for applications requiring V _INT of high potential. Incidentally, in FIG. 7, R ₂₁ to R ₂₄ is the resistance (resistance means).

If the threshold value fluctuates due to the process parameters and V _INT does not reach the desired potential, as shown in FIG. 8, the source side (or drain side or both sides) of DMOS ₂₁ to DMOS ₂₄ is used. In addition, trimming resistors R _{T21 to} R _T24 may be inserted. FIG.
As shown in the figure, a diode-connected EMOS ₃₁ , EMO
S ₃₂ (may be a bipolar transistor) may be used as the resistance means.

As shown in FIG. 10, each transistor (DMOS ₄₁ , DMOS ₄₂ and EMOS _{41 in the} figure)
The substrate potential and the source potential may be the same. The influence of the back bias can be eliminated.
That is, according to the step-down power supply circuit of FIG. 10, the threshold voltage in each of the depletion type and enhancement type MOS transistors DMOS ₄₁ , DMOS _{42 and} EMOS ₄₁ is accurately defined, and the temperature characteristic in the step-down power supply circuit is more accurately determined. By setting, optimum temperature compensation can be performed.

FIGS. 11 to 15 show a second embodiment of the semiconductor integrated circuit according to the present invention. FIG. 11 illustrates a second embodiment of the step-down power supply circuit in the semiconductor integrated circuit according to the present invention. FIG. As shown in FIG. 11, the output (step-down power supply voltage) V _INT of the step-down power supply circuit 1 (22) of the second embodiment is similar to the step-down power supply circuit shown in FIG.
The signal is supplied to a ring oscillator 7 composed of inverters 2 to 6. However, in the present embodiment, the super-high voltage SVcc having a higher potential than the normal high voltage Vcc is applied to the power supply line on the high potential side.

That is, the step-down power supply circuit 1 of the second embodiment
In (22), the first power supply line is an ultra-high potential power supply line for supplying an ultra-high voltage SVcc higher than the normal high potential voltage Vcc, and the second power supply line is for supplying a normal low potential voltage Vss. Low-potential power line. FIG. 12 is a diagram showing temperature characteristics in the step-down power supply circuit of FIG.
As is apparent from FIG. 11, in the step-down power supply circuit of FIG. 11, the temperature characteristic α when a normal high potential voltage Vcc is applied is an ultra-high voltage SVcc higher than the normal high potential voltage Vcc.
When applied, the temperature characteristic becomes α ′, and
The temperature characteristic β when a normal high potential voltage Vcc is applied is
When an ultra-high voltage SVcc is applied, the temperature characteristic becomes β ′. Thereby, the step-down voltage (step-down power supply voltage) V
The potential of _INT is changed to a higher potential than when the normal high potential voltage Vcc is applied, that is, the refresh cycle (the output φOSC of the ring oscillator) is changed to a shorter cycle, and temperature compensation can be performed in a wider range. It has become.

FIG. 13 is a circuit diagram showing a third embodiment of the step-down power supply circuit in the semiconductor integrated circuit according to the present invention. In the figure, reference numeral 10 denotes a step-down power supply circuit 2 shown in FIG.
This corresponds to 2. As shown in FIG. 13, in the third embodiment, the step-down voltage V of the step-down power supply circuit 10 (22) is applied.
A P-channel MOS transistor functioning as a constant current source CCS is connected to an output terminal that outputs _INT . That is, the source of the P-channel MOS transistor is connected to the high potential power supply line (Vcc), the gate is connected to the low potential power supply line (Vss), and the drain is connected to the output terminal (V _INT ) of the step-down power supply circuit. It is supposed to. As a result, the P-channel MOS transistor (CC) is transferred from the high potential power supply line (Vcc) to the low potential
S) and a constant current always flows through the resistor R, and the step-down voltage V _INT generated by the step-down power supply circuit is maintained at a potential equal to or higher than a predetermined level even when the temperature drops below a predetermined temperature. ing.

FIG. 14 shows the required refresh cycle t _REF in the step-down power supply circuit and the output φOS of the ring oscillator.
FIG. 1 is a diagram showing the relationship between C and the cycle time t _CYC1 , and FIG.
FIG. 5 is a diagram showing the relationship between the required refresh cycle t _REF and the cycle time t _CYC2 of the output φOSC of the ring oscillator in the step-down power supply circuit of FIG. First, FIG.
As shown in FIG. 1, for example, the step-down power supply circuit 2 shown in FIG.
Second output voltage (V _INT) is supplied to the ring oscillator (7), when to perform the self-refresh operation of the DRAM, for the temperature T ₁ of less temperature, the ring oscillator output φOSC cycle time ( The refresh cycle (t _CYC1 ) is longer than the required refresh cycle (storage holding time) t _REF , and data cannot be held. This means that the temperature setting range of the temperature compensation must be higher than the temperature T _1, and also means that the range of the temperature compensation is narrowed.

On the other hand, as shown in FIG.
For example, the step-down power supply circuit 10 of the third embodiment shown in FIG.
Is supplied to the ring oscillator (7) and the self-refresh operation of the DRAM is performed.
A constant current always flows through the resistor R by the S transistor CCS, and the step-down voltage V _INT is always kept at a potential equal to or higher than a certain level. That is, the refresh cycle t _CYC2 does not become longer than a certain level even at a temperature lower than the temperature T ₂ and the refresh cycle t
_CYC2 is always the required refresh cycle t _REF
And the data can be held reliably. In other words, according to the third embodiment, the range of temperature compensation can be expanded.

FIG. 20 is a circuit diagram showing a basic modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.
FIG. 21 is a circuit diagram showing an embodiment of a step-down power supply circuit according to the present invention to which the modification of FIG. 20 is applied. In the embodiment shown in FIGS. 1 to 12, the depletion type MOS transistor and the enhancement type MOS transistor constituting the step-down power supply circuit are configured as N-channel type MOS transistors. However, the semiconductor integrated circuit (step-down power supply circuit) according to the present invention. As shown in FIGS. 20 to 24, depletion type MOS transistors and enhancement type MOS transistors
The transistor can be configured as a P-channel MOS transistor.

That is, in the step-down power supply circuit 22 of FIG. 1, the drain of the N-channel depletion type MOS transistor DMOS is connected to the first power supply line (high potential power supply line) Vcc, and the gate is connected to the second power supply line. (Low-potential power supply line) The second power supply line Vss is connected via an N-channel enhancement-type MOS transistor EMOS and a resistor R which are connected to Vss and whose source is diode-connected.
Connected to ss. Then, the output voltage (step-down power supply voltage) V _INT is taken out from a connection point between the enhancement type MOS transistor EMOS and the resistor R.

On the other hand, in the step-down power supply circuit 922 of the basic modification shown in FIG. 20, the drain of the P-channel depletion type MOS transistor DMOS is connected to the first power supply line (low potential power supply line) Vss. , The gate is connected to a second power supply line (high-potential power supply line) Vcc, and the source is connected to the second power supply line Vcc via a diode-connected P-channel enhancement type MOS transistor EMOS and a resistor R. Have been. Then, the output voltage (step-down power supply voltage) V _INT is taken out from a connection point between the enhancement type MOS transistor EMOS and the resistor R.

The step-down power supply circuit shown in FIG. 21 corresponds to the step-down power supply circuit of FIG. 3 and includes a depletion type MOS transistor DMOS ₁₁ , DMOS ₁₂ and an enhancement type MOS transistor EMOS _{11 connected} to a P-channel type MMOS.
It is configured as an OS transistor. here,
Depletion type MOS transistor DMOS ₁₁ , DM
The drain of the OS ₁₂ is connected to a low-potential power supply line (first power supply line) Vss
Connected to the depletion type MOS transistor DM
The source of the OS ₁₁ via the resistor R ₁₁ high-potential power supply line (second
And the source of the depletion type MOS transistor DMOS ₁₂ is a diode-connected enhancement type MOS transistor EMO.
High-potential power supply line via the S ₁₁ is connected to the (second power supply line) Vcc.

FIG. 22 is a diagram showing the potential level of the step-down voltage in the step-down power supply circuit of FIG. 21, and corresponds to FIG. FIG. 23 is a diagram showing a temperature characteristic of a step-down voltage in the step-down power supply circuit of FIG. 21, and corresponds to FIG. FIG. 24 is a circuit diagram showing an example of a ring oscillator to which the step-down power supply circuit of FIG. 21 is applied, and corresponds to FIG.

As shown in FIG. 24, when the step-down power supply circuit 901 of FIG. 21 is applied to a ring oscillator 907 composed of inverters 902 to 906, the drive voltage of the ring oscillator 907 is the high potential power supply voltage Vcc and the potential of the node D. since the voltage (V _INT) difference between the voltage (Vcc-V _INT),
As shown in FIG. 23, when the voltage of the node D decreases with an increase in temperature, the oscillation frequency of the ring oscillator 907 increases with an increase in temperature.

That is, the driving voltage (Vcc- _VINT ) increases with the rise in temperature.
07 (see FIG. 24), the output φOSC changes to the high frequency side as the temperature rises, so that the refresh cycle can always be appropriately controlled for various temperatures from a low temperature range to a high temperature range, and particularly, in the normal temperature range. Excessive refresh operation can be avoided and power consumption can be suppressed.

In the above description, mainly the step-down power supply circuit
Although the case where the present invention is applied to the self-refresh circuit of the RAM has been described, the semiconductor integrated circuit having the step-down power supply circuit according to the present invention is not limited to the DRAM, and it goes without saying that the present invention can be applied to various circuits. Absent.

[0043]

According to the present invention, it is possible to provide a step-down power supply circuit having a positive temperature characteristic which is advantageous in terms of power consumption without complicating the structure and, for example, determines a refresh cycle of a DRAM or the like. Voltage V _INT suitable for a ring oscillator for the purpose of the present invention can be generated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a principle configuration of a step-down power supply circuit in a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram showing an overall configuration of one embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a circuit diagram showing a first embodiment of a step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 4 is a diagram showing a potential level of a step-down voltage in the step-down power supply circuit of FIG. 3;

FIG. 5 is a diagram showing a temperature characteristic of a step-down voltage in the step-down power supply circuit of FIG. 3;

FIG. 6 is a circuit diagram showing a first modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 7 is a circuit diagram showing a second modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 8 is a circuit diagram showing a third modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 9 is a circuit diagram showing a fourth modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 10 is a circuit diagram showing a fifth modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 11 is a block circuit diagram showing a second embodiment of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 12 is a diagram showing temperature characteristics in the step-down power supply circuit of FIG. 11;

FIG. 13 is a circuit diagram showing a third embodiment of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

FIG. 14 is a diagram showing a relationship between a required refresh cycle and a cycle time of an output of a ring oscillator in the step-down power supply circuit.

15 is a diagram showing a relationship between a required refresh cycle and a cycle time of an output of a ring oscillator in the step-down power supply circuit of FIG. 13;

FIG. 16 is a block circuit diagram showing an example of a step-down power supply generation circuit.

FIG. 17 is a block circuit diagram showing an example of a conventional step-down power supply generation circuit.

18 is a diagram showing a relationship between a required refresh cycle and a cycle time of an output of a ring oscillator in the step-down power supply generating circuit of FIG. 16;

FIG. 19 is a circuit diagram showing another example of a conventional step-down power generation circuit.

FIG. 20 is a circuit diagram showing a basic modification of the step-down power supply circuit in the semiconductor integrated circuit of the present invention.

21 is a circuit diagram showing one embodiment of a step-down power supply circuit according to the present invention to which a modification of FIG. 20 is applied.

FIG. 22 is a diagram showing a potential level of a step-down voltage in the step-down power supply circuit of FIG. 21;

FIG. 23 is a diagram showing a temperature characteristic of a step-down voltage in the step-down power supply circuit of FIG. 21;

24 is a circuit diagram showing an example of a ring oscillator to which the step-down power supply circuit of FIG. 21 is applied.

[Explanation of symbols]

DMOS, DMOS ₁₁ , DMOS ₁₂ ... depletion type MOS transistor EMOS, EMOS ₁₁ ... enhancement type MOS transistor R, R ₁₁ , R ₁₂ ... resistance (resistance means) SV _CC ... super high potential side power supply (super high potential side power supply line) V _CC … High-potential-side power supply (high-potential-side power supply line) V _SS … Low-potential-side power supply (low-potential-side power supply line) V _INT … Step-down voltage (step-down power supply voltage) 1,10,22… Step-down power supply circuit

Claims (11)

(57) [Claims] A depletion type MOS transistor having a potential lower than a potential of a first power supply line and higher than a potential of a second power supply line, the potential of which rises as the temperature rises ; The depletion type MOS transistor
A dynamic random access memory, comprising: a step-down power supply circuit for generating a step-down power supply voltage determined by a gate-source voltage of a transistor; and a ring oscillator circuit for controlling a refresh time receiving said step-down power supply voltage. . 2. The depletion type MOS transistor is a P-channel type MOS transistor, a drain of the depletion type MOS transistor is connected to the second power supply line, a gate is connected to the first power supply line, and 2. The dynamic random access memory according to claim 1, wherein a source is connected to an output of said step-down power supply circuit. 3. The depletion type MOS transistor is an N-channel type MOS transistor, a drain of the depletion type MOS transistor is connected to the first power supply line, a gate is connected to the second power supply line, and 2. The dynamic random access memory according to claim 1, wherein a source is connected to an output of said step-down power supply circuit. 4. The dynamic dynamic random access memory according to claim 2, further comprising a diode-connected enhancement type MOS transistor between a source of said depletion type MOS transistor and an output of said step-down power supply circuit. -Random access memory. 5. The dynamic random access according to claim 3, further comprising a trimming resistor for adjustment between a source of said depletion type MOS transistor and an output of said step-down power supply circuit.・
memory. 6. The dynamic random access memory according to claim 2, further comprising a resistor between an output of said step-down power supply circuit and said first power supply line. 7. The semiconductor device according to claim 1, further comprising a resistor between the output of the step-down power supply circuit and the second power supply line, wherein the resistor is a diode-connected enhancement MOS transistor. The dynamic random access memory according to claim 3. 8. The semiconductor device according to claim 1, wherein a plurality of the depletion type MOS transistors are provided, and a gate of the subsequent stage depletion type MOS transistor is connected to a source of the preceding stage depletion type MOS transistor.
A dynamic random access memory according to claim 1. 9. The dynamic random access memory according to claim 8, wherein a substrate potential of each of said depletion type MOS transistors is connected to a source of said transistor. 10. The dynamic random access memory according to claim 1, wherein the potential of said first power supply line is higher than a normal high voltage. 11. A step-down power supply circuit for generating a second step-down power supply voltage having no temperature dependency, wherein the step-down power supply voltage from the second step-down power supply circuit is reduced in a low temperature range. 2. The dynamic random access memory according to claim 1, wherein the dynamic random access memory is supplied to a ring oscillator circuit.