JP3235516B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit which steps down a power supply voltage supplied from the outside in the circuit and supplies the voltage to each section.

[0002]

2. Description of the Related Art An internal step-down circuit used in a semiconductor integrated circuit of this type steps down a power supply voltage VCC of, for example, 3.3 V supplied from the outside, and connects this step-down voltage to a first-stage circuit or a first-stage circuit (not shown). As shown in FIG. 6, the memory circuit includes an internal step-down circuit A and an internal step-down circuit B. First, the internal step-down circuit B will be described. The internal step-down circuit B has a comparator 21 of a differential amplifier type.
MOS transistors Q21 and Q22 and constant current source NMO
It comprises an S transistor Q23 and PMOS transistors Q24 and Q25, which are load current mirror circuits.
Here, the internal step-down voltage V is applied to the gate of the transistor Q21.
INT and a reference voltage Vref are applied to the gate of the transistor Q22, respectively.

A voltage corresponding to the level difference between the two differential inputs is obtained from the drain of the transistor Q22. This voltage output is output as the internal step-down voltage VINT by the PMOS transistor Q26,
21 is fed back to the gate. The reference voltage Vref is also applied to the gate of the transistor Q23, so that a constant current is output.

Next, the internal step-down circuit A will be described.
This internal step-down circuit A is also a differential amplifier type comparator 1
1 and the comparator 11 is a differential pair NMO
It comprises S transistors Q11 and Q12, a constant current source NMOS transistor Q13, and load current mirror PMOS transistors Q14 and Q15. Then, the internal step-down voltage VINT is applied to the gate of the transistor Q11, and the reference voltage Vref is applied to the gate of the transistor Q12.

Similarly, a voltage corresponding to the level difference between the two differential inputs is output from the drain of the transistor Q12. This voltage output is output as the internal step-down voltage VINT by the PMOS transistor Q16, and is fed back to the gate of the transistor Q11. The reference voltage Vref is also applied to the gate of the transistor Q13, so that a constant current is output. Transistor Q
13, an NMOS transistor Q17 is connected in series, and the gate of the transistor Q17 is connected to a control signal ACT.
The constant current of the transistor Q13 is turned on and off by turning on and off, thereby enabling the activation control of the internal step-down circuit A to be freely performed.

That is, when the integrated circuit is put into an operating state, the control signal ACT is set to "H" level. Then, a predetermined internal step-down voltage VINT is generated by flowing a constant current through the transistor Q13 of the internal step-down circuit A,
This internal step-down voltage VINT is applied to a first-stage circuit and a memory circuit that constitute an integrated circuit. In this case, the current consumption of each of the internal step-down circuits A and B is about 2.1 mA. On the other hand, the control signal ACT is set to “L” to make the integrated circuit inoperative.
When set to the level, only the internal step-down circuit B operates, and in such a standby state (standby state), the current consumption of the internal step-down circuit B is about 100 μA.

[0007]

As described above, in the conventional semiconductor integrated circuit, when the integrated circuit is not operating, a low current is supplied from the internal step-down circuit B to each part of the integrated circuit so that the internal step-down circuit consumes less power. Current is being achieved. But,
This type of semiconductor integrated circuit generally requires much less time in the non-operation state than in the operation state. Therefore, there is a demand for reducing the current consumption of the internal step-down circuit in the non-operation state. I have. Therefore, an object of the present invention is to reduce the current consumption of an internal step-down circuit of a semiconductor integrated circuit when the integrated circuit is not operating.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a semiconductor integrated circuit which steps down an external power supply and supplies it as an internal operating voltage to each part in the integrated circuit. An internal voltage step-down circuit that lowers the external power supply to output the internal operating voltage at the same time, and at least stops the output of the internal operating voltage when the integrated circuit is in a standby state; And a plurality of internal step-down units for individually stopping the output of the internal operating voltage according to each mode in the standby state of the integrated circuit. A first internal step-down unit for stopping the output of the internal operating voltage in the down mode, and a second internal step-down unit for stopping the output of the internal operating voltage in the self-refresh mode of the integrated circuit And parts, which is constituted by the third internal step-down unit for outputting a constant internal operating voltage. Therefore, during the standby state of the integrated circuit, the output of the internal operating voltage from the internal step-down circuit is stopped, and the internal operating voltage output of each internal step-down unit is also stopped according to each mode, and the current consumption is particularly suppressed as much as possible. In the case of a desired power-down mode or self-refresh mode, the current consumption of the internal step-down circuit and the internal step-down unit can be reduced.
In the self-refresh mode, the internal step-down circuit has a period during which the output of the internal operation voltage is stopped and a period during which the internal operation voltage for refreshing the storage element is output. The internal step-down circuit stops the output of the internal operation voltage in the power down mode when the integrated circuit is operating. In the non-power-down mode, the internal step-down circuit stops outputting the internal operating voltage, and all the plurality of internal step-down units output the internal operating voltage in the non-power-down mode. Things. In the power down mode, the first internal step-down unit stops outputting the internal operation voltage, and the second and third internal step-down units output the internal operation voltage. In the self-refresh mode, the first and second internal step-down units stop outputting the internal operation voltage, and only the third internal step-down unit outputs the internal operation voltage. Further, the internal operating voltage is supplied only to a desired first-stage circuit among the first-stage circuits in accordance with the operation state and each mode at the time of standby. Also, the internal step-down circuit
Is the refresh of the storage element in the self-refresh mode.
Outputs the internal operating voltage during refresh, and
To temporarily increase the supply capacity.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an example of the semiconductor integrated circuit according to the present invention. In FIG. 1, this integrated circuit performs input / output of an internal step-down power supply circuit 1 for stepping down a power supply voltage VCC supplied from the outside, and addresses A0 to A10 and data DO0 to DO15 accessed from an external CPU, for example. A first stage circuit 2 and a dynamic RA for storing and reading data by access from the first stage circuit 2
And a memory circuit 3 such as M.

The internal step-down power supply circuit 1 receives a power supply voltage VCC and a ground voltage VSS applied from the outside, reduces the power supply voltage VCC, and supplies the reduced voltage to the first-stage circuit 2 and the memory circuit 3. When this stepped-down voltage is applied, the first-stage circuit 2 outputs a chip enable signal CS (bar), a write signal WE (bar), an address A0 to A10, and a column and row address among addresses A0 to A10 provided from an external CPU. Strobe signal CAS specifying
, RAS, clock CLK, clock enable signal WLE, and data DO0 to DO15 are output to the memory circuit 3. As a result, data is written to the corresponding address of the memory circuit 3. In addition, in the read mode in which the write signal WE (bar) is at the “H” level, data at the corresponding address is read from the memory circuit 3 and output to the outside via the first-stage circuit 2.

FIG. 3 is a circuit diagram showing an example of the first stage circuit 2. In the first stage circuit shown in FIG. 3A, when an external address or data is given as an external signal Vin1, a signal Vout is output from a transistor Q52. As memory circuit 3
Output to Here, when the integrated circuit is in a non-operating state and enters a power down mode described later, the step-down voltage VINT from the internal step-down power supply circuit 1 is not output to this circuit. That is, when the clock enable signal CKE shown in FIG. 2 changes from “H” level indicating an enabled state to “L” level indicating a non-enabled state, the power down signal PWDNB changes to “L” level. As a result, power is not supplied to the first-stage circuit of FIG. 3A (that is, the step-down voltage VINT to the transistors Q55 and Q56), and the transistors Q55 and Q56 are also turned off. Therefore, data is not read from or written to the memory circuit 3.

On the other hand, in the first stage circuit shown in FIG. 3B, when an external clock CLK is given as an external signal Vin2, the transistor Q62 outputs the signal to the memory circuit 3 as a signal Vout. Here, when the integrated circuit is in a non-operation state and enters a self-refresh mode described later, the step-down voltage VINT from the internal step-down power supply circuit 1 is not output to this circuit. At this time, the transistors Q65 and Q66 are also turned off by the "L" level self-refresh signal SRSB. Therefore, in this case, the first stage circuit in FIG. 3B does not operate, and the clock CLK from the outside is not supplied to the memory circuit 3. For this reason, the memory circuit 3 refreshes itself and retains the stored contents.

As described above, the present semiconductor integrated circuit has an operating state and a standby state representing a non-operating state (standby mode). In the standby state, the power supply to the first-stage circuit 2 is stopped except for a part (clock CLK supply portion) of the power-down mode in FIG. 3A, and the self-refresh to stop the power supply to all the first-stage circuits. There is a mode mode. In addition, there is a non-power-down mode (non-power-down mode) in which power supply to the first-stage circuit 2 is not stopped as a standby state.

FIG. 1 is a circuit diagram showing a main part of the present semiconductor integrated circuit, and shows a configuration of an internal step-down power supply circuit 1 which steps down a power supply voltage supplied from the outside and supplies it to each part of the integrated circuit. . 1, the internal step-down power supply circuit 1 includes an internal step-down circuit A, an internal step-down circuit B1 (first internal step-down unit), an internal step-down circuit B2 (second internal step-down unit), and an internal step-down circuit B3 ( (Third internal step-down unit). The internal step-down circuit A has a differential amplifier type comparator 11, and the comparator 11 includes a differential pair of NMOS transistors Q11 and Q12, a constant current source NMOS transistor Q13, and a load current mirror PMOS transistor Q14, Q15. And the transistor Q
The internal step-down voltage VINT is applied to the gate of the transistor 11, and the reference voltage Vref is applied to the gate of the transistor Q12.

The transistor Q12 outputs a voltage from the drain according to the level difference between the two differential inputs. This voltage output is output as an internal step-down voltage VINT by the PMOS transistor Q16,
Is fed back to the gate. The reference voltage Vref is also applied to the gate of the transistor Q13, so that a constant current is output. NMOS transistor Q17, Q19 are connected in series with transistor Q13, respectively.
The gates of the transistors Q17 and Q19 are turned on / off by a control signal ACT indicating the operation state of the integrated circuit and a power down signal PWDNB, respectively, so that the output current of the transistor Q13 is turned on / off.

Therefore, when the integrated circuit is operating, internal control circuit A applies a reduced voltage VINT to first stage circuit 2 because control signal ACT and power down signal PWDNB are both supplied as "H" level signals. The supply state is activated. In addition, when the integrated circuit is in the standby state, the control signal ACT of “L” level is externally supplied, so that the first stage circuit 2 is in the inactive state in which the step-down voltage VINT is not supplied. Note that the control signal ACT indicating the operation state of the integrated circuit is externally supplied as shown in FIG.
Chip enable signal CS (bar), write signal WE
(Bar), the strobe signals CAS (bar), RAS (bar), and the like are supplied to the internal voltage down converter A when they become active.

Next, the internal step-down circuit B1 similarly has a differential amplifier type comparator 21, and the comparator 21 is composed of a differential pair of NMOS transistors Q21 and Q22.
, A constant current source NMOS transistor Q23, and load current mirror PMOS transistors Q24 and Q25. Then, the internal step-down voltage VINT is applied to the gate of the transistor Q21, and the reference voltage Vref is applied to the gate of the transistor Q22.

The transistor Q22 outputs a voltage from the drain according to the level difference between the two differential inputs. This voltage output is output as the internal step-down voltage VINT by the PMOS transistor Q26,
Is fed back to the gate. The reference voltage Vref is also applied to the gate of the transistor Q23, so that a constant current is output. An NMOS transistor Q27 is connected in series to the transistor Q23, and the gate of the transistor Q27 is connected to the power down signal PWD.
By turning on / off by NB, the transistor Q2
3 is turned on and off. Therefore, the internal step-down circuit B1 outputs “H” even when the integrated circuit is in the standby state.
When the power down signal PWDNB at the level is applied, and therefore, in the non-power down mode, the first stage circuit 2 is activated to supply the step-down voltage VINT. When the power down signal PWDNB goes to the “L” level,
As described in (a), the step-down voltage VINT is supplied to the first stage circuit 2.
Do not supply.

Next, the internal step-down circuit B2 has the same configuration as the internal step-down circuit B1, except that the gate of the transistor Q27 is turned on / off by the self-refresh signal SRSB. Therefore, the internal step-down circuit B2 outputs "H".
When self-refresh signal SRSB at the level is externally applied, first stage circuit 2 is activated to supply stepped-down voltage VINT. Here, when the self-refresh signal SRSB goes to the “L” level and enters the self-refresh mode, the first-stage circuit 2 is turned on as described with reference to FIG.
Does not supply the step-down voltage VINT to The self-refresh signal SRSB is such that the clock enable signal CKE, the chip enable signal CS (bar), and the strobe signals CAS (bar) and RAS (bar) provided from the outside are both at the “L” level, and the write signal WE (bar). ) Goes to the “H” level, and then goes to the “L” level.

Next, the internal step-down circuit B3 also has a differential amplifier type comparator 41, which is a differential pair of NMOS transistors Q41 and Q42.
And a constant current source NMOS transistor Q43 and load current mirror PMOS transistors Q44 and Q45. The internal step-down voltage VINT is applied to the gate of the transistor Q41, and the reference voltage Vref is applied to the gate of the transistor Q42.

The transistor Q42 outputs a voltage from the drain according to the level difference between the two differential inputs. This voltage output is output as the internal step-down voltage VINT by the PMOS transistor Q46,
Is fed back to the gate. The reference voltage Vref is also applied to the gate of the transistor Q43, and a constant current is output. The internal step-down circuit B3 is not controlled by the external power-down signal PWDNB or the self-refresh signal SRSB, and thus is always in an active state of outputting the step-down voltage VINT.

As described above, according to the present invention, when the integrated circuit is to be operated, the control signal ACT, the power down signal PWDNB, and the self refresh signal SRS are externally supplied.
B are both supplied as "H" level signals, and the internal voltage down converters A and B1 to B3 are activated to supply the reduced voltage VINT to the first stage circuit 2. In this case, the sum of the current consumed by each internal voltage down converter is about 2.1 mA. Also,
When the integrated circuit is to be placed in the standby state and the non-power-down mode, only the control signal ACT is externally given as “L” level, only the internal voltage down circuit A is inactivated, and the voltage is reduced from each of the internal voltage down circuits B1 to B3. Voltage VI
NT is supplied to the first stage circuit 2. In this case, the sum of the current consumed by each of the internal step-down circuits B1 to B3 is about 100 μA.
It is.

Next, when the integrated circuit is to be set to the standby state and the power down mode, a control signal A
Both the CT and the power down signal PWDNB are supplied as “L” level, and the internal voltage down converters A and B1 are deactivated. Therefore, in this case, the step-down voltage VINT is supplied to the first stage circuit 2 from each of the active internal step-down circuits B2 and B3. In this case, the sum of the currents consumed by the internal voltage down converters B2 and B3 is about 20 μA. Next, when it is desired to set the integrated circuit in the power down mode and the self refresh mode in the standby state, the control signal ACT, the power down signal PWDNB, and the self refresh signal SRSB are both externally applied as “L” level, and the internal step-down circuit is provided. A, B1, and B2 are deactivated. Therefore, in this case, the step-down voltage VINT is supplied to the first-stage circuit 2 only from the internal step-down circuit B3. In this case, the current consumed by the internal step-down circuit B3 is about 5 μA.

In the self-refresh mode, as described above, the memory circuit 3 internally performs a self-refresh according to a predetermined timing in order to retain its own stored contents. This self-refresh is performed every about 10 μS as shown in FIG. 5, and at the time of this refresh, the internal step-down circuit A is activated to increase the supply capability of the internal step-down power supply VINT. As a result, the current consumption in the internal step-down circuit is increased from 5 μA, but the refresh time is about 50 nS, which is の of the refresh interval of about 10 μS.
Since it is 00, the increasing current consumption is a negligible value.

As described above, according to the present invention, a plurality of internal step-down circuits are provided for stepping down an external power supply and supplying the steps to an integrated circuit.
Each internal step-down circuit is activated according to each application. Therefore, it is possible to prevent the internal voltage down converter from consuming more current than necessary when the integrated circuit is in the standby state. As a result, it is possible to reduce the current consumption when the integrated circuit is not operating.

FIG. 4 is a diagram showing an example of a state transition of the present integrated circuit. When the integrated circuit is in the operating state, each of the internal step-down circuits A, B1 to B3 is activated. Here, when the control signal ACT is set to the “L” level, a standby state of a non-power down mode in which only the internal voltage down converter A is inactivated is set. In this state, when the control signal ACT is set to "H" level, all the internal step-down circuits are activated and shift to the operating state again.

When the clock enable signal CKE shown in FIG. 2 is changed from the "H" level in the enabled state to the "L" level in the non-enabled state in the standby state, the power down signal PWDNB is set to "L" as described above. Level, the internal step-down circuits B1, B
Only 2 is in a standby state in a power down mode in which it is activated. When the clock enable signal CKE is set to “H” level in the power-down mode with such low current consumption, the state shifts to the standby state in the non-power-down mode, and when the control signal ACT is set to “H” level, all the signals are turned off. The internal step-down circuit is activated and shifts to the operating state again. Therefore, in order to shift from the power-down mode with low current consumption to the operation state, it is necessary to temporarily shift to the standby state in the non-power-down mode and then shift to the operation state.

On the other hand, when the clock enable signal CKE is changed from the enable state "H" level to the non-enable state "L" level while the integrated circuit is operating and the control signal ACT is maintained at the "H" level. Then, the internal voltage down converters A and B1 are deactivated, and only the internal voltage down converters B1 and B2 enter the standby state of the power down mode in which they are activated. Then, when the clock enable signal CKE is set to the “H” level in this state, all the internal voltage down converters are activated and shift to the operating state again. Therefore, a transition can be made in one step between the low power consumption mode and the operating state by controlling the clock enable signal CKE (ie, controlling the power down signal PWDNB). That is, it is possible to directly shift from the operation state to the standby state with low current consumption, and to immediately shift from the standby state with low current consumption to the operation state in which all the internal voltage down converters are activated. As a result, the memory circuit 3 inside the integrated circuit can be immediately accessed from outside via the first-stage circuit 2.

[0029]

As described above, according to the present invention, the internal power supply is stepped down to output the internal operating voltage when the integrated circuit is operating, and the internal operating voltage is stopped when the integrated circuit is in the standby state. A step-down circuit, and a plurality of step-down circuits for stepping down an external power supply during an operation state of the integrated circuit to output an internal operation voltage to each unit, and stopping output of the internal operation voltage to each unit according to each mode in a standby state of the integrated circuit. Since an internal step-down unit is provided, the output of the internal operating voltage of the internal step-down circuit is stopped during the standby state of the integrated circuit, and the internal operating voltage output of each internal step-down unit is also stopped according to each mode. The current consumption of the internal step-down circuit and the internal step-down unit when the integrated circuit is not operating can be reduced. In addition, a plurality of internal step-down units are configured to stop outputting an internal operating voltage when the integrated circuit is in a power down mode, and a second internal step-down unit is configured to stop outputting the internal operating voltage when the integrated circuit is in a self-refresh mode. Since it is composed of an internal voltage step-down unit and a third internal voltage step-down unit that constantly outputs an internal operation voltage, the internal voltage step-down circuit can be used in a standby state, especially in a power-down mode or a self-refresh mode in which current consumption is to be minimized. And the current consumption of the internal step-down unit can be reduced. In the non-power-down mode, the internal step-down unit is in an activated state for outputting the internal operating voltage. Therefore, when the integrated circuit is activated, only the internal step-down circuit needs to be activated. Can be immediately shifted to the operating state, and each unit in the integrated circuit can be quickly accessed from outside. In addition, since the internal step-down circuit stops outputting the operation voltage based on the signal indicating the power down mode in the operation state of the integrated circuit, when the integrated circuit enters the standby state, the internal step-down signal is quickly reduced by the power down signal. The current consumption can be reduced by deactivating the circuit and the internal step-down unit. When the integrated circuit is activated, the internal step-down circuit and the internal step-down unit can be immediately activated by the non-power-down signal. Can access each part in the integrated circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an internal step-down circuit showing a main part of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit.

FIG. 3 is a circuit diagram illustrating an example of a first-stage circuit forming a semiconductor integrated circuit;

FIG. 4 is a diagram showing a state transition of the semiconductor integrated circuit.

FIG. 5 is a diagram showing the timing of self-refresh of a memory circuit forming a semiconductor integrated circuit.

FIG. 6 is a circuit diagram of a conventional internal voltage down converter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Internal step-down power supply circuit, 2 ... First stage circuit, 3 ... Memory circuit, 11, 21, 31, 41 ... Comparator, Q11-
Q19, Q21-Q28, Q31-Q38, Q41-Q
46, Q51 to Q56, Q61 to Q66 ... transistors, IN1, IN2 ... inverters.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/4074 G11C 11/406

Claims (10)

(57) [Claims] 1. A semiconductor integrated circuit which steps down an external power supply and supplies it as an internal operating voltage to internal parts including a first stage circuit, wherein the external power supply is stepped down to output the internal operating voltage when the semiconductor integrated circuit is in an operating state. An internal step-down circuit for stopping output of the internal operating voltage at least when the semiconductor integrated circuit is in a standby state, and stepping down an external power supply during the operation state of the semiconductor integrated circuit to output the internal operating voltage to each of the semiconductor integrated circuits; A plurality of internal step-down units for individually stopping the output of the internal operating voltage in accordance with each mode in the standby state of the circuit, wherein the plurality of internal step-down units are provided in the standby state of the semiconductor integrated circuit. A first mode for stopping the output of the internal operating voltage in a power down mode;
An internal step-down unit, a second internal step-down unit for stopping output of the internal operating voltage in a self-refresh mode during the standby state of the semiconductor integrated circuit, and a third internal step-down unit constantly outputting the internal operating voltage A semiconductor integrated circuit comprising: 2. The self-refresh mode according to claim 1 , wherein said internal step-down circuit operates in said self-refresh mode.
A period during which the output of the internal operating voltage is stopped and a period during which the internal operating voltage for refreshing the storage element is output. 3. The internal voltage down converter according to claim 1, wherein the internal step-down circuit has a function of transitioning between an operation state of the semiconductor integrated circuit and a power down mode during the standby state. A semiconductor integrated circuit which stops outputting an operating voltage. 4. The semiconductor integrated circuit according to claim 1, wherein an internal operation voltage output terminal of the internal voltage down converter and each of the internal operation voltage output terminals of the plurality of internal voltage down converters are connected in common. . 5. The semiconductor integrated circuit according to claim 1, wherein each of the modes in the standby state includes at least a non-power-down mode, a power-down mode, and a self-refresh mode. 6. The non-power-down mode according to claim 1, further comprising a non-power-down mode as the mode in the standby state.
The semiconductor integrated circuit according to claim 1, wherein the internal step-down circuit stops outputting an internal operating voltage, and all of the plurality of internal step-down units output an internal operating voltage. 7. The device according to claim 1, wherein in the power down mode, the first internal step-down unit stops outputting an internal operating voltage, and the second and third internal step-down units output an internal operating voltage. A semiconductor integrated circuit characterized by the above-mentioned. 8. The semiconductor device according to claim 1, wherein the first and second memory cells are in the self-refresh mode.
Wherein the internal step-down unit stops outputting the internal operating voltage and only the third internal step-down unit outputs the internal operating voltage. 9. The circuit according to claim 1, wherein the internal operating voltage is supplied to only a desired first-stage circuit among the first-stage circuits in accordance with an operation state and a mode in a standby state. A semiconductor integrated circuit characterized by the following. 10. The self-refresh mode according to claim 1, wherein said internal step-down circuit is in said self-refresh mode.
Output the internal operating voltage when refreshing the storage element
And temporarily increase the supply capacity of the internal operating voltage.
Characteristic semiconductor integrated circuit.